Started 3 mo 22 days ago
Took 47 min on green-dragon-03

Success Build rL:366732 - C:366719 - #63414 (Jul 22, 2019 1:04:20 PM)

Revisions
  • http://llvm.org/svn/llvm-project/llvm/trunk : 366732
  • http://llvm.org/svn/llvm-project/cfe/trunk : 366719
Changes
  1. [X86] When using AND+PACKUS in lowerV16I8Shuffle, generate the build vector directly in v16i8 with the correct 0x00 or 0xFF elements rather than using another VT and bitcasting it.

    The build_vector will become a constant pool load. By using the
    desired type initially, it ensures we don't generate a bitcast
    of the constant pool load which will need to be folded with
    the load.

    While experimenting with another patch, I noticed that when the
    load type and the constant pool type don't match, then
    SimplifyDemandedBits can't handle it. While we should probably
    fix that, this was a simple way to fix the issue I saw. (detail/ViewSVN)
    by ctopper
  2. [NFC][PowerPC]Change ADDIStocHA to ADDIStocHA8 to follow 64-bit naming convention

    Summary:

    Since we are planning to add ADDIStocHA for 32bit in later patch, we decided
    to change 64bit one first to follow naming convention with 8 behind opcode.

    Patch by: Xiangling_L

    Differential Revision: https://reviews.llvm.org/D64814 (detail/ViewSVN)
    by jasonliu

Started by an SCM change (2 times)

This run spent:

  • 8 min 32 sec waiting;
  • 47 min build duration;
  • 56 min total from scheduled to completion.
LLVM/Clang Warnings: 0 warnings.
  • No warnings since build 63,411.
  • Still 22 days before reaching the previous zero warnings highscore.
Test Result (no failures)