Test Result: 0 tests failing out of a total of 47,966 tests.100
Build stability: No recent builds failed.100
Build History
 Identified problems
 Identified problems
 Identified problems


rL:366832 - C:366831 - #63440 (Jul 23, 2019 11:30:08 AM)

  1. [Remarks] Add unit tests for YAML serialization

    Add tests for both the string table and non string table case. — thegameg / ViewSVN

rL:366829 - C:366831 - #63439 (Jul 23, 2019 10:52:24 AM)

  1. clang-format: Fix namespace end comments for namespaces with attributes and macros.

    Fixes PR39247.

    While here, also make C++20 `namespace A::inline B::inline C` nested
    inline namespaced definitions work.

        #define DEPRECATE_WOOF [[deprecated("meow")]]

        namespace DEPRECATE_WOOF woof {
        void f() {}
        } // namespace DEPRECATE_WOOFwoof

        namespace [[deprecated("meow")]] woof {
          void f() {}
        } // namespace [[deprecated("meow")]]woof

        namespace woof::inline bark {
          void f() {}
        } // namespace woof::inlinebark

        #define DEPRECATE_WOOF [[deprecated("meow")]]

        namespace DEPRECATE_WOOF woof {
        void f() {}
        } // namespace woof

        namespace [[deprecated("meow")]] woof {
        void f() {}
        } // namespace woof

        namespace woof::inline bark {
        void f() {}
        } // namespace woof::inline bark

    (In addition to the fixed namespace end comments, also note the correct
    indent of the namespace contents.)

    Differential Revision: https://reviews.llvm.org/D65125 — nico / ViewSVN
  2. [IndVars] Fix a subtle bug in optimizeLoopExits

    The original code failed to account for the fact that one exit can have a pointer exit count without all of them having pointer exit counts.  This could cause two separate bugs:
    1) We might exit the loop early, and leave optimizations undone.  This is what triggered the assertion failure in the reported test case.
    2) We might optimize one exit, then exit without indicating a change.  This could result in an analysis invalidaton bug if no other transform is done by the rest of indvars.

    Note that the pointer exit counts are a really fragile concept.  They show up only when we have a pointer IV w/o a datalayout to provide their size.  It's really questionable to me whether the complexity implied is worth it. — reames / ViewSVN
  3. Improve clang-format-diff help output

    The description in clang-format-diff.py is more useful than the one
    in `clang-format-diff -h`, so use the same description in both places.

    Differential Revision: https://reviews.llvm.org/D64998 — nico / ViewSVN
  4. [IR][Verifier] Allow IntToPtrInst to be !dereferenceable

    Allow IntToPtrInst to carry !dereferenceable metadata tag.
    This is valid since !dereferenceable can be only be applied to
    pointer type values.

    Change-Id: If8a6e3c616f073d51eaff52ab74535c29ed497b4

    Subscribers: llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64954 — rtayl / ViewSVN
  5. [RISCV][NFC] Correct RUN in rvi-pseudos-invalid.s

    This test should test both riscv32 and riscv64. — lenary / ViewSVN

rL:366821 - C:366823 - #63438 (Jul 23, 2019 10:00:10 AM)

  1. [clang][NFCI] Fix random typos — jkorous / ViewSVN
  2. [CMake] Add -z defs on Solaris

    Like other ELF targets, shared objects should be linked with -z defs on Solaris.

    Tested on x86_64-pc-solaris2.11 and sparcv9-sun-solaris2.11.

    Differential Revision: https://reviews.llvm.org/D64484 — ro / ViewSVN
  3. [clang, test] Fix Clang :: Headers/max_align.c on 64-bit SPARC

    Clang :: Headers/max_align.c currently FAILs on 64-bit SPARC:

      error: 'error' diagnostics seen but not expected:
        File /vol/llvm/src/clang/dist/test/Headers/max_align.c Line 12: static_assert failed due to requirement '8 == _Alignof(max_align_t)' ""
      1 error generated.

    This happens because SuitableAlign isn't defined for SPARCv9 unlike SPARCv8
    (which uses the default of 64 bits).  gcc's sparc/sparc.h has

      #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64)

    This patch sets SuitableAlign to match and updates the corresponding testcase.

    Tested on sparcv9-sun-solaris2.11.

    Differential Revision: https://reviews.llvm.org/D64487 — ro / ViewSVN

rL:366819 - C:366818 - #63437 (Jul 23, 2019 9:22:41 AM)

  1. [GlobalISel][AArch64] Teach GISel to handle shifts in load addressing modes

    When we select the XRO variants of loads, we can pull in very specific shifts
    (of the size of an element). E.g.

    ldr x1, [x2, x3, lsl #3]

    This teaches GISel to handle these when they're coming from shifts

    This adds a new addressing mode function, `selectAddrModeShiftedExtendXReg`
    which recognizes this pattern.

    This also packs this up with `selectAddrModeRegisterOffset` into
    `selectAddrModeXRO`. This is intended to be equivalent to `selectAddrModeXRO`
    in AArch64ISelDAGtoDAG.

    Also update load-addressing-modes to show that all of the cases here work.

    Differential Revision: https://reviews.llvm.org/D65119 — paquette / ViewSVN
  2. [ASTImporter] Fix inequivalence of ClassTemplateInstantiations

    We falsely state inequivalence if the template parameter is a
    qualified/nonquialified template in the first/second instantiation.
    Also, different kinds of TemplateName should be equal if the template
    decl (if available) is equal (even if the name kind is different).

    Reviewers: a_sidorin, a.sidorin

    Subscribers: rnkovacs, dkrupp, Szelethus, gamesh411, cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D64241 — martong / ViewSVN
  3. [TargetLowering] SimplifyMultipleUseDemandedBits - add VECTOR_SHUFFLE support.

    If all the demanded elts are from one operand and are inline, then we can use the operand directly.

    The changes are mainly from SSE41 targets which has blendvpd but not cmpgtq, allowing the v2i64 comparison to be simplified as we only need the signbit from alternate v4i32 elements. — rksimon / ViewSVN

rL:366813 - C:366792 - #63435 (Jul 23, 2019 7:50:31 AM)

  1. [llvm-ar] Fix support for archives with members larger than 4GB

    llvm-ar outputs a strange error message when handling archives with
    members larger than 4GB due to not checking file size when passing the
    value as an unsigned 32 bit integer. This overflow issue caused
    malformed archives to be created.:


    This change allows for members above 4GB and will error in a case that
    is over the formats size limit, a 10 digit decimal integer.

    Differential Revision: https://reviews.llvm.org/D65093 — gbreynoo / ViewSVN
  2. [ARM][LowOverheadLoops] Fix branch target codegen
    While lowering test.set.loop.iterations, it wasn't checked how the
    brcond was using the result and so the wls could branch to the loop
    preheader instead of not entering it. The same was true for
    So brcond and br_cc and now lowered manually when using the hwloop
    intrinsics. During this we now check whether the result has been
    negated and whether we're using SETEQ or SETNE and 0 or 1. We can
    then figure out which basic block the WLS and LE should be targeting.

    Differential Revision: https://reviews.llvm.org/D64616 — sam_parker / ViewSVN
  3. Fix MSVC warning about extending a uint32_t shift result to uint64_t. NFCI. — rksimon / ViewSVN
  4. [SLPVectorizer] Revert local change that got accidently got committed in rL366799

    This wasn't part of D63281 — rksimon / ViewSVN
  5. Revert [RISCV] Re-enable rv32i-aliases-invalid.s test

    This reverts r366797 (git commit 53f9fec8e8b58f5a904bbfb4a1d648cde65aa860) — lenary / ViewSVN
  6. [NFC][InstCombine] Fixup commutative/negative tests with icmp preds in @llvm.umul.with.overflow tests — lebedevri / ViewSVN
  7. [InstSimplify][NFC] Tests for skipping 'div-by-0' checks before inverted @llvm.umul.with.overflow

    It would be already handled by the non-inverted case if we were hoisting
    the `not` in InstCombine, but we don't (granted, we don't sink it
    in this case either), so this is a separate case. — lebedevri / ViewSVN
  8. [NFC][PhaseOredering][SimplifyCFG] Add more runlines to umul.with.overflow tests

    This way it will be more obvious that the problem is both
    in cost threshold and in hardcoded benefit check,
    plus will show how the instsimplify cleans this all in the end. — lebedevri / ViewSVN
  9. [TargetLowering] Add SimplifyMultipleUseDemandedBits

    This patch introduces the DAG version of SimplifyMultipleUseDemandedBits, which attempts to peek through ops (mainly and/or/xor so far) that don't contribute to the demandedbits/elts of a node - which means we can do this even in cases where we have multiple uses of an op, which normally requires us to demanded all bits/elts. The intention is to remove a similar instruction - SelectionDAG::GetDemandedBits - once SimplifyMultipleUseDemandedBits has matured.

    The InstCombine version of SimplifyMultipleUseDemandedBits can constant fold which I haven't added here yet, and so far I've only wired this up to some basic binops (and/or/xor/add/sub/mul) to demonstrate its use.

    We do see a couple of regressions that need to be addressed:

        AMDGPU unsigned dot product codegen retains an AND mask (for ZERO_EXTEND) that it previously removed (but otherwise the dotproduct codegen is a lot better).

        X86/AVX2 has poor handling of vector ANY_EXTEND/ANY_EXTEND_VECTOR_INREG - it prematurely gets converted to ZERO_EXTEND_VECTOR_INREG.

    The code owners have confirmed its ok for these cases to fixed up in future patches.

    Differential Revision: https://reviews.llvm.org/D63281 — rksimon / ViewSVN

rL:366797 - C:366792 - #63434 (Jul 23, 2019 5:21:52 AM)

  1. [RISCV] Re-enable rv32i-aliases-invalid.s test

    We were getting test failures on some builders, which pointed to @LINE
    being an undefined variable. I think that these failures should have
    been fixed by https://reviews.llvm.org/rL366434, so I'm re-enabling the
    test. — lenary / ViewSVN
  2. [Object/ELF.h] - Improve testing of the fields in ELFFile<ELFT>::sections().

    This eliminates a one error untested and
    also introduces a error for one more possible case
    which lead to crash previously.

    Differential revision: https://reviews.llvm.org/D64987 — grimar / ViewSVN

rL:366794 - C:366792 - #63433 (Jul 23, 2019 4:36:33 AM)

  1. [yaml2obj] - Add a support for defining null sections in YAMLs.

    ELF spec shows (Figure 4-10: Section Header Table Entry:Index 0,
    that section header at index 0 (null section) can have sh_size and
    sh_link fields set to non-zero values.

    It says (https://docs.oracle.com/cd/E19683-01/817-3677/6mj8mbtc9/index.html):

    "If the number of sections is greater than or equal to SHN_LORESERVE (0xff00),
    this member has the value zero and the actual number of section header table
    entries is contained in the sh_size field of the section header at index 0.
    Otherwise, the sh_size member of the initial entry contains 0."


    "If the section name string table section index is greater than or equal to SHN_LORESERVE
    (0xff00), this member has the value SHN_XINDEX (0xffff) and the actual index of the section
    name string table section is contained in the sh_link field of the section header at index 0.
    Otherwise, the sh_link member of the initial entry contains 0."

    At this moment it is not possible to create custom section headers at index 0 using yaml2obj.

    This patch implements this.

    Differential revision: https://reviews.llvm.org/D64913 — grimar / ViewSVN

rL:366793 - C:366792 - #63432 (Jul 23, 2019 4:00:09 AM)

  1. [SLPVectorizer] Remove null-pointer test. NFCI.

    cast<CallInst> shouldn't return null and we dereference the pointer in a lot of other places, causing both MSVC + cppcheck to warn about dereferenced null pointers — rksimon / ViewSVN

rL:366790 - C:366792 - #63431 (Jul 23, 2019 3:25:52 AM)

  1. PlistDiagnostics Fix for compile warning (NFC). — balazske / ViewSVN

rL:366790 - C:366782 - #63430 (Jul 23, 2019 2:42:31 AM)

  1. [ARM] Rename NEONModImm to VMOVModImm. NFC

    Rename NEONModImm to VMOVModImm as it is used in both NEON and MVE. — dmgreen / ViewSVN

rL:366789 - C:366782 - #63429 (Jul 23, 2019 1:53:00 AM)

  1. [Attributor][NFC] Re-run clang-format on the Attributor.cpp — uenoku / ViewSVN
  2. [Attributor] Deduce "dereferenceable" attribute

    Deduce dereferenceable attribute in Attributor.

    These will be added in a later patch.
    * dereferenceable(_or_null)_globally (D61652)
    * Deduction based on load instruction (similar to D64258)

    Reviewers: jdoerfert, sstefan1

    Reviewed By: jdoerfert

    Subscribers: hiraditya, jfb, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64876 — uenoku / ViewSVN

rL:366787 - C:366782 - #63428 (Jul 23, 2019 1:18:12 AM)

  1. [llvm-objcopy] Allow strip symtab in executables and DSOs

    Re-commit of the patch after addressing -Wl,--emit-relocs case.
    Differential revision: https://reviews.llvm.org/D61672 — evgeny777 / ViewSVN
  2. Fix gold-plugin Windows build

    r365588 missed one instance of integer file descriptor use in
    gold-plugin.cpp. — kongyi / ViewSVN
  3. [yaml2elf] - Treat the SHN_UNDEF section as kind of regular section.

    We have a logic that adds a few sections implicitly.
    Though the SHT_NULL section with section number 0
    is an exception.

    In D64913 I want to teach yaml2obj to redefine the null section.
    And in this patch I add it to the sections list,
    to make it kind of a regular section.

    Differential revision: https://reviews.llvm.org/D65087 — grimar / ViewSVN

rL:366781 - C:366782 - #63427 (Jul 23, 2019 12:25:00 AM)

  1. [CrossTU] Added CTU argument to diagnostic consumer create fn.

    The PListDiagnosticConsumer needs a new CTU parameter that is passed
    through the create functions.

    Reviewers: NoQ, Szelethus, xazax.hun, martong

    Reviewed By: Szelethus

    Subscribers: rnkovacs, dkrupp, Szelethus, gamesh411, cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D64635 — balazske / ViewSVN

rL:366781 - C:366761 - #63426 (Jul 22, 2019 11:50:55 PM)

  1. [AMDGPU][NFC] Simplify test file for amdgcn intrinsics

    Summary: Remove unchecked attribute in the call site and use FileCheck String Substitution for `convergent` check.

    Reviewers: nhaehnle

    Reviewed By: nhaehnle

    Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64901 — uenoku / ViewSVN

rL:366779 - C:366761 - #63425 (Jul 22, 2019 10:36:56 PM)

  1. [DAGCombiner] Make ShrinkLoadReplaceStoreWithStore return an SDValue instead of an SDNode*. NFCI

    The function was calling getNode() on an SDValue to return and the
    caller turned the result back into a SDValue. So just return the
    original SDValue to avoid this. — ctopper / ViewSVN
  2. [DAGCombiner] Use SDNode::isOperandOf to simplify some code. NFCI — ctopper / ViewSVN

rL:366777 - C:366761 - #63424 (Jul 22, 2019 10:00:54 PM)

  1. [LLVM-C] Improve Bindings to The Internalize Pass

    Summary: Adds a binding to the internalize pass that allows the caller to pass a function pointer that acts as the visibility-preservation predicate.  Previously, one could only pass an unsigned value (not LLVMBool?) that directed the pass to consider "main" or not.

    Reviewers: whitequark, deadalnix, harlanhaskins

    Reviewed By: whitequark, harlanhaskins

    Subscribers: kren1, hiraditya, llvm-commits, harlanhaskins

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D62456 — codafi / ViewSVN

rL:366775 - C:366761 - #63423 (Jul 22, 2019 8:54:05 PM)

  1. [PowerPC] Replace float load/store pair with integer load/store pair when it's only used in load/store

    Replace float load/store pair with integer load/store pair when it's only used in load/store,
    because float load/store instructions cost more cycles then integer load/store.

    A typical scenario is when there is a call with more than 13 float arguments passing, we need pass them by stack.
    So we need a load/store pair to do such memory operation if the variable is global variable.

    Differential Revision: https://reviews.llvm.org/D64195 — wuzish / ViewSVN

rL:366773 - C:366761 - #63421 (Jul 22, 2019 8:00:53 PM)

  1. Move variable out from debug only section.

    MFI is no longer just needed for an assert.  Move it out of the debug only
    section to allow non-assert builds to be able to find it. — rtrieu / ViewSVN

rL:366772 - C:366761 - #63420 (Jul 22, 2019 5:45:53 PM)

  1. [llvm-lipo] Implement -info

    Prints architecture type of all input files.

    Patch by Anusha Basana <anusha.basana@gmail.com>

    Differential Revision: https://reviews.llvm.org/D64668 — smeenai / ViewSVN

rL:366769 - C:366761 - #63419 (Jul 22, 2019 5:19:26 PM)

  1. Fixing build error from commit 95cbc3d

    [Attributor] Liveness analysis.

    Liveness analysis abstract attribute used to indicate which BasicBlocks are dead and can therefore be ignored.
    Right now we are only looking at noreturn calls.

    Reviewers: jdoerfert, uenoku

    Subscribers: hiraditya, llvm-commits

    Differential Revision: https://reviews.llvm.org/D64162 — sstefan / ViewSVN
  2. [Statepoints] Fix a bug in statepoint lowering for functions w/no-realign-stack

    We were silently using the ABI alignment for all of the stores generated for deopt and gc values.  We'd gotten the alignment of the stack slot itself properly reduced (via MachineFrameInfo's clamping), but having the MMO on the store incorrect was enough for us to generate an aligned store to a unaligned location.

    The simplest fix would have been to just pass the alignment to the helper function, but once we do that, the helper function doesn't really help.  So, inline it and directly call the MMO version of DAG.getStore with a properly constructed MMO.

    Note that there's a separate performance possibility here.  Even if we *can* realign stacks, we probably don't *want to* if all of the stores are in slowpaths.  But that's a later patch, if at all.  :) — reames / ViewSVN
  3. Fix pointer width in test from r366754. — pcc / ViewSVN
  4. gn build: Wrap two comments to 80 columns — nico / ViewSVN
  5. [DWARF] Add more error handling to debug line parser.

    This patch exnteds the error handling in the debug line parser to get
    rid of the existing MD5 assertion. I want to reuse the debug line parser
    from LLVM in LLDB where we cannot crash on invalid input.

    Differential revision: https://reviews.llvm.org/D64544 — jdevlieghere / ViewSVN

rL:366760 - C:366761 - #63418 (Jul 22, 2019 4:15:41 PM)

  1. [NFC][clang] Refactor getCompilationPhases()+Types.def step 1.

    Moves list of phases into Types.def table: Currently Types.def contains a
    table of strings that are used to assemble a list of compilation phases to be
    setup in the clang driver's jobs pipeline. This change makes it so that the table
    itself contains the list of phases. A subsequent patch will remove the strings.

    Differential Revision: https://reviews.llvm.org/D64098 — zer0 / ViewSVN
  2. [Statepoints] Add a test which shows a miscompile with no-realign-stacks — reames / ViewSVN
  3. Revert "Fixing build error from commit 9285295."

    This reverts commit 95cbc3da8871f43c1ce2b2926afaedcd826202b1. — sstefan / ViewSVN

rL:366755 - C:366744 - #63417 (Jul 22, 2019 3:46:46 PM)

  1. llvm-objcopy/test: add REQUIRES: shell for use of umask

    (follow-up to r365162) — dblaikie / ViewSVN
  2. Analysis: Don't look through aliases when simplifying GEPs.

    It is not safe in general to replace an alias in a GEP with its aliasee
    if the alias can be replaced with another definition (i.e. via strong/weak
    resolution (linkonce_odr) or via symbol interposition (default visibility
    in ELF)) while the aliasee cannot. An example of how this can go wrong is
    in the included test case.

    I was concerned that this might be a load-bearing misoptimization (it's
    possible for us to use aliases to share vtables between base and derived
    classes, and on Windows, vtable symbols will always be aliases in RTTI
    mode, so this change could theoretically inhibit trivial devirtualization
    in some cases), so I built Chromium for Linux and Windows with and without
    this change. The file sizes of the resulting binaries were identical, so it
    doesn't look like this is going to be a problem.

    Differential Revision: https://reviews.llvm.org/D65118 — pcc / ViewSVN
  3. Fixing build error from commit 9285295.

    [Attributor] Liveness analysis.

    Liveness analysis abstract attribute used to indicate which BasicBlocks are dead and can therefore be ignored.
    Right now we are only looking at noreturn calls.

    Reviewers: jdoerfert, uenoku

    Subscribers: hiraditya, llvm-commits

    Differential revision: https://reviews.llvm.org/D64162 — sstefan / ViewSVN
  4. [NFC][PatternMatch] Refactor code into a proper "matcher for any integral constant"

    Having it as a proper matcher is better for reusability elsewhere
    (in a follow-up patch.) — lebedevri / ViewSVN
  5. [InstSimplify][NFC] Tests for skipping 'div-by-0' checks before @llvm.umul.with.overflow

    These may remain after @llvm.umul.with.overflow was canonicalized
    from the code that was originally doing the check via division. — lebedevri / ViewSVN
  6. [SimplifyCFG][NFC] Test that we fail to flatten CFG in JPEG "sign" value extend pattern

    This comes up in JPEG decoding, see e.g.
    Figure F.12 – Extending the sign bit of a decoded value in V
    of ITU T.81 (JPEG specification). — lebedevri / ViewSVN
  7. [SimplifyCFG][NFC] Test that we fail to flatten CFG after forming @llvm.umul.with.overflow

    Even if we formed @llvm.umul.with.overflow, we are still stuck
    with that guard against div-by-zero, which is no longer needed,
    because we didn't flatten the CFG. — lebedevri / ViewSVN
  8. [InstCombine][NFC] Tests for canonicalization of unsigned multiply overflow check — lebedevri / ViewSVN
  9. [NFC][PhaseOrdering] Add tests showcasing the problems of unsigned multiply overflow check

    While we can form the @llvm.mul.with.overflow easily,
    we are still left with that check that was guarding against div-by-0.
    And in the second case we won't even flatten the CFG. — lebedevri / ViewSVN
  10. [IndVarSimplify][NFC] Autogenerate check lines in loop_evaluate_1.ll

    Being affected by upcoming patch. — lebedevri / ViewSVN
  11. [Driver] Set the default win32-macho debug format to DWARF


    Differential Revision: https://reviews.llvm.org/D65116 — vedantk / ViewSVN
  12. AMDGPU: Don't use SDNodeXForm for DS offset output

    The xform has no real valuewhen it's using out of a complex pattern
    output. The complex pattern was already creating TargetConstants with
    i16, so this was just unnecessary machinery.

    This allows global isel to import the simple cases once the complex
    pattern is implemented. — arsenm / ViewSVN

rL:366737 - C:366719 - #63416 (Jul 22, 2019 2:07:34 PM)

  1. Temporarily Revert "[Attributor] Liveness analysis." as it's breaking the build.

    This reverts commit 9285295f75a231dc446fa7cbc10a0a391b3434a5. — echristo / ViewSVN

rL:366736 - C:366719 - #63415 (Jul 22, 2019 2:04:37 PM)

  1. [Attributor] Liveness analysis.

    Liveness analysis abstract attribute used to indicate which BasicBlocks are dead and can therefore be ignored.
    Right now we are only looking at noreturn calls.

    Reviewers: jdoerfert, uenoku

    Subscribers: hiraditya, llvm-commits

    Differential revision: https://reviews.llvm.org/D64162 — sstefan / ViewSVN

rL:366732 - C:366719 - #63414 (Jul 22, 2019 1:04:20 PM)

  1. [X86] When using AND+PACKUS in lowerV16I8Shuffle, generate the build vector directly in v16i8 with the correct 0x00 or 0xFF elements rather than using another VT and bitcasting it.

    The build_vector will become a constant pool load. By using the
    desired type initially, it ensures we don't generate a bitcast
    of the constant pool load which will need to be folded with
    the load.

    While experimenting with another patch, I noticed that when the
    load type and the constant pool type don't match, then
    SimplifyDemandedBits can't handle it. While we should probably
    fix that, this was a simple way to fix the issue I saw. — ctopper / ViewSVN
  2. [NFC][PowerPC]Change ADDIStocHA to ADDIStocHA8 to follow 64-bit naming convention


    Since we are planning to add ADDIStocHA for 32bit in later patch, we decided
    to change 64bit one first to follow naming convention with 8 behind opcode.

    Patch by: Xiangling_L

    Differential Revision: https://reviews.llvm.org/D64814 — jasonliu / ViewSVN

rL:366728 - C:366719 - #63413 (Jul 22, 2019 12:50:03 PM)

  1. [Attributor] NoAlias on return values.

    Porting function return value attribute noalias to attributor.
    This will be followed with a patch for callsite and function argumets.

    Reviewers: jdoerfert

    Subscribers: lebedev.ri, hiraditya, llvm-commits

    Differential Revision: https://reviews.llvm.org/D63067 — sstefan / ViewSVN
  2. Stubs out TLOF for AIX and add support for common vars in assembly output.

    Stubs out a TargetLoweringObjectFileXCOFF class, implementing only
    SelectSectionForGlobal for common symbols. Also adds an override of
    EmitGlobalVariable in PPCAIXAsmPrinter which adds a number of defensive errors
    and adds support for emitting common globals. — sfertile / ViewSVN
  3. [SafeStack] Insert the deref after the offset

    While debugging code that uses SafeStack, we've noticed that LLVM
    produces an invalid DWARF. Concretely, in the following example:

      int main(int argc, char* argv[]) {
        std::string value = "";
        printf("%s\n", value.c_str());
        return 0;

    DWARF would describe the value variable as being located at:

      DW_OP_breg14 R14+0, DW_OP_deref, DW_OP_constu 0x20, DW_OP_minus

    The assembly to get this variable is:

      leaq    -32(%r14), %rbx

    The order of operations in the DWARF symbols is incorrect in this case.
    Specifically, the deref is incorrect; this appears to be incorrectly
    re-inserted in repalceOneDbgValueForAlloca.

    With this change which inserts the deref after the offset instead of
    before it, LLVM produces correct DWARF:

      DW_OP_breg14 R14-32

    Differential Revision: https://reviews.llvm.org/D64971 — phosek / ViewSVN
  4. WholeProgramDevirt: Teach the pass to respect the global's alignment.

    The bytes inserted before an overaligned global need to be padded according
    to the alignment set on the original global in order for the initializer
    to meet the global's alignment requirements. The previous implementation
    that padded to the pointer width happened to be correct for vtables on most
    platforms but may do the wrong thing if the vtable has a larger alignment.

    This issue is visible with a prototype implementation of HWASAN for globals,
    which will overalign all globals including vtables to 16 bytes.

    There is also no padding requirement for the bytes inserted after the global
    because they are never read from nor are they significant for alignment
    purposes, so stop inserting padding there.

    Differential Revision: https://reviews.llvm.org/D65031 — pcc / ViewSVN
  5. [PowerPC] Fix comment on MO_PLT Target Operand Flag. [NFC]

    Patch by Xiangling Liao. — sfertile / ViewSVN
  6. [Object][XCOFF] Remove extra includes from XCOFF related files. [NFC]

    Differential Revision: https://reviews.llvm.org/D60885 — sfertile / ViewSVN
  7. LowerTypeTests: Teach the pass to respect global alignments.

    We were previously ignoring alignment entirely when combining globals
    together in this pass. There are two main things that we need to do here:
    add additional padding before each global to meet the alignment requirements,
    and set the combined global's alignment to the maximum of all of the original
    globals' alignments.

    Since we now need to calculate layout as we go anyway, use the calculated
    layout to produce GlobalLayout instead of using StructLayout.

    Differential Revision: https://reviews.llvm.org/D65033 — pcc / ViewSVN

rL:366712 - C:366719 - #63411 (Jul 22, 2019 11:04:40 AM)

  1. Adds support for formatting NS_CLOSED_ENUM and CF_CLOSED_ENUM alongside NS_ENUM and CF_ENUM.

    Addresses the formatting of NS_CLOSED_ENUM and CF_CLOSED_ENUM, introduced in Swift 5.


    typedef NS_CLOSED_ENUM(NSInteger, Foo){FooValueOne = 1, FooValueTwo,


    typedef NS_CLOSED_ENUM(NSInteger, Foo) {
      FooValueOne = 1,

    Contributed by heijink.

    Reviewers: benhamilton, krasimir

    Reviewed By: benhamilton

    Subscribers: cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D65012 — benhamilton / ViewSVN
  2. [SLPVectorizer] Fix some MSVC/cppcheck uninitialized variable warnings. NFCI. — rksimon / ViewSVN
  3. Revert "Reland [ELF] Loose a condition for relocation with a symbol"

    This reverts commit r366686 as it appears to be causing buildbot
    failures on sanitizer-x86_64-linux-android and sanitizer-x86_64-linux. — vlad.tsyrklevich / ViewSVN
  4. [OPENMP][MSVC]Enable /openmp[:experimental] to compile OpenMP.

    Mapped /openmp[:experimental] to -fopenmp option and /openmp- option to
    -fno-openmp — abataev / ViewSVN

rL:366695 - C:366699 - #63410 (Jul 22, 2019 9:00:56 AM)

  1. [X86] Remove const from some intrinsics that shouldn't have them — probinson / ViewSVN
  2. [clangd] Add dlog()s for SelectionTree, enabling -debug-only=SelectionTree.cpp

    SelectionTree is a RecursiveASTVisitor which processes getSourceRange() for
    every node. This is a lot of surface area with the AST, as getSourceRange()
    is specialized for *many* node types.
    And the resulting SelectionTree depends on the source ranges of many
    visited nodes, and the order of traversal.

    Put together, this means we really need a traversal log to debug when we
    get an unexpected SelectionTree. I've built this ad-hoc a few times, now
    it's time to check it in.

    Example output:
    D[14:07:44.184] Computing selection for </usr/local/google/home/sammccall/test.cc:1:7, col:8>
    D[14:07:44.184]  push: VarDecl const auto x = 42
    D[14:07:44.184]   claimRange: </usr/local/google/home/sammccall/test.cc:1:12, col:13>
    D[14:07:44.184]   push: NestedNameSpecifierLoc (empty NestedNameSpecifierLoc)
    D[14:07:44.184]   pop: NestedNameSpecifierLoc (empty NestedNameSpecifierLoc)
    D[14:07:44.184]   push: QualifiedTypeLoc const auto
    D[14:07:44.184]   pop: QualifiedTypeLoc const auto
    D[14:07:44.184]    claimRange: </usr/local/google/home/sammccall/test.cc:1:7, col:11>
    D[14:07:44.184]    hit selection: </usr/local/google/home/sammccall/test.cc:1:7, col:8>
    D[14:07:44.184]   skip: IntegerLiteral 42
    D[14:07:44.184]    skipped range = </usr/local/google/home/sammccall/test.cc:1:16>
    D[14:07:44.184]  pop: VarDecl const auto x = 42
    D[14:07:44.184]   claimRange: </usr/local/google/home/sammccall/test.cc:1:1, col:18>
    D[14:07:44.184]  skip: VarDecl int y = 43
    D[14:07:44.184]   skipped range = </usr/local/google/home/sammccall/test.cc:2:1, col:9>
    D[14:07:44.184] Built selection tree
      VarDecl const auto x = 42
         .QualifiedTypeLoc const auto


    Reviewers: hokein

    Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, kadircet, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D65073 — sammccall / ViewSVN

rL:366695 - C:366694 - #63409 (Jul 22, 2019 8:15:09 AM)

  1. TableGen: Support physical register inputs > 255

    This was truncating register value that didn't fit in unsigned char.
    Switch AMDGPU sendmsg intrinsics to using a tablegen pattern. — arsenm / ViewSVN
  2. [NFC] Relaxed regression tests for PR42665

    Following up on the buildbot failures, this commits relaxes some tests:
    instead of checking for specific IR output, it now ensures that the
    underlying issue (the crash), and only that, doesn't happen. — mantognini / ViewSVN
  3. [ARM][LowOverheadLoops] Revert remaining pseudos

    ARMLowOverheadLoops would assert a failure if it did not find all the
    pseudo instructions that comprise the hardware loop. Instead of doing
    this, iterate through all the instructions of the function and revert
    any remaining pseudo instructions that haven't been converted.

    Differential Revision: https://reviews.llvm.org/D65080 — sam_parker / ViewSVN

rL:366688 - C:366689 - #63408 (Jul 22, 2019 7:06:12 AM)

  1. [OPENMP]Add support for analysis of firstprivate variables.

    Firstprivate variables are the variables, for which the private copies
    must be created in the OpenMP regions and must be initialized with the
    original values. Thus, we must report if the uninitialized variable is
    used as firstprivate.

    Reviewers: NoQ

    Subscribers: guansong, jdoerfert, caomhin, kkwli0, cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D64765 — abataev / ViewSVN
  2. AMDGPU/GlobalISel: Fix broken tests — arsenm / ViewSVN

rL:366686 - C:366683 - #63407 (Jul 22, 2019 6:14:59 AM)

  1. Reland [ELF] Loose a condition for relocation with a symbol

    This patch was not the reason of the buildbot failure.

    Deleted code was introduced as a work around for a bug in the gold linker
    (http://sourceware.org/PR16794). Test case that was given as a reason for
    this part of code, the one on previous link, now works for the gold.
    This condition is too strict and when a code is compiled with debug info
    it forces generation of numerous relocations with symbol for architectures
    that do not have relocation addend.

    Reviewers: arsenm, espindola

    Reviewed By: MaskRay

    Differential Revision: https://reviews.llvm.org/D64327 — nikolaprica / ViewSVN
  2. AMDGPU/GlobalISel: Remove unnecessary code

    The minnum/maxnum case are dead, and the cvt is handled by the
    default. — arsenm / ViewSVN
  3. [ARM] Fix for MVE VPT block pass

    We need to ensure that the number of T's is correct when adding multiple
    instructions into the same VPT block.

    Differential revision: https://reviews.llvm.org/D65049 — dmgreen / ViewSVN
  4. Updated the signature for some stack related intrinsics (CLANG)

    Modified the intrinsics
    int_frameaddress & int_sponentry.
    This commit depends on the changes in rL366679

    Reviewed By: arsenm

    Differential Revision: https://reviews.llvm.org/D64563 — cdevadas / ViewSVN
  5. Revert the change to the [[nodiscard]] feature test macro value.

    This value only gets bumped once both P1301 and P1771 are implemented. — aaronballman / ViewSVN
  6. [X86] EltsFromConsecutiveLoads - support common source loads (REAPPLIED)

    This patch enables us to find the source loads for each element, splitting them into a Load and ByteOffset, and attempts to recognise consecutive loads that are in fact from the same source load.

    A helper function, findEltLoadSrc, recurses to find a LoadSDNode and determines the element's byte offset within it. When attempting to match consecutive loads, byte offsetted loads then attempt to matched against a previous load that has already been confirmed to be a consecutive match.

    Next step towards PR16739 - after this we just need to account for shuffling/repeated elements to create a vector load + shuffle.

    Fixed out of bounds load assert identified in rL366501

    Differential Revision: https://reviews.llvm.org/D64551 — rksimon / ViewSVN
  7. AMDGPU/GlobalISel: Fix tests without asserts

    The legality check is only done under NDEBUG, so the failure cases are
    different in a release build. — arsenm / ViewSVN
  8. Added address-space mangling for stack related intrinsics

    Modified the following 3 intrinsics:
    int_frameaddress & int_sponentry.

    Reviewed By: arsenm

    Differential Revision: https://reviews.llvm.org/D64561 — cdevadas / ViewSVN

rL:366678 - C:366672 - #63406 (Jul 22, 2019 5:41:16 AM)

  1. [X86][SSE] Add EltsFromConsecutiveLoads test case identified in rL366501

    Test case that led to rL366441 being reverted at rL366501 — rksimon / ViewSVN

rL:366677 - C:366672 - #63405 (Jul 22, 2019 5:05:55 AM)

  1. [yaml2obj] - Change how we handle implicit sections.

    Instead of having the special list of implicit sections,
    that are mixed with the sections read from YAML on late
    stages, I just create the placeholders and add them to
    the main sections list early.

    That allows to significantly simplify the code.

    Differential revision: https://reviews.llvm.org/D64999 — grimar / ViewSVN

rL:366671 - C:366672 - #63404 (Jul 22, 2019 3:13:10 AM)

  1. [AST] Treat semantic form of InitListExpr as implicit code in traversals

    In particular, do not traverse the semantic form if shouldVisitImplicitCode()
    returns false.

    This simplifies the common case of traversals, avoiding the need to
    worry about some expressions being traversed twice.

    No tests break after the change, the change would allow to simplify at
    least one of the usages, i.e. r366070 which had to handle this in

    Reviewers: gribozavr

    Reviewed By: gribozavr

    Subscribers: kadircet, cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D64762 — ibiryukov / ViewSVN
  2. Add location of SVN staging dir to git-llvm error output

    In pre-monorepo times the svn staging directory was `.git/svn`. The below error message wasn't mentioning the new name yet.

    Example before:
    Can't push git rev 104cfa289d9 because svn status is not empty:
    !     llvm/trunk/include/llvm

    Example after:
    Can't push git rev 104cfa289d9 because status in svn staging dir (.git/llvm-upstream-svn) is not empty:
    !     llvm/trunk/include/llvm

    Reviewers: mehdi_amini, jlebar, teemperor

    Reviewed By: mehdi_amini

    Subscribers: llvm-commits, #llvm

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D65038 — stefan.graenitz / ViewSVN
  3. [OpenCL] Improve destructor support in C++ for OpenCL

    This re-applies r366422 with a fix for Bug PR42665 and a new regression
    test. — mantognini / ViewSVN

rL:366669 - C:366663 - #63403 (Jul 22, 2019 2:35:54 AM)

  1. [IPRA][ARM] Make use of the "returned" parameter attribute

    ARM has code to recognise uses of the "returned" function parameter
    attribute which guarantee that the value passed to the function in r0
    will be returned in r0 unmodified. IPRA replaces the regmask on call
    instructions, so needs to be told about this to avoid reverting the

    Differential revision: https://reviews.llvm.org/D64986 — ostannard / ViewSVN

rL:366668 - C:366663 - #63402 (Jul 22, 2019 1:10:58 AM)

  1. [llvm-readobj] - Stop using precompiled objects in file-headers.test

    This converts all sub-tests except one to YAML instead of precompiled inputs.

    Differential revision: https://reviews.llvm.org/D64800 — grimar / ViewSVN

rL:366667 - C:366663 - #63401 (Jul 22, 2019 12:20:57 AM)

  1. [AMDGPU] Save some work when an atomic op has no uses

    In the atomic optimizer, save doing a bunch of work and generating a
    bunch of dead IR in the fairly common case where the result of an
    atomic op (i.e. the value that was in memory before the atomic op was
    performed) is not used. NFC.

    Reviewers: arsenm, dstuttard, tpr

    Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, t-tye, hiraditya, jfb, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64981 — foad / ViewSVN

rL:366666 - C:366663 - #63400 (Jul 21, 2019 10:38:04 PM)

  1. [PowerPC][NFC] Precommit a test case where ppc-mi-peepholes miscompiles extswsli

    Added a test case to show codegen differences. — lkail / ViewSVN
  2. [Loop Peeling] Fix the handling of branch weights of peeled off branches.

    Current algorithm to update branch weights of latch block and its copies is
    based on the assumption that number of peeling iterations is approximately equal
    to trip count.

    However it is not correct. According to profitability check in one case we can decide to peel
    in case it helps to reduce the number of phi nodes. In this case the number of peeled iteration
    can be less then estimated trip count.

    This patch introduces another way to set the branch weights to peeled of branches.
    Let F is a weight of the edge from latch to header.
    Let E is a weight of the edge from latch to exit.
    F/(F+E) is a probability to go to loop and E/(F+E) is a probability to go to exit.
    Then, Estimated TripCount = F / E.
    For I-th (counting from 0) peeled off iteration we set the the weights for
    the peeled latch as (TC - I, 1). It gives us reasonable distribution,
    The probability to go to exit 1/(TC-I) increases. At the same time
    the estimated trip count of remaining loop reduces by I.

    As a result after peeling off N iteration the weights will be
    (F - N * E, E) and trip count of loop becomes
    F / E - N or TC - N.

    The idea is taken from the review of the patch D63918 proposed by Philip.

    Reviewers: reames, mkuper, iajbar, fhahn
    Reviewed By: reames
    Subscribers: hiraditya, zzheng, llvm-commits
    Differential Revision: https://reviews.llvm.org/D64235 — skatkov / ViewSVN

rL:366664 - C:366663 - #63399 (Jul 21, 2019 10:03:00 PM)

  1. [utils] Clean up UpdateTestChecks/common.py — maskray / ViewSVN

rL:366662 - C:366663 - #63398 (Jul 21, 2019 9:15:59 PM)

  1. [analyzer] Fix -Wunused-function in NDEBUG builds with #ifdef LLVM_DUMP_METHOD — maskray / ViewSVN

rL:366662 - C:366645 - #63397 (Jul 21, 2019 7:45:57 PM)

  1. [InstCombine] Add foldAndOfICmps test cases inspired by PR42691.

    icmp ne %x, INT_MIN can be treated similarly to icmp sgt %x, INT_MIN.
    icmp ne %x, INT_MAX can be treated similarly to icmp slt %x, INT_MAX.
    icmp ne %x, UINT_MAX can be treated similarly to icmp ult %x, UINT_MAX.

    We already treat icmp ne %x, 0 similarly to icmp ugt %x, 0 — ctopper / ViewSVN

rL:366661 - C:366645 - #63396 (Jul 21, 2019 2:34:17 PM)

  1. [PowerPC][NFC] Precomit test case for upcoming patch

    Just committing a test case for an upcoming patch so that the review can show
    only the codegen differences. — nemanjai / ViewSVN
  2. [X86] SimplifyDemandedVectorEltsForTargetNode - Move SUBV_BROADCAST narrowing handling. NFCI.

    Move the narrowing of SUBV_BROADCAST to where we handle all the other opcodes. — rksimon / ViewSVN

rL:366659 - C:366645 - #63395 (Jul 21, 2019 11:45:59 AM)

  1. [PowerPC][NFC] Regenerate test using script

    This test case ended up as a hybrid of generated checks and manually inserted
    checks. Regenerate using script to make it consistent. — nemanjai / ViewSVN

rL:366658 - C:366645 - #63394 (Jul 21, 2019 9:29:04 AM)

  1. [InstCombine] Update comment I missed in r366649. NFC — ctopper / ViewSVN
  2. [SmallBitVector] Fix bug in find_next_unset for small types with indices >=32

    We were creating a bitmask from a shift of unsigned instead of uintptr_t, meaning we couldn't create masks for indices above 31.

    Noticed due to a MSVC analyzer warning. — rksimon / ViewSVN
  3. [GISel]: Attach missing range metadata while translating G_LOADs


    Attach range information to G_LOAD when only defining one register.

    reviewed by: arsenm — aditya_nandakumar / ViewSVN

rL:366655 - C:366645 - #63393 (Jul 21, 2019 6:11:00 AM)

  1. [ARM] Move MVE VPT block tests into the Thumb2 directory. NFC — dmgreen / ViewSVN

rL:366652 - C:366645 - #63392 (Jul 21, 2019 2:28:39 AM)

  1. [NFC][InstCombine] Add a few extra srem-by-power-of-two tests - extra uses — lebedevri / ViewSVN

rL:366649 - C:366645 - #63391 (Jul 20, 2019 11:45:57 PM)

  1. [InstCombine] Remove insertRangeTest code that handles the equality case.

    For equality, the function called getTrue/getFalse with the VT
    of the comparison input. But getTrue/getFalse need the boolean VT.
    So if this code ever executed, it would assert.

    I believe these cases are removed by InstSimplify so we don't get here.

    So this patch just fixes up an assert to exclude the equality
    possibility and removes the broken code. — ctopper / ViewSVN

rL:366648 - C:366645 - #63390 (Jul 20, 2019 10:30:58 PM)

  1. [InstCombine] Don't use AddOne/SubOne to see if two APInts are 1 apart. Use APInt operations instead. NFCI

    AddOne/SubOne create new Constant objects. That seems heavy for
    comparing ConstantInts which wrap APInts. Just do the math on
    on the APInts and compare them. — ctopper / ViewSVN

rL:366646 - C:366645 - #63389 (Jul 20, 2019 5:29:58 PM)

  1. gn build: Merge r366622 — nico / ViewSVN

rL:366643 - C:366645 - #63388 (Jul 20, 2019 4:21:07 PM)

  1. [Clang] Replace cc1 options '-mdisable-fp-elim' and '-momit-leaf-frame-pointer'
    with '-mframe-pointer'

    After D56351 and D64294, frame pointer handling is migrated to tri-state
    (all, non-leaf, none) in clang driver and on the function attribute.
    This patch makes the frame pointer handling cc1 option tri-state.

    Reviewers: chandlerc, rnk, t.p.northover, MaskRay

    Reviewed By: MaskRay

    Differential Revision: https://reviews.llvm.org/D56353 — yuanfang / ViewSVN

rL:366643 - C:366635 - #63387 (Jul 20, 2019 3:18:03 PM)

  1. [NFC][InstCombine] Autogenerate a few tests — lebedevri / ViewSVN
  2. [NFC][InstCombine] Add srem-by-signbit tests - still can fold to bittest

    https://rise4fun.com/Alive/IIeS — lebedevri / ViewSVN

rL:366640 - C:366635 - #63386 (Jul 20, 2019 12:31:02 PM)

  1. [NFC][Codegen][X86][AArch64] Add "(x s% C) == 0" tests

    Much like with `urem`, the same optimization (albeit with slightly
    different algorithm) applies for the signed case, too.

    I'm simply copying the test coverage from `urem` case for now,
    i believe it should be (close to?) sufficient. — lebedevri / ViewSVN

rL:366637 - C:366635 - #63385 (Jul 20, 2019 9:36:03 AM)

  1. [Codegen][SelectionDAG] X u% C == 0 fold: non-splat vector improvements

    Four things here:
    1. Generalize the fold to handle non-splat divisors. Reasonably trivial.
    2. Unban power-of-two divisors. I don't see any reason why they should
       be illegal.
       * There is no ban in Hacker's Delight
       * I think the ban came from the same bug that caused the miscompile
          in the base patch - in `floor((2^W - 1) / D)` we were dividing by
          `D0` instead of `D`, and we **were** ensuring that `D0` is not `1`,
          which made sense.
    3. Unban `1` divisors. I no longer believe Hacker's Delight actually says
       that the fold is invalid for `D = 0`. Further considerations:
       * We know that
         * `(X u% 1) == 0`  can be constant-folded to `1`,
         * `(X u% 1) != 0`  can be constant-folded to `0`,
       *  Also, we know that
         * `X u<= -1` can be constant-folded to `1`,
         * `X u>  -1` can be constant-folded to `0`,
       * https://godbolt.org/z/7jnZJX https://rise4fun.com/Alive/oF6p
       * We know will end up with the following:
           `(setule/setugt (rotr (mul N, P), K), Q)`
       * Therefore, for given new DAG nodes and comparison predicates
         (`ule`/`ugt`), we will still produce the correct answer if:
         `Q` is a all-ones constant; and both `P` and `K` are *anything*
         other than `undef`.
       * The fold will indeed produce `Q = all-ones`.
    4. Try to re-splat the `P` and `K` vectors - we don't care about
       their values for the lanes where divisor was `1`.

    Reviewers: RKSimon, hermord, craig.topper, spatel, xbolva00

    Reviewed By: RKSimon

    Subscribers: hiraditya, javed.absar, dexonsmith, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D63963 — lebedevri / ViewSVN

rL:366633 - C:366635 - #63383 (Jul 20, 2019 7:51:52 AM)

  1. Fix cppcheck reduce scope variable warnings. NFCI

    Move a couple of variables inside the block where they are actually needed. — rksimon / ViewSVN

rL:366633 - C:366630 - #63382 (Jul 20, 2019 5:31:02 AM)

  1. [Local] Zap blockaddress without users in ConstantFoldTerminator.

    If the blockaddress is not destoryed, the destination block will still
    be marked as having its address taken, limiting further transformations.

    I think there are other places where the dead blockaddress constants are kept
    around, I'll look into that as follow up.

    Reviewers: craig.topper, brzycki, davide

    Reviewed By: brzycki, davide

    Differential Revision: https://reviews.llvm.org/D64936 — fhahn / ViewSVN

rL:366625 - C:366630 - #63381 (Jul 20, 2019 2:39:01 AM)

  1. [c++20] P1161R3: a[b,c] is deprecated. — rsmith / ViewSVN

rL:366625 - C:366629 - #63380 (Jul 20, 2019 2:04:12 AM)

  1. Mark P1301R4 in C++2a as being SVN instead. — aaronballman / ViewSVN

rL:366625 - C:366628 - #63379 (Jul 20, 2019 1:26:03 AM)

  1. We support P1301R4 in C++2a as of r366626. — aaronballman / ViewSVN
  2. [cxx_status] Update status page for WG21 Cologne meeting motions.

    Note that many of the paper links will be dead until the post-meeting
    mailing is released. — rsmith / ViewSVN

rL:366625 - C:366626 - #63378 (Jul 20, 2019 1:01:04 AM)

  1. Implement P1301R4, which allows specifying an optional message on the [[nodiscard]] attribute.

    This also bumps the attribute feature test value and introduces the notion of a C++2a extension warning. — aaronballman / ViewSVN

rL:366625 - C:366624 - #63377 (Jul 19, 2019 6:56:03 PM)

  1. [GlobalISel][AArch64] Contract trivial same-size cross-bank copies into G_STOREs

    Sometimes, you can end up with cross-bank copies between same-sized GPRs and
    FPRs, which feed into G_STOREs. When these copies feed only into stores, they
    aren't necessary; we can just store using the original register bank.

    This provides some minor code size savings for some floating point SPEC
    benchmarks. (Around 0.2% for 453.povray and 450.soplex)

    This issue doesn't seem to show up due to regbankselect or anything similar. So,
    this patch introduces an early select function, `contractCrossBankCopyIntoStore`
    which performs the contraction when possible. The selector then continues
    normally and selects the correct store opcode, eliminating needless copies
    along the way.

    Differential Revision: https://reviews.llvm.org/D65024 — paquette / ViewSVN

rL:366624 - C:366624 - #63376 (Jul 19, 2019 4:50:57 PM)

  1. [WebAssembly] Compute and export TLS block alignment

    Add immutable WASM global `__tls_align` which stores the alignment
    requirements of the TLS segment.

    Add `__builtin_wasm_tls_align()` intrinsic to get this alignment in Clang.

    The expected usage has now changed to:


    Reviewers: tlively, aheejin, sbc100, sunfish, alexcrichton

    Reviewed By: tlively

    Subscribers: dschuff, jgravelle-google, hiraditya, cfe-commits, llvm-commits

    Tags: #clang, #llvm

    Differential Revision: https://reviews.llvm.org/D65028 — quantum / ViewSVN

rL:366622 - C:366623 - #63375 (Jul 19, 2019 4:22:38 PM)

  1. [LTO] Always mark regular LTO units with EnableSplitLTOUnit=1

    Regular LTO modules do not need LTO Unit splitting, only ThinLTO does
    (they must be consistently split into regular and Thin units for
    optimizations such as whole program devirtualization and lower type
    tests). In order to avoid spurious errors from LTO when combining with
    split ThinLTO modules, always set this flag for regular LTO modules.

    Reviewers: pcc

    Subscribers: mehdi_amini, Prazek, inglorion, steven_wu, dexonsmith, cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D65009 — tejohnson / ViewSVN
  2. Re-commit: r366610 and r366612: Expand pseudo-components before embedding in llvm-config

    There were two main problems:
    * The 'nativecodegen' pseudo-component was unconditionally adding
      ${native_tgt}CodeGen even though it conditionally added ${native_tgt}Info and
      ${native_tgt}Desc. This has been fixed by making ${native_tgt}CodeGen
      conditional too
    * The 'all' pseudo-component was causing library names like LLVMLLVMDemangle as
      the expansion was to a library name and not a component. There doesn't seem to
      be a list of available components anywhere so this has been fixed by moving the
      expansion of 'all' back where it was before. This manifested in different ways
      on different builders but it was the same root cause — dsanders / ViewSVN

rL:366621 - C:366620 - #63374 (Jul 19, 2019 3:31:03 PM)

  1. AMDGPU/GlobalISel: Legalize GEP for other 32-bit address spaces — arsenm / ViewSVN

rL:366619 - C:366620 - #63373 (Jul 19, 2019 3:01:57 PM)

  1. [NFC] Remove unused variable

    Change-Id: I5aee24dcdf6eebfbf788e52be22463387f23d927 — dendibakh / ViewSVN
  2. [AMDGPU] Autogenerate register sequences in tuples

    Differential Revision: https://reviews.llvm.org/D65007 — rampitec / ViewSVN
  3. Disallow most calling convention attributes on PS4

    PS4 now only allows "cdecl", and its equivalent on PS4, "sysv_abi".

    Differential Revision: https://reviews.llvm.org/D64780 — ssrivastava / ViewSVN
  4. [AMDGPU] Fixed occupancy calculation for gfx10

    Differential Revision: https://reviews.llvm.org/D65010 — rampitec / ViewSVN

rL:366615 - C:366592 - #63372 (Jul 19, 2019 2:16:03 PM)

  1. Revert r366610 and r366612: Expand pseudo-components before embedding in llvm-config

    Some targets are missing LLVMDemangle, one is adding the LLVM prefix twice, and two
    are hitting the very error this patch fixes for my target. Reverting while I work
    through the reports. — dsanders / ViewSVN

rL:366614 - C:366592 - #63371 (Jul 19, 2019 2:11:04 PM)

  1. [InstCombine] Fix copy/paste mistake in the test cases I added for PR42691. NFC — ctopper / ViewSVN

rL:366613 - C:366592 - #63370 (Jul 19, 2019 2:06:04 PM)

  1. AMDGPU: Avoid custom predicates for stores with glue — arsenm / ViewSVN

rL:366612 - C:366592 - #63369 (Jul 19, 2019 2:01:05 PM)

  1. Fix a latent bug discovered by r366610: nativecodegen includes X86CodeGen when X86 is not compiled

    I believe this to have been a latent bug as the same expansion checks for the
    existence of ${native_tgt}Info and ${native_tgt}Desc and only adds them if
    they were compiled but unconditionally adds ${native_tgt}CodeGen.

    This should fix llvm-clang-x86_64-win-fast which builds ARM only on an X86 host and similar builders. — dsanders / ViewSVN

rL:366611 - C:366592 - #63368 (Jul 19, 2019 1:51:02 PM)

  1. [InstCombine] Add test cases for PR42691. NFC — ctopper / ViewSVN

rL:366610 - C:366592 - #63367 (Jul 19, 2019 1:46:12 PM)

  1. Expand pseudo-components before embedding in llvm-config

    If you use pseudo-targets like AllTargetsCodeGens in LLVM_DYLIB_COMPONENTS
    then a test will fail because `./bin/llvm-config --shared-mode` can't
    handle these targets. We can fix this by expanding them before embedding
    the string into llvm-config

    Reviewers: bogner

    Reviewed By: bogner

    Subscribers: mgorny, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D65011 — dsanders / ViewSVN
  2. AMDGPU: Redefine setcc condition PatLeafs

    Avoid using custom code predicates. — arsenm / ViewSVN

rL:366608 - C:366592 - #63366 (Jul 19, 2019 1:06:05 PM)

  1. AMDGPU: Don't rely on m0 being -1 for GWS offsets

    This only works if the high bits of m0 are also 0, so m0 would have to
    be set to 0xffff. — arsenm / ViewSVN

rL:366607 - C:366592 - #63365 (Jul 19, 2019 12:54:13 PM)

  1. AMDGPU: Force s_waitcnt after GWS instructions

    This is apparently required to be the immediately following
    instruction, so force it into a bundle with a waitcnt. — arsenm / ViewSVN

rL:366605 - C:366592 - #63364 (Jul 19, 2019 12:38:22 PM)

  1. LiveIntervals: Fix handleMove asserting on BUNDLE

    The top-level BUNDLE instruction should behave as an ordinary
    instruction. It is supposed to have all relevant registers as implicit
    operands. Moving it should work as any other instruction. I believe
    the assert intended to avoid moving instructions inside bundles. — arsenm / ViewSVN

rL:366603 - C:366592 - #63363 (Jul 19, 2019 12:09:10 PM)

  1. Revert "[libc++] Integrate the PSTL into libc++"

    This reverts r366593, which caused unforeseen breakage on the build bots.
    I'm reverting until the problems have been figured out and fixed. — ldionne / ViewSVN
  2. [AMDGPU] Add test case on crashing of `si-lower-sgpr-spills` pass

    Reviewers: arsenm

    Subscribers: qcolombet, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64273 — hliao / ViewSVN

rL:366600 - C:366592 - #63362 (Jul 19, 2019 11:42:31 AM)

  1. Revert "Use the MachineBasicBlock symbol for a callbr target"

    This reverts commit r366523/ccbffefccaff42b0d094c9ef0f49fc3e8c8456ea.

    Two regressions were immediately reported:
    - https://github.com/ClangBuiltLinux/linux/issues/614
    - https://github.com/ClangBuiltLinux/linux/issues/615

    Reported-by: nathanchance — nickdesaulniers / ViewSVN

rL:366599 - C:366592 - #63361 (Jul 19, 2019 11:12:04 AM)

  1. [RISCV] Disable tests failing on buildbots.

    r366399 enabled a couple tests that are failing on a few buildbots. — morehouse / ViewSVN
  2. [AMDGPU] Allow register tuples to set asm names

    This change reverts most of the previous register name generation.
    The real problem is that RegisterTuple does not generate asm names.
    Added optional operand to RegisterTuple. This way we can simplify
    register name access and dramatically reduce the size of static
    tables for the backend.

    Differential Revision: https://reviews.llvm.org/D64967 — rampitec / ViewSVN
  3. AMDGPU/GlobalISel: Fix MMO flags for kernel argument loads

    The DAG lowering sets dereferencable and invariant, not nontemporal. — arsenm / ViewSVN
  4. GlobalISel: Add GINodeEquiv for fcopysign

    I don't need this at the moment, but it should be here. — arsenm / ViewSVN

rL:366586 - C:366546 - #63358 (Jul 19, 2019 8:33:00 AM)

  1. AMDGPU: Attempt to fix bot error

    Manually remove file name from check line, since it somehow ends
    up being different on an msvc bot. — arsenm / ViewSVN
  2. AMDGPU/GlobalISel: Selection for fminnum/fmaxnum

    v2f16 case doesn't work yet because the VOP3P complex patterns haven't
    been ported yet. — arsenm / ViewSVN
  3. AMDGPU/GlobalISel: Support arguments with multiple registers

    Handles structs used directly in argument lists. — arsenm / ViewSVN

rL:366582 - C:366546 - #63357 (Jul 19, 2019 7:17:55 AM)

  1. AMDGPU/GlobalISel: Rewrite lowerFormalArguments

    This should now handle everything except structs passed as multiple

    I think most of the packing logic should be handled by
    handleAssignments, but I'm unclear on what the contract is for
    multiple registers. This is copying how x86 handles this.

    This does change the behavior of the test_sgpr_alignment0 amdgpu_vs
    test. I don't think shader arguments should try to follow the
    alignment, and registers need to be repacked. I also don't think it
    matters, since I think the pointers are packed to the beginning of the
    argument list anyway. — arsenm / ViewSVN
  2. AMDGPU: Decompose all values to 32-bit pieces for calling conventions

    This is the more natural lowering, and presents more opportunities to
    reduce 64-bit ops to 32-bit.

    This should also help avoid issues graphics shaders have had with
    64-bit values, and simplify argument lowering in globalisel. — arsenm / ViewSVN
  3. gn build: Set +x on symlink_or_copy.py — nico / ViewSVN
  4. DAG: Handle dbg_value for arguments split into multiple subregs

    This was handled previously for arguments split due to not fitting in
    an MVT. This was dropping the register for argument registers split
    due to TLI::getRegisterTypeForCallingConv. — arsenm / ViewSVN

rL:366572 - C:366546 - #63356 (Jul 19, 2019 6:26:25 AM)

  1. [NFC] include cstdint/string prior to using uint8_t/string

    Summary: include proper header prior to use of uint8_t typedef
    and std::string.

    Subscribers: llvm-commits

    Reviewers: cherry

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64937 — thanm / ViewSVN
  2. [AMDGPU][MC] Corrected parsing of branch offsets

    See bug 40820: https://bugs.llvm.org/show_bug.cgi?id=40820

    Reviewers: artem.tamazov, arsenm

    Differential Revision: https://reviews.llvm.org/D64629 — dpreobra / ViewSVN
  3. [MachineCSE][MachinePRE] Avoid hoisting code from code regions into hot BBs.

    Current PRE hoists common computations into
    CMBB = DT->findNearestCommonDominator(MBB, MBB1).
    However, if CMBB is in a hot loop body, we might get performance

    Differential Revision: https://reviews.llvm.org/D64394 — lkail / ViewSVN

rL:366569 - C:366546 - #63355 (Jul 19, 2019 5:56:06 AM)

  1. [X86] for split stack, not save/restore nested arg if unused

    For split-stack, if the nested argument (i.e. R10) is not used, no need to save/restore it in the prologue.

    Reviewers: thanm

    Reviewed By: thanm

    Subscribers: mstorsjo, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64673 — thanm / ViewSVN

rL:366565 - C:366546 - #63354 (Jul 19, 2019 4:33:44 AM)

  1. [NFC][InstCombine] Tests for 'rem' formation from sub-of-mul-by-'div' (PR42673)

    https://bugs.llvm.org/show_bug.cgi?id=42673 — lebedevri / ViewSVN
  2. [NFC][InstCombine] Redundant masking before left-shift: tests with assume

    If the legality check is `(shiftNbits-maskNbits) s>= 0`,
    then we can simplify it to `shiftNbits u>= maskNbits`,
    which is easier to check for.

    However, currently switching the `dropRedundantMaskingOfLeftShiftInput()`
    to `SimplifyICmpInst()` does not catch these cases and regresses
    currently-handled cases, so i'll leave it as is for now.

    https://rise4fun.com/Alive/25P — lebedevri / ViewSVN

rL:366563 - C:366546 - #63353 (Jul 19, 2019 4:21:06 AM)

  1. Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI. — rksimon / ViewSVN

rL:366562 - C:366546 - #63352 (Jul 19, 2019 3:41:03 AM)

  1. Don't update NoTrappingFPMath and FPDenormalMode in resetTargetOptions

    We'd like to remove this whole function, because these are properties of
    functions, not the target as a whole. These two are easy to remove
    because they are only used for emitting ARM build attributes, which
    expects them to represent the defaults for the whole module, not just
    the last function generated.

    This is needed to get correct build attributes when using IPRA on ARM,
    because IPRA causes resetTargetOptions to get called before

    Differential revision: https://reviews.llvm.org/D64929 — ostannard / ViewSVN

rL:366558 - C:366546 - #63351 (Jul 19, 2019 3:16:04 AM)

  1. [llvm-readelf] - A fix for: "--hash-symbols asserts for 64-bit ELFs"

    Fixes https://bugs.llvm.org/show_bug.cgi?id=42622.
    (--hash-symbols switch is currently broken for 64-bit ELF files, due to r352630.)

    Differential revision: https://reviews.llvm.org/D64788 — grimar / ViewSVN

rL:366557 - C:366546 - #63350 (Jul 19, 2019 3:01:06 AM)

  1. [IPRA] Don't rely on non-exact function definitions

    If a function definition is not exact, then the linker could select a
    differently-compiled version of it, which could use different registers.

    https://reviews.llvm.org/D64909 — ostannard / ViewSVN

rL:366555 - C:366546 - #63349 (Jul 19, 2019 2:51:03 AM)

  1. [ARM] Add <saturate> operand to SQRSHRL and UQRSHLL

    According to the new Armv8-M specification
    https://static.docs.arm.com/ddi0553/bh/DDI0553B_h_armv8m_arm.pdf the
    instructions SQRSHRL and UQRSHLL now have an additional immediate
    operand <saturate>. The new assembly syntax is:

    SQRSHRL<c> RdaLo, RdaHi, #<saturate>, Rm
    UQRSHLL<c> RdaLo, RdaHi, #<saturate>, Rm

    where <saturate> can be either 64 (the existing behavior) or 48, in
    that case the result is saturated to 48 bits.

    The new operand is encoded as follows:
      #64 Encoded as sat = 0
      #48 Encoded as sat = 1
    sat is bit 7 of the instruction bit pattern.

    This patch adds a new assembler operand class MveSaturateOperand which
    implements parsing and encoding. Decoding is implemented in

    Reviewers: ostannard, simon_tatham, t.p.northover, samparker, dmgreen, SjoerdMeijer

    Reviewed By: simon_tatham

    Subscribers: javed.absar, kristof.beyls, hiraditya, pbarrio, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64810 — miyuki / ViewSVN

rL:366544 - C:366546 - #63348 (Jul 19, 2019 2:16:05 AM)

  1. [OpenCL] Define CLK_NULL_EVENT without cast

    Defining CLK_NULL_EVENT with a `(void*)` cast has the (unintended?)
    side-effect that the address space will be fixed (as generic in OpenCL
    2.0 mode).  The consequence is that any target specific address space
    for the clk_event_t type will not be applied.

    It is not clear why the void pointer cast was needed in the first
    place, and it seems we can do without it.

    Differential Revision: https://reviews.llvm.org/D63876 — svenvh / ViewSVN

rL:366544 - C:366544 - #63347 (Jul 19, 2019 1:51:07 AM)

  1. [sanitizers] Use covering ObjectFormatType switches

    This patch removes the `default` case from some switches on
    `llvm::Triple::ObjectFormatType`, and cases for the missing enumerators
    (`UnknownObjectFormat`, `Wasm`, and `XCOFF`) are then added.

    For `UnknownObjectFormat`, the effect of the action for the `default`
    case is maintained; otherwise, where `llvm_unreachable` is called,
    `report_fatal_error` is used instead.

    Where the `default` case returns a default value, `report_fatal_error`
    is used for XCOFF as a placeholder. For `Wasm`, the effect of the action
    for the `default` case in maintained.

    The code is structured to avoid strongly implying that the `Wasm` case
    is present for any reason other than to make the switch cover all
    `ObjectFormatType` enumerator values.

    Reviewers: sfertile, jasonliu, daltenty

    Reviewed By: sfertile

    Subscribers: hiraditya, aheejin, sunfish, llvm-commits, cfe-commits

    Tags: #clang, #llvm

    Differential Revision: https://reviews.llvm.org/D64222 — hubert.reinterpretcast / ViewSVN

rL:366543 - C:366518 - #63346 (Jul 19, 2019 1:41:04 AM)

  1. [AMDGPU] Simplify the exclusive scan used for optimized atomics

    Change the scan algorithm to use only power-of-two shifts (1, 2, 4, 8,
    16, 32) instead of starting off shifting by 1, 2 and 3 and then doing
    a 3-way ADD, because:

    1. It simplifies the compiler a little.
    2. It minimizes vgpr pressure because each instruction is now of the
       form vn = vn + vn << c.
    3. It is more friendly to the DPP combiner, which currently can't
       combine into an ADD3 instruction.

    Because of #2 and #3 the end result is improved from this:

      v_add_u32_dpp v4, v3, v3  row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0
      v_mov_b32_dpp v5, v3  row_shr:2 row_mask:0xf bank_mask:0xf
      v_mov_b32_dpp v1, v3  row_shr:3 row_mask:0xf bank_mask:0xf
      v_add3_u32 v1, v4, v5, v1
      s_nop 1
      v_add_u32_dpp v1, v1, v1  row_shr:4 row_mask:0xf bank_mask:0xe
      s_nop 1
      v_add_u32_dpp v1, v1, v1  row_shr:8 row_mask:0xf bank_mask:0xc
      s_nop 1
      v_add_u32_dpp v1, v1, v1  row_bcast:15 row_mask:0xa bank_mask:0xf
      s_nop 1
      v_add_u32_dpp v1, v1, v1  row_bcast:31 row_mask:0xc bank_mask:0xf

    To this:

      v_add_u32_dpp v1, v1, v1  row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0
      s_nop 1
      v_add_u32_dpp v1, v1, v1  row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0
      s_nop 1
      v_add_u32_dpp v1, v1, v1  row_shr:4 row_mask:0xf bank_mask:0xe
      s_nop 1
      v_add_u32_dpp v1, v1, v1  row_shr:8 row_mask:0xf bank_mask:0xc
      s_nop 1
      v_add_u32_dpp v1, v1, v1  row_bcast:15 row_mask:0xa bank_mask:0xf
      s_nop 1
      v_add_u32_dpp v1, v1, v1  row_bcast:31 row_mask:0xc bank_mask:0xf

    I.e. two fewer computational instructions, one extra nop where we could
    schedule something else.

    Reviewers: arsenm, sheredom, critson, rampitec, vpykhtin

    Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64411 — foad / ViewSVN
  2. [Loop Peeling] Enable peeling of multiple exits by default.

    Enable loop peeling with multiple exits where all non-latch exits
    ends up with deopt by default.

    Reviewers: reames, fhahn
    Reviewed By: reames
    Subscribers: xbolva00, hiraditya, zzheng, llvm-commits
    Differential Revision: https://reviews.llvm.org/D64619 — skatkov / ViewSVN

rL:366540 - C:366518 - #63345 (Jul 19, 2019 1:31:06 AM)

  1. [InstCombine] Dropping redundant masking before left-shift [5/5] (PR42563)

    If we have some pattern that leaves only some low bits set, and then performs
    left-shift of those bits, if none of the bits that are left after the final
    shift are modified by the mask, we can omit the mask.

    There are many variants to this pattern:
    f. `((x << MaskShAmt) a>> MaskShAmt) << ShiftShAmt`
    All these patterns can be simplified to just:
    `x << ShiftShAmt`
    f. `(ShiftShAmt-MaskShAmt) s>= 0` (i.e. `ShiftShAmt u>= MaskShAmt`)

    Normally, the inner pattern is sign-extend,
    but for our purposes it's no different to other patterns:

    alive proofs:
    f: https://rise4fun.com/Alive/7U3

    For now let's start with patterns where both shift amounts are variable,
    with trivial constant "offset" between them, since i believe this is
    both simplest to handle and i think this is most common.
    But again, there are likely other variants where we could use
    ValueTracking/ConstantRange to handle more cases.


    Differential Revision: https://reviews.llvm.org/D64524 — lebedevri / ViewSVN
  2. [InstCombine] Dropping redundant masking before left-shift [4/5] (PR42563)

    If we have some pattern that leaves only some low bits set, and then performs
    left-shift of those bits, if none of the bits that are left after the final
    shift are modified by the mask, we can omit the mask.

    There are many variants to this pattern:
    e. `((x << MaskShAmt) l>> MaskShAmt) << ShiftShAmt`
    All these patterns can be simplified to just:
    `x << ShiftShAmt`
    e. `(ShiftShAmt-MaskShAmt) s>= 0` (i.e. `ShiftShAmt u>= MaskShAmt`)

    alive proofs:
    e: https://rise4fun.com/Alive/0FT

    For now let's start with patterns where both shift amounts are variable,
    with trivial constant "offset" between them, since i believe this is
    both simplest to handle and i think this is most common.
    But again, there are likely other variants where we could use
    ValueTracking/ConstantRange to handle more cases.


    Differential Revision: https://reviews.llvm.org/D64521 — lebedevri / ViewSVN
  3. [InstCombine] Dropping redundant masking before left-shift [3/5] (PR42563)

    If we have some pattern that leaves only some low bits set, and then performs
    left-shift of those bits, if none of the bits that are left after the final
    shift are modified by the mask, we can omit the mask.

    There are many variants to this pattern:
    d. `(x & ((-1 << MaskShAmt) >> MaskShAmt)) << ShiftShAmt`
    All these patterns can be simplified to just:
    `x << ShiftShAmt`
    d. `(ShiftShAmt-MaskShAmt) s>= 0` (i.e. `ShiftShAmt u>= MaskShAmt`)

    alive proofs:
    d: https://rise4fun.com/Alive/I5Y

    For now let's start with patterns where both shift amounts are variable,
    with trivial constant "offset" between them, since i believe this is
    both simplest to handle and i think this is most common.
    But again, there are likely other variants where we could use
    ValueTracking/ConstantRange to handle more cases.


    Differential Revision: https://reviews.llvm.org/D64519 — lebedevri / ViewSVN
  4. [InstCombine] Dropping redundant masking before left-shift [2/5] (PR42563)

    If we have some pattern that leaves only some low bits set, and then performs
    left-shift of those bits, if none of the bits that are left after the final
    shift are modified by the mask, we can omit the mask.

    There are many variants to this pattern:
    c. `(x & (-1 >> MaskShAmt)) << ShiftShAmt`
    All these patterns can be simplified to just:
    `x << ShiftShAmt`
    c. `(ShiftShAmt-MaskShAmt) s>= 0` (i.e. `ShiftShAmt u>= MaskShAmt`)

    alive proofs:
    c: https://rise4fun.com/Alive/RgJh

    For now let's start with patterns where both shift amounts are variable,
    with trivial constant "offset" between them, since i believe this is
    both simplest to handle and i think this is most common.
    But again, there are likely other variants where we could use
    ValueTracking/ConstantRange to handle more cases.


    Differential Revision: https://reviews.llvm.org/D64517 — lebedevri / ViewSVN
  5. [InstCombine] Dropping redundant masking before left-shift [1/5] (PR42563)

    If we have some pattern that leaves only some low bits set, and then performs
    left-shift of those bits, if none of the bits that are left after the final
    shift are modified by the mask, we can omit the mask.

    There are many variants to this pattern:
    b. `(x & (~(-1 << maskNbits))) << shiftNbits`
    All these patterns can be simplified to just:
    `x << ShiftShAmt`
    b. `(MaskShAmt+ShiftShAmt) u>= bitwidth(x)`

    alive proof:
    b: https://rise4fun.com/Alive/y8M

    For now let's start with patterns where both shift amounts are variable,
    with trivial constant "offset" between them, since i believe this is
    both simplest to handle and i think this is most common.
    But again, there are likely other variants where we could use
    ValueTracking/ConstantRange to handle more cases.


    Differential Revision: https://reviews.llvm.org/D64514 — lebedevri / ViewSVN
  6. [InstCombine] Dropping redundant masking before left-shift [0/5] (PR42563)

    If we have some pattern that leaves only some low bits set, and then performs
    left-shift of those bits, if none of the bits that are left after the final
    shift are modified by the mask, we can omit the mask.

    There are many variants to this pattern:
    a. `(x & ((1 << MaskShAmt) - 1)) << ShiftShAmt`
    All these patterns can be simplified to just:
    `x << ShiftShAmt`
    a. `(MaskShAmt+ShiftShAmt) u>= bitwidth(x)`

    alive proof:
    a: https://rise4fun.com/Alive/wi9

    Indeed, not all of these patterns are canonical.
    But since this fold will only produce a single instruction
    i'm really interested in handling even uncanonical patterns,
    since i have this general kind of pattern in hotpaths,
    and it is not totally outlandish for bit-twiddling code.

    For now let's start with patterns where both shift amounts are variable,
    with trivial constant "offset" between them, since i believe this is
    both simplest to handle and i think this is most common.
    But again, there are likely other variants where we could use
    ValueTracking/ConstantRange to handle more cases.


    Reviewers: spatel, nikic, huihuiz, xbolva00

    Reviewed By: xbolva00

    Subscribers: efriedma, hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64512 — lebedevri / ViewSVN

rL:366533 - C:366518 - #63344 (Jul 19, 2019 12:26:04 AM)

  1. [NFC] Fix an indentation issue in llvm/Support/TargetRegistry.h — hubert.reinterpretcast / ViewSVN

rL:366531 - C:366518 - #63343 (Jul 18, 2019 11:11:05 PM)

  1. [DebugInfo] Some fields do not need relocations even relax is enabled.

    In debug frame information, some fields, e.g., Length in CIE/FDE and
    Offset in FDE are attributes to describe the structure of CIE/FDE. They
    are not related to the relaxed code. However, these attributes are
    symbol differences. So, in current design, these attributes will be
    filled as zero and LLVM generates relocations for them.

    We only need to generate relocations for symbols in executable sections.
    So, if the symbols are not located in executable sections, we still
    evaluate their values under relaxation.

    Differential Revision: https://reviews.llvm.org/D61584 — hsiangkai / ViewSVN

rL:366530 - C:366518 - #63342 (Jul 18, 2019 10:51:04 PM)

  1. unbreak links — lattner / ViewSVN

rL:366529 - C:366518 - #63341 (Jul 18, 2019 10:26:06 PM)

  1. replace the old kaleidoscope tutorial files with orphaned pages that forward to the new copy. — lattner / ViewSVN

rL:366528 - C:366518 - #63340 (Jul 18, 2019 10:21:06 PM)

  1. Point to the dusted off version of the kaleidoscope tutorial. — lattner / ViewSVN

rL:366527 - C:366518 - #63339 (Jul 18, 2019 7:36:06 PM)

  1. [test] [llvm-objcopy] Fix broken test case

    Summary: The test case added in D62718 did not work unless the user was root because write bits were not set for the output file. This change uses only permissions with user write (0200) to ensure tests pass regardless of the users permissions.

    Reviewers: jhenderson, rupprecht, MaskRay, espindola, alexshap

    Reviewed By: MaskRay

    Subscribers: emaste, arichardson, jakehehrlich, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64302 — abrachet / ViewSVN

rL:366526 - C:366518 - #63338 (Jul 18, 2019 7:26:04 PM)

  1. [NFC][PowerPC] Modify the test case add_cmp.ll — zhangkang / ViewSVN

rL:366524 - C:366518 - #63337 (Jul 18, 2019 7:06:09 PM)

  1. [DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame.

    It is necessary to generate fixups in .debug_frame or .eh_frame as
    relaxation is enabled due to the address delta may be changed after

    There is an opcode with 6-bits data in debug frame encoding. So, we
    also need 6-bits fixup types.

    Differential Revision: https://reviews.llvm.org/D58335 — hsiangkai / ViewSVN

rL:366523 - C:366518 - #63336 (Jul 18, 2019 6:11:07 PM)

  1. Use the MachineBasicBlock symbol for a callbr target

    Inline asm doesn't use labels when compiled as an object file. Therefore, we
    shouldn't create one for the (potential) callbr destination. Instead, use the
    symbol for the MachineBasicBlock.

    Reviewers: nickdesaulniers, craig.topper

    Reviewed By: nickdesaulniers

    Subscribers: xbolva00, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64888 — void / ViewSVN

rL:366516 - C:366518 - #63334 (Jul 18, 2019 5:26:09 PM)

  1. Fix formatting of inline argument comments. NFC.

    Also, remove the final arg from ItaniumCXXABI in the PNaCl case since
    its not needed.

    Differential Revision: https://reviews.llvm.org/D64955 — sbc / ViewSVN
  2. [GlobalISel] Translate calls to memcpy et al to G_INTRINSIC_W_SIDE_EFFECTs and legalize later.

    I plan on adding memcpy optimizations in the GlobalISel pipeline, but we can't
    do that unless we delay lowering to actual function calls. This patch changes
    the translator to generate G_INTRINSIC_W_SIDE_EFFECTS for these functions, and
    then have each target specify that using the new custom legalizer for intrinsics
    hook that they want it expanded it a libcall.

    Differential Revision: https://reviews.llvm.org/D64895 — aemerson / ViewSVN
  3. [cmake] Fix typo where a varible was checked for Apple instead of Darwin

    Subscribers: mgorny, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64965 — lanza / ViewSVN

rL:366514 - C:366511 - #63333 (Jul 18, 2019 5:11:07 PM)

  1. [cmake] Convert the NATIVE llvm build process to be project agnostic

    lldb recently added a tablegen tool. In order to properly cross compile
    lldb standalone there needs to be a mechanism to generate the native
    lldb build, analgous to what's done for the NATIVE llvm build. Thus,
    we can simply modify this setup to allow for any project to be used. — lanza / ViewSVN

rL:366512 - C:366511 - #63332 (Jul 18, 2019 3:51:09 PM)

  1. Reapply [llvm-lipo] Implement -create (with hardcoded alignments)

    This reapplies r366142 with a fix for the failing Windows test.

    Original commit message:

    Creates universal binary output file from input files. Currently uses
    hard coded value for alignment.  Want to get the create functionality
    approved before implementing the alignment function.

    Patch by Anusha Basana <anusha.basana@gmail.com>

    Differential Revision: https://reviews.llvm.org/D64102 — smeenai / ViewSVN
  2. Update the SimpleJIT class in the clang-interpreter example to use ORCv2.

    This will remove the ORCv1 deprecation warnings. — lhames / ViewSVN

rL:366505 - C:366509 - #63331 (Jul 18, 2019 3:36:04 PM)

  1. [clang-scan-deps] Dependency directives source minimizer: handle #pragma once

    We should re-emit `#pragma once` to ensure the preprocessor will
    still honor it when running on minimized sources.

    Differential Revision: https://reviews.llvm.org/D64945 — arphaman / ViewSVN

rL:366505 - C:366499 - #63330 (Jul 18, 2019 3:21:08 PM)

  1. [AMDGPU] Drop Reg32 and use regular AsmName

    This allows to reduce generated AMDGPUGenAsmWriter.inc by ~100Kb.

    Differential Revision: https://reviews.llvm.org/D64952 — rampitec / ViewSVN

rL:366503 - C:366499 - #63329 (Jul 18, 2019 2:51:27 PM)

  1. [GlobalISel][AArch64] Add support for base register + offset register loads

    Add support for folding G_GEPs into loads of the form

    ldr reg, [base, off]

    when possible. This can save an add before the load. Currently, this is only
    supported for loads of 64 bits into 64 bit registers.

    Add a new addressing mode function, `selectAddrModeRegisterOffset` which
    performs this folding when it is profitable.

    Also add a test for addressing modes for G_LOAD.

    Differential Revision: https://reviews.llvm.org/D64944 — paquette / ViewSVN

rL:366502 - C:366499 - #63328 (Jul 18, 2019 2:41:06 PM)

  1. CodeGen: Allow !associated metadata to point to aliases.

    This is a small extension of !associated, mostly useful for the implementation
    convenience of instrumentation passes that RAUW globals with aliases, such
    as LowerTypeTests.

    Differential Revision: https://reviews.llvm.org/D64951 — pcc / ViewSVN

rL:366501 - C:366499 - #63327 (Jul 18, 2019 2:34:27 PM)

  1. Revert [X86] EltsFromConsecutiveLoads - support common source loads

    This reverts r366441 (git commit 48104ef7c9c653bbb732b66d7254957389fea337)

    This causes clang to fail to compile some file in Skia. Reduction soon. — rnk / ViewSVN

rL:366499 - C:366499 - #63326 (Jul 18, 2019 2:20:08 PM)

  1. [WebAssembly] Fix __builtin_wasm_tls_base intrinsic

    Properly generate the outchain for the `__builtin_wasm_tls_base` intrinsic.

    Also marked the intrinsic pure, per @sunfish's suggestion.

    Reviewers: tlively, aheejin, sbc100, sunfish

    Reviewed By: tlively

    Subscribers: dschuff, jgravelle-google, hiraditya, cfe-commits, llvm-commits, sunfish

    Tags: #clang, #llvm

    Differential Revision: https://reviews.llvm.org/D64949 — quantum / ViewSVN
  2. [cmake] Only run llvm-codesign if targetting apple on an apple host

    Other platforms don't have the capability to perform llvm_codesign
    step. If LLVM_CODESIGNING_IDENTITY is set then this chunk of code would
    attempt to codesign if the target was Apple. But when cross compiling
    to Darwin from Linux, for example, this step would fail. So test if the
    host is Apple as well.

    Subscribers: mgorny, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64942 — lanza / ViewSVN

rL:366497 - C:366483 - #63325 (Jul 18, 2019 2:13:13 PM)

  1. Fix typo in r366494. Spotted by Yuanfang Chen. — pcc / ViewSVN
  2. Remove the static initialize introduced in r365099

    Some polish for r365099 which adds a static initializer to
    MachOObjectFile. Remove it by moving it to file scope.

    Reviewers: smeenai, alexshap, compnerd, mtrent, anushabasana

    Reviewed By: smeenai

    Subscribers: hiraditya, jkorous, dexonsmith, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64873 — steven_wu / ViewSVN

rL:366494 - C:366483 - #63324 (Jul 18, 2019 2:03:32 PM)

  1. IR: Teach Constant::needsRelocation() that relative pointers don't need to be relocated.

    This causes sections with relative pointers to be marked as read only,
    which means that they won't end up sharing pages with writable data.

    Differential Revision: https://reviews.llvm.org/D64948 — pcc / ViewSVN

rL:366487 - C:366483 - #63323 (Jul 18, 2019 1:48:36 PM)

  1. gn build: Merge r366458. — pcc / ViewSVN

rL:366486 - C:366483 - #63322 (Jul 18, 2019 1:06:06 PM)

  1. FileSystem: Check for DTTOIF alone, not _DIRENT_HAVE_D_TYPE

    While 'd_type' is a non-standard extension to `struct dirent`, only
    glibc signals its presence with a macro '_DIRENT_HAVE_D_TYPE'.
    However, any platform with 'd_type' also includes a way to convert to
    mode_t values using the macro 'DTTOIF', so we can check for that alone
    and still be confident that the 'd_type' member exists.

    (If this turns out to be wrong, I'll go back and set up an actual
    CMake check.)

    I couldn't think of how to write a test for this, because I couldn't
    think of how to test that a 'stat' call doesn't happen without
    controlling the filesystem or intercepting 'stat', and there's no good
    cross-platform way to do that that I know of.

    Follow-up (almost a year later) to r342089.

    https://reviews.llvm.org/D64940 — jrose / ViewSVN

rL:366485 - C:366483 - #63321 (Jul 18, 2019 1:02:06 PM)

  1. [ORC] Suppress an ORCv1 deprecation warning. — lhames / ViewSVN

rL:366481 - C:366483 - #63320 (Jul 18, 2019 12:41:09 PM)

  1. [OPENMP]Fix sharing of threadprivate variables with TLS support.

    If the threadprivate variable is used in the copyin clause on inner
    parallel directive with TLS support, we capture this variable in all
    outer OpenMP scopes. It leads to the fact that in all scopes we're
    working with the original variable, not the threadprivate copies. — abataev / ViewSVN

rL:366481 - C:366480 - #63319 (Jul 18, 2019 11:36:24 AM)

  1. Fix C++ modules build

    llvm-svn: 366344 missed an include that broke the LLVM_ENABLE_MODULES
    build. — teemperor / ViewSVN
  2. [RISCV] Hard float ABI support

    The RISC-V hard float calling convention requires the frontend to:

    * Detect cases where, once "flattened", a struct can be passed using
    int+fp or fp+fp registers under the hard float ABI and coerce to the
    appropriate type(s)
    * Track usage of GPRs and FPRs in order to gate the above, and to
    determine when signext/zeroext attributes must be added to integer

    This patch attempts to do this in compliance with the documented ABI,
    and uses ABIArgInfo::CoerceAndExpand in order to do this. @rjmccall, as
    author of that code I've tagged you as reviewer for initial feedback on
    my usage.

    Note that a previous version of the ABI indicated that when passing an
    int+fp struct using a GPR+FPR, the int would need to be sign or
    zero-extended appropriately. GCC never did this and the ABI was changed,
    which makes life easier as ABIArgInfo::CoerceAndExpand can't currently
    handle sign/zero-extension attributes.

    Re-landed after backing out 366450 due to missed hunks.

    Differential Revision: https://reviews.llvm.org/D60456 — asb / ViewSVN
  3. [COFF] Change a variable type to be const in the HeapAllocSite map. — akhuang / ViewSVN

rL:366477 - C:366475 - #63318 (Jul 18, 2019 11:18:20 AM)

  1. [FPEnv] Teach the IRBuilder about constrained FPTrunc and FPExt

    The IRBuilder doesn't know that FPTrunc and FPExt have constrained
    equivalents. Add the support by building on the strict FP mode now
    present in the IRBuilder.

    Reviewed by: John McCall
    Approved by: John McCall
    Differential Revision: https://reviews.llvm.org/D64934 — kpn / ViewSVN

rL:366475 - C:366475 - #63317 (Jul 18, 2019 10:56:50 AM)

  1. [WebAssembly] Implement __builtin_wasm_tls_base intrinsic

    Add `__builtin_wasm_tls_base` so that LeakSanitizer can find the thread-local
    block and scan through it for memory leaks.

    Reviewers: tlively, aheejin, sbc100

    Subscribers: dschuff, jgravelle-google, hiraditya, sunfish, cfe-commits, llvm-commits

    Tags: #clang, #llvm

    Differential Revision: https://reviews.llvm.org/D64900 — quantum / ViewSVN
  2. [OPENMP]Provide correct data sharing attributes for loop control

    Loop control variables are private in loop-based constructs and we shall
    take this into account when generate the code for inner constructs.
    Currently, those variables are reported as shared in many cases. Moved
    the analysis of the data-sharing attributes of the loop control variable
    to an early semantic stage to correctly handle their attributes. — abataev / ViewSVN

rL:366470 - C:366473 - #63316 (Jul 18, 2019 10:46:06 AM)

  1. [LibTooling] Relax Transformer to allow rewriting macro expansions

    Currently, Transformer rejects any changes to source locations inside macro
    expansions. This change relaxes that constraint to allow rewrites when the
    entirety of the expansion is replaced, since that can be mapped to replacing the
    entirety of the expansion range in the file source.  This change makes
    Transformer consistent with the handling of edit ranges in `clang::edit::Commit`
    (which is used, for example, for applying `FixItHint`s from diagnostics).

    Reviewers: ilya-biryukov

    Subscribers: gribozavr, cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D64518 — ymandel / ViewSVN

rL:366470 - C:366469 - #63315 (Jul 18, 2019 10:31:09 AM)

  1. [LAA] Re-check bit-width of pointers after stripping.

    - As the pointer stripping now tracks through `addrspacecast`, prepare
      to handle the bit-width difference from the result pointer.

    Reviewers: jdoerfert

    Subscribers: jvesely, nhaehnle, hiraditya, arphaman, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64928 — hliao / ViewSVN
  2. [LibTooling] Add function to translate and validate source range for editing

    Adds the function `getRangeForEdit` to validate that a given source range is
    editable and, if needed, translate it into a range in the source file (for
    example, if it's sourced in macro expansions).

    Reviewers: ilya-biryukov

    Subscribers: cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D64924 — ymandel / ViewSVN

rL:366464 - C:366457 - #63314 (Jul 18, 2019 10:06:09 AM)

  1. [NFC][llvm-readobj] Refactor dynamic string table indexing into a function.

    Restore printDynamicString removed in rL363868. It provides better
    error handling whenever indexing dynamic string table is needed.

    Reviewers: jhenderson, MaskRay, grimar

    Reviewed by: jhenderson, MaskRay, grimar

    Differential Revision: https://reviews.llvm.org/D64674 — yuanfang / ViewSVN

rL:366462 - C:366457 - #63313 (Jul 18, 2019 9:56:06 AM)

  1. MC: AArch64: Add support for prel_g* relocation specifiers.

    Differential Revision: https://reviews.llvm.org/D64683 — pcc / ViewSVN
  2. AArch64: Unify relocation restrictions between MOVK/MOVN/MOVZ.

    There doesn't seem to be a practical reason for these instructions to have
    different restrictions on the types of relocations that they may be used
    with, notwithstanding the language in the ELF AArch64 spec that implies that
    specific relocations are meant to be used with specific instructions.

    For example, we currently forbid the first instruction in the following
    sequence, despite it currently being used by clang to generate a global
    reference under -mcmodel=large:

    movz x0, #:abs_g0_nc:foo
    movk x0, #:abs_g1_nc:foo
    movk x0, #:abs_g2_nc:foo
    movk x0, #:abs_g3:foo

    Therefore, allow MOVK/MOVN/MOVZ to accept the union of the set of relocations
    that they currently accept individually.

    Differential Revision: https://reviews.llvm.org/D64466 — pcc / ViewSVN

rL:366456 - C:366457 - #63312 (Jul 18, 2019 9:46:40 AM)

  1. [ASTUnit] Attempt to unbreak Windows buildbots after r366448 — ibiryukov / ViewSVN
  2. Minor styling fix. NFC. — hliao / ViewSVN
  3. Revert "[RISCV] Hard float ABI support" r366450

    The commit was missing a few hunks. Will fix and recommit. — asb / ViewSVN
  4. Revert r366449: [CrossTU] Add a function to retrieve original source location.

    Reason: the commit breaks layering by adding a dependency on ASTUnit
    (which is inside clangFrontend) from the ASTImporter (which is inside
    clangAST). — ibiryukov / ViewSVN
  5. [RISCV] Hard float ABI support

    The RISC-V hard float calling convention requires the frontend to:

    * Detect cases where, once "flattened", a struct can be passed using
    int+fp or fp+fp registers under the hard float ABI and coerce to the
    appropriate type(s) * Track usage of GPRs and FPRs in order to gate the
    above, and to
    determine when signext/zeroext attributes must be added to integer

    This patch attempts to do this in compliance with the documented ABI,
    and uses ABIArgInfo::CoerceAndExpand in order to do this. @rjmccall, as
    author of that code I've tagged you as reviewer for initial feedback on
    my usage.

    Note that a previous version of the ABI indicated that when passing an
    int+fp struct using a GPR+FPR, the int would need to be sign or
    zero-extended appropriately. GCC never did this and the ABI was changed,
    which makes life easier as ABIArgInfo::CoerceAndExpand can't currently
    handle sign/zero-extension attributes.

    Differential Revision: https://reviews.llvm.org/D60456 — asb / ViewSVN
  6. [CrossTU] Add a function to retrieve original source location.

    A new function will be added to get the original SourceLocation
    for a SourceLocation that was imported as result of getCrossTUDefinition.
    The returned SourceLocation is in the context of the (original)
    SourceManager for the original source file. Additionally the
    ASTUnit object for that source file is returned. This is needed
    to get a SourceManager to operate on with the returned source location.

    The new function works if multiple different source files are loaded
    with the same CrossTU context.

    This patch can be treated as part of a bigger change that is needed to
    improve macro expansion handliong at plist generation.

    Reviewers: martong, shafik, a_sidorin, xazax.hun

    Reviewed By: martong

    Subscribers: rnkovacs, dkrupp, Szelethus, gamesh411, cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D64554 — balazske / ViewSVN
  7. [ASTUnit] Fix a regression in cached completions

    After r345152 cached completions started adding namespaces after
    nested name specifiers, e.g. in `some_name::^`

    The CCC_Symbol indicates the completed item cannot be a namespace (it is
    described as being "a type, a function or a variable" in the comments).

    Therefore, 'nested specifier' completions should only be added from cache
    when the context is CCC_SymbolOrNewName (which roughly seems to indicate
    that a nested name specifier is allowed).

    Fixes https://bugs.llvm.org/show_bug.cgi?id=42646

    Reviewers: kadircet, sammccall

    Reviewed By: kadircet, sammccall

    Subscribers: arphaman, nik, sammccall, cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D64918 — ibiryukov / ViewSVN
  8. [CMake] Don't set Python_ADDITIONAL_VERSIONS

    Until recently, Python_ADDITIONAL_VERSIONS was used to limit LLVM's
    Python support to 2.7. Now that both LLVM and LLDB both support Python
    3, there's no longer a need to put an arbitrary limit on this.

    However, instead of removing the variable, r365692 expanded the list,
    which has the (presumably unintentional) side-effect of expression
    preference for Python 3.

    Instead, as Michal proposed in the original code review, we should just
    not set the list at all, and let CMake pick whatever Python interpreter
    you have in your path.

    This patch removes the Python_ADDITIONAL_VERSIONS variable in llvm,
    clang and lld. I've also updated the docs with the default behavior and
    how to force a different Python version to be used.

    Differential revision: https://reviews.llvm.org/D64894 — jdevlieghere / ViewSVN
  9. Revert "[DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame."

    This reverts commit 17e3cbf5fe656483d9016d0ba9e1d0cd8629379e. — hsiangkai / ViewSVN
  10. [DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame.

    It is necessary to generate fixups in .debug_frame or .eh_frame as
    relaxation is enabled due to the address delta may be changed after

    There is an opcode with 6-bits data in debug frame encoding. So, we
    also need 6-bits fixup types.

    Differential Revision: https://reviews.llvm.org/D58335 — hsiangkai / ViewSVN
  11. [X86] EltsFromConsecutiveLoads - support common source loads

    This patch enables us to find the source loads for each element, splitting them into a Load and ByteOffset, and attempts to recognise consecutive loads that are in fact from the same source load.

    A helper function, findEltLoadSrc, recurses to find a LoadSDNode and determines the element's byte offset within it. When attempting to match consecutive loads, byte offsetted loads then attempt to matched against a previous load that has already been confirmed to be a consecutive match.

    Next step towards PR16739 - after this we just need to account for shuffling/repeated elements to create a vector load + shuffle.

    Differential Revision: https://reviews.llvm.org/D64551 — rksimon / ViewSVN
  12. [analyzer] Add CTU user docs

    Reviewers: dkrupp, a_sidorin, Szelethus, NoQ

    Subscribers: whisperity, xazax.hun, baloghadamsoftware, szepet, rnkovacs, a.sidorin, mikhail.ramalho, donat.nagy, gamesh411, Charusso, cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D64801 — martong / ViewSVN
  13. [OPENMP][NVPTX]Mark barrier functions calls as convergent.

    Added convergent attribute to the barrier functions calls for correct
    optimizations. — abataev / ViewSVN
  14. [DAGCombine] Pull getSubVectorSrc helper out of narrowInsertExtractVectorBinOp. NFCI.

    NFC step towards reusing this in other EXTRACT_SUBVECTOR combines. — rksimon / ViewSVN
  15. [FileCheck] Fix numeric variable redefinition

    Commit r365249 changed usage of FileCheckNumericVariable to have one
    instance of that class per variable as opposed to one instance per
    definition of a given variable as was done before. However, it retained
    the safety check in setValue that it should only be called with the
    variable unset, even after r365625.

    However this causes assert failure when a non-pseudo variable is being
    redefined. And while redefinition of @LINE at each CHECK line work in
    the general case, it caused problem when a substitution failed (fixed in
    r365624) and still causes problem when a CHECK line does not match since
    @LINE's value is cleared after substitutions in match() happened but
    printSubstitutions also attempts a substitution.

    This commit solves the root of the problem by changing setValue to set a
    new value regardless of whether a value was set or not, thus fixing all
    the aforementioned issues.

    Reviewers: jhenderson, chandlerc, jdenny, probinson, grimar, arichardson, rnk

    Subscribers: hiraditya, llvm-commits, probinson, dblaikie, grimar, arichardson, tra, rnk, kristina, hfinkel, rogfer01, JonChesterfield

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64882 — thopre / ViewSVN
  16. [x86] try harder to form LEA from ADD to avoid flag conflicts (PR40483)

    LEA doesn't affect flags, so use it more liberally to replace an ADD when
    we know that the ADD operands affect flags.

    In the motivating example from PR40483:
    ...this lets us avoid duplicating a math op just to avoid flag conflict.

    As mentioned in the TODO comments, this heuristic can be extended to
    fire more often if that leads to more improvements.

    Differential Revision: https://reviews.llvm.org/D64707 — spatel / ViewSVN
  17. [llvm-readelf] - Remove the precompiled binary from gnu-hash-symbols.test

    I am working on https://bugs.llvm.org/show_bug.cgi?id=42622
    and this patch reworks the gnu-hash-symbols.test so that it
    will be easier to expand it with x86_64 case.

    Differential revision: https://reviews.llvm.org/D64750 — grimar / ViewSVN
  18. Revert r366422: [OpenCL] Improve destructor support in C++ for OpenCL

    Reason: this commit causes crashes in the clang compiler when building
    LLVM Support with libc++, see https://bugs.llvm.org/show_bug.cgi?id=42665
    for details. — ibiryukov / ViewSVN
  19. Bump the trunk version to 10.0.0svn

    and clear the release notes. — hans / ViewSVN
  20. [ARM][DAGCOMBINE][FIX] PerformVMOVRRDCombine

    PerformVMOVRRDCombine ommits adding a offset
    of 4 to the PointerInfo, when converting a
    f64 = load[M]
    {i32, i32} = {load[M], load[M + 4]}

    Which would allow the machine scheduller
    to break dependencies with the second load.

    - pr42638

    Reviewers: eli.friedman, dmgreen, ostannard

    Reviewed By: ostannard

    Subscribers: ostannard, javed.absar, kristof.beyls, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64870 — dnsampaio / ViewSVN
  21. [OpenCL] Improve destructor support in C++ for OpenCL

    This patch does mainly three things:
    1. It fixes a false positive error detection in Sema that is similar to
        D62156. The error happens when explicitly calling an overloaded
        destructor for different address spaces.
    2. It selects the correct destructor when multiple overloads for
        address spaces are available.
    3. It inserts the expected address space cast when invoking a
        destructor, if needed, and therefore fixes a crash due to the unmet
        assertion in llvm::CastInst::Create.

    The following is a reproducer of the three issues:

        struct MyType {
          ~MyType() {}
          ~MyType() __constant {}

        __constant MyType myGlobal{};

        kernel void foo() {
          myGlobal.~MyType(); // 1 and 2.
          // 1. error: cannot initialize object parameter of type
          //    '__generic MyType' with an expression of type '__constant MyType'
          // 2. error: no matching member function for call to '~MyType'

        kernel void bar() {
          // 3. The implicit call to the destructor crashes due to:
          //    Assertion `castIsValid(op, S, Ty) && "Invalid cast!"' failed.
          //    in llvm::CastInst::Create.
          MyType myLocal;

    The added test depends on D62413 and covers a few more things than the
    above reproducer.

    Subscribers: yaxunl, Anastasia, cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D64569 — mantognini / ViewSVN
  22. [OpenCL] Update comments/diagnostics to refer to C++ for OpenCL

    Clang doesn't implement OpenCL C++, change the comments to
    reflect that.

    Differential Revision: https://reviews.llvm.org/D64867 — stulova / ViewSVN
  23. [SCEV] add no wrap flag for SCEVAddExpr.
    Differential Revision: https://reviews.llvm.org/D64868 — shchenz / ViewSVN
  24. [OpenCL][PR42033] Fix addr space deduction with template parameters

    If dependent types appear in pointers or references we allow addr
    space deduction because the addr space in template argument will
    belong to the pointee and not the pointer or reference itself.

    We also don't diagnose addr space on a function return type after
    template instantiation. If any addr space for the return type was
    provided on a template parameter this will be diagnosed during the
    parsing of template definition.

    Differential Revision: https://reviews.llvm.org/D62584 — stulova / ViewSVN
  25. [RISCV] Reset NoPHIS MachineFunctionProperty in emitSelectPseudo

    We insered PHIS were there were none before, so the property must be
    reset. This error was found on an EXPENSIVE_CHECKS build. — asb / ViewSVN
  26. [LoopInfo] Use early return in branch weight update functions. NFC. — skatkov / ViewSVN
  27. [RISCV][DebugInfo] Fix dwarf-riscv-relocs.ll test on Windows

    Windows sees DW_AT_decl_file (".\dwarf-riscv-relocs.c") while Linux sees
    DW_AT_decl_file ("./dwarf-riscv-relocs.c").

    This fixes a failure introduced in rL366402. — asb / ViewSVN
  28. [CodeComplete] Fix ASTUnit cached completion of macros from preamble, broken in r342528

    The problem is the default LoadExternal with no completer, which happens when
    loading global results.

    Reviewers: ilya-biryukov, nik

    Subscribers: arphaman, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64864 — sammccall / ViewSVN
  29. [NFC][PowerPC] Add the test to test the pass block-placement — zhangkang / ViewSVN
  30. [PowerPC][Clang] Remove use of malloc in mm_malloc

    Remove dependency of malloc in implementation of mm_malloc function in PowerPC
    intrinsics and alignment assumption on glibc.

    Reviewed By: Hal Finkel

    Differential Revision: https://reviews.llvm.org/D64850 — chaofan / ViewSVN
  31. [X86] Disable combineConcatVectors for vXi1 vectors.

    I'm not convinced the code this calls is properly vetted for
    vXi1 vectors. Experimental vector widening legalization testing
    for D55251 is now hitting an assertion failure inside
    EltsFromConsecutiveLoads. This is occurring from a v2i1 load
    having a store size different than its VT size. Hopefully
    this commit will keep such issues from happening. — ctopper / ViewSVN
  32. Fix typo in programmer's manual cantFile -> cantFail — lanza / ViewSVN
  33. [DWARF][RISCV] Add support for RISC-V relocations needed for debug info

    When code relaxation is enabled many RISC-V fixups are not resolved but
    instead relocations are emitted. This happens even for DWARF debug
    sections. Therefore, to properly support the parsing of DWARF debug info
    we need to be able to resolve RISC-V relocations. This patch adds:

    * Support for RISC-V relocations in RelocationResolver
    * DWARF support for two relocations per object file offset
    * DWARF changes to support relocations in more DIE fields

    The two relocations per offset change is needed because some RISC-V
    relocations (used for label differences) come in pairs.

    Relocations can also be emitted for DWARF fields where relocations were
    not yet evaluated. Adding relocation support for some of these fields is
    essencial. On the other hand, LLVM currently emits RISC-V relocations
    for fixups that could be safely evaluated, since they can never be
    affected by code relaxations. This patch also adds relocation support
    for the fields affected by those extraneous relocations (the DWARF unit
    entry Length, and the DWARF debug line entry TotalLength and
    PrologueLength), for testing purposes.

    Differential Revision: https://reviews.llvm.org/D62062
    Patch by Luís Marques. — asb / ViewSVN

rL:366399 - C:366391 - #63311 (Jul 17, 2019 9:08:31 PM)

  1. [RISCV] Re-land r366331 d RISCV to LLVM_ALL_TARGETS

    *San flagged issues should be now be addressed. — asb / ViewSVN
  2. [RISCV] Avoid signed integer overflow UB in RISCVMatInt::generateInstSeq

    Found by UBSan. — asb / ViewSVN
  3. [RISCV] Don't acccess an invalidated iterator in RISCVInstrInfo::removeBranch

    Issue found by ASan. — asb / ViewSVN

rL:366390 - C:366379 - #63308 (Jul 17, 2019 4:56:55 PM)

  1. Changes to display code view debug info type records in hex format — nilanjana_basu / ViewSVN
  2. Make DT a transitive dependency of LI.

    LoopInfoWrapperPass::verify uses DT, which means DT must be alive
    even if it has no direct users.

    Fixes a crash in expensive checks mode.

    Reviewers: pcc, leonardchan

    Subscribers: hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64896 — eugenis / ViewSVN
  3. [llvm-bcanalyzer] Fixed error 'Expected<T> must be checked before access or destruction'

    After rL365286 I had failing test:
      LLVM :: tools/gold/X86/v1.12/thinlto_emit_linked_objects.ll

    It was failing with the output:
    $ llvm-bcanalyzer --dump llvm/test/tools/gold/X86/v1.12/Output/thinlto_emit_linked_objects.ll.tmp3.o.thinlto.bc
    Expected<T> must be checked before access or destruction.
    Unchecked Expected<T> contained error:
    Unexpected end of file reading 0 of 0 bytesStack dump:

    Change-Id: I07e03262074ea5e0aae7a8d787d5487c87f914a2 — dendibakh / ViewSVN

rL:366367 - C:366357 - #63303 (Jul 17, 2019 1:39:29 PM)

  1. GlobalISel: Handle widenScalar of arbitrary G_MERGE_VALUES sources

    Extract the sources to the GCD of the original size and target size,
    padding with implicit_def as necessary.

    Also fix the case where the requested source type is wider than the
    original result type. This was ignoring the type, and just using the
    destination. Do the operation in the requested type and truncate back. — arsenm / ViewSVN
  2. GlobalISel: Handle more cases for widenScalar of G_MERGE_VALUES

    Use an anyext to the requested type for the leftover operand to
    produce a slightly wider type, and then truncate the final merge.

    I have another implementation almost ready which handles arbitrary
    widens, but I think it produces worse code in this example (which I
    think is 90% due to not folding redundant copies or folding out
    implicit_def users), so I wanted to add this as a baseline first. — arsenm / ViewSVN

rL:366361 - C:366357 - #63302 (Jul 17, 2019 12:29:35 PM)

  1. Basic MTE stack tagging instrumentation.

    Use MTE intrinsics to tag stack variables in functions with
    sanitize_memtag attribute.

    Reviewers: pcc, vitalybuka, hctim, ostannard

    Subscribers: srhines, mgorny, javed.absar, hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64173 — eugenis / ViewSVN
  2. Basic codegen for MTE stack tagging.

    Implement IR intrinsics for stack tagging. Generated code is very
    unoptimized for now.

    Two special intrinsics, llvm.aarch64.irg.sp and llvm.aarch64.tagp are
    used to implement a tagged stack frame pointer in a virtual register.

    Differential Revision: https://reviews.llvm.org/D64172 — eugenis / ViewSVN

rL:366348 - C:366336 - #63299 (Jul 17, 2019 10:08:06 AM)

  1. [AMDGPU] Tune inlining parameters for AMDGPU target

    Since the target has no significant advantage of vectorization,
    vector instructions bous threshold bonus should be optional.

    amdgpu-inline-arg-alloca-cost parameter default value and the target
    InliningThresholdMultiplier value tuned then respectively.

    Reviewers: arsenm, rampitec

    Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, eraman, hiraditya, haicheng, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64642 — dfukalov / ViewSVN
  2. [ORC] Add deprecation warnings to ORCv1 layers and utilities.

    ORCv1 is deprecated. The current aim is to remove it before the LLVM 10.0
    release. This patch adds deprecation attributes to the ORCv1 layers and
    utilities to warn clients of the change.

    Reviewers: dblaikie, sgraenitz, AlexDenisov

    Subscribers: llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64609 — lhames / ViewSVN
  3. [RISCV] Revert r366331 as it exposed some sanitizer failures

    See <http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/33612>. — asb / ViewSVN
  4. AMDGPU: Use getTargetConstant

    Avoids creating an extra intermediate mov. — arsenm / ViewSVN

rL:366335 - C:366336 - #63298 (Jul 17, 2019 8:36:02 AM)

  1. [OPENMP]Fix crash in LoopCounterRefChecker when MemberExpr is not Var or Field

    checkDecl is only valid for VarDecls or FieldDecls, since getCanonicalDecl
    expects only these. Prevent other Decl kinds (such as CXXMethodDecls and
    EnumConstantDecls) from entering and asserting.

    Differential Revision: https://reviews.llvm.org/D64842 — mikerice / ViewSVN
  2. [Attributor] Deduce "willreturn" function attribute

    Deduce the "willreturn" attribute for functions.

    For now, intrinsics are not willreturn. More annotation will be done in another patch.

    Reviewers: jdoerfert

    Subscribers: jvesely, nhaehnle, nicholas, hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D63046 — uenoku / ViewSVN
  3. [llvm-ar][test] Add tests failing on Darwin

    These tests that failed on Darwin but passed on other machines due to the default archive format differing
    on a Darwin machine, and what looks to be bugs in the output of this format.
    I can not investigate these issue further so the tests are considered expected failures on Darwin.

    Differential Revision: https://reviews.llvm.org/D64802 — gbreynoo / ViewSVN

rL:366331 - C:366332 - #63297 (Jul 17, 2019 8:05:13 AM)

  1. [ASTImporter] Fix structural eq of lambdas

    The structural equivalence check reported false eq between lambda classes
    with different parameters in their call signature.
    The solution is to check the methods for equality too in case of lambda

    Reviewers: a_sidorin, a.sidorin

    Subscribers: rnkovacs, dkrupp, Szelethus, gamesh411, cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D64075 — martong / ViewSVN
  2. [RISCV] Add RISCV to LLVM_ALL_TARGETS so it s built by default

    This follows the RFC <http://lists.llvm.org/pipermail/llvm-dev/2019-July/133724.html>.

    Follow-on commits will add appropriate release notes changes etc.

    Pushing this now and in a minimal form so there is reasonable time before 9.0
    branches to resolve any issues arising from e.g. the backend being exposed on
    different sanitizer setups.

    The current builder for RISC-V is on the staging build-bot
    <http://lab.llvm.org:8014/builders/llvm-riscv-linux>, however with the RISCV
    backend being built by default it won't provide any real additional coverage.
    We will shortly set up a builder that runs the test-suite in qemu-user. — asb / ViewSVN
  3. [RISCV][NFC] Remove outdated TODO from test/CodeGen/RISCV/dwarf-eh.ll — asb / ViewSVN
  4. [AsmPrinter] Make the encoding of call sites in .gcc_except_table configurable and use for RISC-V

    The original behavior was to always emit the offsets to each call site in the
    call site table as uleb128 values, however on some architectures (eg RISCV)
    these uleb128 offsets into the code cannot always be resolved until link time
    (because relaxation will invalidate any calculated offsets), and there are no
    appropriate relocations for uleb128 values. As a consequence it needs to be
    possible to specify an alternative.

    This also switches RISCV to use DW_EH_PE_udata4 for call side encodings in

    Differential Revision: https://reviews.llvm.org/D63415
    Patch by Edward Jones. — asb / ViewSVN

rL:366328 - C:366325 - #63296 (Jul 17, 2019 7:04:41 AM)

  1. Mips: Remove immarg from copy and insert intrinsics

    These intrinsics do in fact work with non-constant index arguments.

    These are lowered to either the generic
    VEXTRACT_SEXT_ELT. The handling of these all accept variable
    indexes. Turning these into generic instructions which do allow
    variables introduces complications in a future change to immarg

    Since these just turn into generic instructions, these are kind of
    pointless and should probably just be autoupgraded to
    extractelement/insertelement. — arsenm / ViewSVN
  2. [RISCV] Set correct encodings for DWARF exception handling

    This patch sets correct encodings for DWARF exception handling for RISC-V
    (other than call site encoding, which must be udata4 rather than uleb128 and
    is handled by D63415).

    This has the same intend as D63409, except this version matches GCC/binutils
    behaviour which uses the same encodings regardless of PIC/non-PIC and
    medlow/medany code model. — asb / ViewSVN
  3. [RISCV][NFC] Add tests that capture current encodings for DWARF EH

    Items which are known to be wrong/different vs GCC are marked as TODO and will
    be address in follow-up patches. — asb / ViewSVN
  4. [ASTImporter] Fix LLDB lookup in transparent ctx and with ext src

    With LLDB we use localUncachedLookup(), however, that fails to find
    Decls when a transparent context is involved and the given DC has
    external lexical storage.  The solution is to use noload_lookup, which
    works well with transparent contexts.  But, we cannot use only the
    noload_lookup since the slow case of localUncachedLookup is still needed
    in some other cases.

    These other cases are handled in ASTImporterLookupTable, but we cannot
    use that with LLDB since that traverses through the AST which initiates
    the load of external decls again via DC::decls().

    We must avoid loading external decls during the import becuase
    ExternalASTSource is implemented with ASTImporter, so external loads
    during import results in uncontrolled and faulty import.

    Reviewers: shafik, teemperor, jingham, clayborg, a_sidorin, a.sidorin

    Subscribers: rnkovacs, dkrupp, Szelethus, gamesh411, cfe-commits, lldb-commits

    Tags: #clang, #lldb

    Differential Revision: https://reviews.llvm.org/D61333 — martong / ViewSVN
  5. [llvm-ar][test] \r\n -> \n

    Also simplify some empty output tests with 'count 0' — maskray / ViewSVN
  6. [AMDGPU] Optimize atomic AND/OR/XOR

    Summary: Extend the atomic optimizer to handle AND, OR and XOR.

    Reviewers: arsenm, sheredom

    Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, jfb, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64809 — foad / ViewSVN
  7. [AArch64] Add support for Transactional Memory Extension (TME)

    TME is a future architecture technology, documented in


    More about the future architectures:


    This patch adds support for the TME instructions TSTART, TTEST, TCOMMIT, and
    TCANCEL and the target feature/arch extension "tme".

    It also implements TME builtin functions, defined in ACLE Q2 2019

    Patch by Javed Absar and Momchil Velikov

    Differential Revision: https://reviews.llvm.org/D64416 — chill / ViewSVN

rL:366319 - C:366315 - #63295 (Jul 17, 2019 5:41:38 AM)

  1. PowerPC: Fix register spilling for SPE registers

    Missed in the original commit, use the correct callee-saved register
    list for spilling, instead of the standard SVR432 list.  This avoids
    needlessly spilling the SPE non-volatile registers when they're not used.

    As part of this, also add where missing, and sort, the spill opcode
    checks for SPE and SPE4 register classes.

    Reviewers: nemanjai, hfinkel, joerg

    Subscribers: kbarton, jsji, llvm-commits

    Differential Revision: https://reviews.llvm.org/D56703 — jhibbits / ViewSVN
  2. PowerPC/SPE: Fix load/store handling for SPE

    Pointed out in a comment for D49754, register spilling will currently
    spill SPE registers at almost any offset.  However, the instructions
    `evstdd` and `evldd` require a) 8-byte alignment, and b) a limit of 256
    (unsigned) bytes from the base register, as the offset must fix into a
    5-bit offset, which ranges from 0-31 (indexed in double-words).

    The update to the register spill test is taken partially from the test
    case shown in D49754.

    Additionally, pointed out by Kei Thomsen, globals will currently use
    evldd/evstdd, though the offset isn't known at compile time, so may
    exceed the 8-bit (unsigned) offset permitted.  This fixes that as well,
    by forcing it to always use evlddx/evstddx when accessing globals.

    Part of the patch contributed by Kei Thomsen.

    Reviewers: nemanjai, hfinkel, joerg

    Subscribers: kbarton, jsji, llvm-commits

    Differential Revision: https://reviews.llvm.org/D54409 — jhibbits / ViewSVN
  3. [MIPS GlobalISel] ClampScalar and select pointer G_ICMP

    Add narrowScalar to half of original size for G_ICMP.
    ClampScalar G_ICMP's operands 2 and 3 to to s32.
    Select G_ICMP for pointers for MIPS32. Pointer compare is same
    as for integers, it is enough to declare them as legal type.

    Differential Revision: https://reviews.llvm.org/D64856 — petar.avramovic / ViewSVN

rL:366314 - C:366315 - #63294 (Jul 17, 2019 4:35:28 AM)

  1. [AArch64] Consistent types and naming for AArch64 target features (NFC)

    Differential Revision: https://reviews.llvm.org/D64415

    Committed as obvious. — chill / ViewSVN
  2. AMDGPU/GFX10: Apply the VMEM-to-scalar-write hazard also to writes to EXEC

    Summary: Change-Id: I854fbf7d48e937bef9f8f3f5d0c8aeb970652630

    Reviewers: rampitec, mareko

    Subscribers: arsenm, kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64807

    Change-Id: I4405b3a7f84186acea5a78d291bff71056e745fc — nha / ViewSVN
  3. AMDGPU: Improve alias analysis for GDS

    Summary: GDS cannot alias anything else.

    Original patch by: Marek Olšák

    Reviewers: arsenm, mareko

    Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, Petar.Avramovic, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64114

    Change-Id: I07bfbd96f5d5c37a6dfba7997df12f291dd794b0 — nha / ViewSVN
  4. [TableGen] Do not set ReadNone attribute on intrinsics with side effects

    If an intrinsic is defined without outputs, but having side effects,
    it still can be removed completely from the program. This patch makes
    TableGen not set Attribute::ReadNone for intrinsics which
    are declared with IntrHasSideEffects.

    Differential Revision: https://reviews.llvm.org/D64414 — chill / ViewSVN

rL:366308 - C:366306 - #63292 (Jul 17, 2019 3:05:35 AM)

  1. [ARM GlobalISel] Cleanup CallLowering. NFC

    Migrate CallLowering::lowerReturnVal to use the same infrastructure as
    lowerCall/FormalArguments and remove the now obsolete code path from

    Forgot to push this earlier. — rovka / ViewSVN

rL:366303 - C:366306 - #63291 (Jul 17, 2019 1:59:23 AM)

  1. [OpenCL][Sema] Minor refactoring and constraint checking

    Simplify code a bit and add assertion to address post-landing comments
    from D64083.

    Subscribers: yaxunl, Anastasia, cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D64804 — mantognini / ViewSVN

rL:366303 - C:366305 - #63290 (Jul 17, 2019 1:53:07 AM)

  1. [Driver] Enable __cxa_atexit on Solaris

    Starting with Solaris 11.4 (which is now the required minimal version), Solaris does
    support __cxa_atexit.  This patch reflects that.

    One might consider removing the affected tests altogether instead of inverting them,
    as is done on other targets.

    Besides, this lets two ASan tests PASS:

      AddressSanitizer-i386-sunos :: TestCases/init-order-atexit.cc
      AddressSanitizer-i386-sunos-dynamic :: TestCases/init-order-atexit.cc

    Tested on x86_64-pc-solaris2.11 and sparcv9-sun-solaris2.11.

    Differential Revision: https://reviews.llvm.org/D64491 — ro / ViewSVN

rL:366303 - C:366286 - #63289 (Jul 17, 2019 1:15:37 AM)

  1. [mips] Remove redundant test case. NFC

    The `inlineasm-constraint-reg64.ll` test checks the same functionality. — atanasyan / ViewSVN
  2. [mips] Name inline asm constraint test cases in a uniform manner. NFC — atanasyan / ViewSVN
  3. [mips] Use mult/mflo pattern on 64-bit targets prior to MIPS64

    The `MUL` instruction is available starting from the MIPS32/MIPS64 targets. — atanasyan / ViewSVN
  4. [mips] Implement .cplocal directive

    This directive forces to use the alternate register for context pointer.
    For example, this code:
      .cplocal $4
      jal foo
    expands to:
      ld    $25, %call16(foo)($4)
      jalr  $25

    Differential Revision: https://reviews.llvm.org/D64743 — atanasyan / ViewSVN
  5. [mips] Support the "o" inline asm constraint

    As well as other LLVM targets we do not handle "offsettable"
    memory addresses in any special way. In other words, the "o" constraint
    is an exact equivalent of the "m" one. But some existing code require
    the "o" constraint support.

    This fixes PR42589.

    Differential Revision: https://reviews.llvm.org/D64792 — atanasyan / ViewSVN

rL:366294 - C:366286 - #63288 (Jul 17, 2019 12:10:34 AM)

  1. [LoopInfo] Fix getUniqueNonLatchExitBlocks

    It is possible that exit block has two predecessors and one of them is a latch
    block while another is not.

    Current algorithm is based on the assumption that all exits are dedicated
    and therefore we can check only first predecessor of loop exit to find all unique

    However if we do not consider latch block and it is first predecessor of some
    exit then this exit will be found.

    Regression test is added.

    As a side effect of algorithm re-writing, the restriction that all exits are dedicated
    is eliminated.

    Reviewers: reames, fhahn, efriedma
    Reviewed By: efriedma
    Subscribers: llvm-commits
    Differential Revision: https://reviews.llvm.org/D64787 — skatkov / ViewSVN

rL:366291 - C:366286 - #63287 (Jul 17, 2019 12:05:35 AM)

  1. Update email address. — chaofan / ViewSVN

rL:366283 - C:366286 - #63284 (Jul 16, 2019 5:05:39 PM)

  1. AMDGPU: Add some missing builtins — arsenm / ViewSVN

rL:366283 - C:366284 - #63283 (Jul 16, 2019 4:45:35 PM)

  1. Fix OpenCLCXX test on 32-bit Windows where thiscall is present — rnk / ViewSVN
  2. [AMDGPU] Autogenerate register asm names

    Differential Revision: https://reviews.llvm.org/D64839 — rampitec / ViewSVN

rL:366280 - C:366282 - #63282 (Jul 16, 2019 4:40:38 PM)

  1. Fix darwin-ld.c if dsymutil.exe exists on PATH — rnk / ViewSVN

rL:366280 - C:366276 - #63281 (Jul 16, 2019 4:00:18 PM)

  1. ARM: Fix missing immarg for space intrinsic — arsenm / ViewSVN
  2. GlobalISel: Add overload of handleAssignments with CCState

    AMDGPU needs to allocate special argument registers separately from
    the user function argument list, so needs direct control over the

    The ArgLocs argument is only really necessary because CCState doesn't
    allow access to it. — arsenm / ViewSVN
  3. [TableGen] Generate offsets into a flat array for getOperandType

    Rather than an array of std::initializer_list, generate a table of
    offsets and a flat array of the operands for getOperandType. This is a
    bit more efficient on platforms that don't manage to get the array of
    inintializer_lists initialized at link time (I'm looking at you
    macOS). It's also quite quite a bit faster to compile. — bogner / ViewSVN

rL:366275 - C:366276 - #63280 (Jul 16, 2019 3:37:12 PM)

  1. Fix a typo in target features

    There was a slight typo in r364352 that ended up causing our backend to
    complain on some x86 Android builds. This CL fixes that.

    Differential Revision: https://reviews.llvm.org/D64781 — gbiv / ViewSVN

rL:366275 - C:366272 - #63279 (Jul 16, 2019 3:25:37 PM)

  1. [WebAssembly] Compile all TLS on Emscripten as local-exec

    Currently, on Emscripten, dynamic linking is not supported with threads.
    This means that if thread-local storage is used, it must be used in a
    statically-linked executable. Hence, local-exec is the only possible model.

    This diff compiles all TLS variables to use local-exec on Emscripten as a
    temporary measure until dynamic linking is supported with threads.

    The goal for this is to allow C++ types with constructors to be thread-local.

    Currently, when `clang` compiles a `thread_local` variable with a constructor,
    it generates `__tls_guard` variable:

        @__tls_guard = internal thread_local global i8 0, align 1

    As no TLS model is specified, this is treated as general-dynamic, which we do
    not support (and cannot support without implementing dynamic linking support
    with threads in Emscripten). As a result, any C++ constructor in `thread_local`
    variables would not compile.

    By compiling all `thread_local` as local-exec, `__tls_guard` will compile and
    we can support C++ constructors with TLS without implementing dynamic linking
    with threads.

    Depends on D64537

    Reviewers: tlively, aheejin, sbc100

    Reviewed By: aheejin

    Subscribers: dschuff, jgravelle-google, hiraditya, sunfish, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64776 — quantum / ViewSVN

rL:366274 - C:366272 - #63278 (Jul 16, 2019 3:15:59 PM)

  1. [TableGen] Add "getOperandType" to get operand types from opcode/opidx

    The InstrInfoEmitter outputs an enum called "OperandType" which gives
    numerical IDs to each operand type. This patch makes use of this enum
    to define a function called "getOperandType", which allows looking up
    the type of an operand given its opcode and operand index.

    Patch by Nicolas Guillemot. Thanks!

    Differential Revision: https://reviews.llvm.org/D63320 — bogner / ViewSVN
  2. [WebAssembly] Implement thread-local storage (local-exec model)

    Thread local variables are placed inside a `.tdata` segment. Their symbols are
    offsets from the start of the segment. The address of a thread local variable
    is computed as `__tls_base` + the offset from the start of the segment.

    `.tdata` segment is a passive segment and `memory.init` is used once per thread
    to initialize the thread local storage.

    `__tls_base` is a wasm global. Since each thread has its own wasm instance,
    it is effectively thread local. Currently, `__tls_base` must be initialized
    at thread startup, and so cannot be used with dynamic libraries.

    `__tls_base` is to be initialized with a new linker-synthesized function,
    `__wasm_init_tls`, which takes as an argument a block of memory to use as the
    storage for thread locals. It then initializes the block of memory and sets
    `__tls_base`. As `__wasm_init_tls` will handle the memory initialization,
    the memory does not have to be zeroed.

    To help allocating memory for thread-local storage, a new compiler intrinsic
    is introduced: `__builtin_wasm_tls_size()`. This instrinsic function returns
    the size of the thread-local storage for the current function.

    The expected usage is to run something like the following upon thread startup:


    Reviewers: tlively, aheejin, kripken, sbc100

    Subscribers: dschuff, jgravelle-google, hiraditya, sunfish, jfb, cfe-commits, llvm-commits

    Tags: #clang, #llvm

    Differential Revision: https://reviews.llvm.org/D64537 — quantum / ViewSVN

rL:366271 - C:366267 - #63277 (Jul 16, 2019 3:01:43 PM)

  1. AMDGPU: Partially revert r366250

    GCCBuiltin doesn't work for these, because they have a mangled type
    (although they arguably should not). — arsenm / ViewSVN

rL:366270 - C:366267 - #63276 (Jul 16, 2019 2:49:01 PM)

  1. [ORC][docs] Fix an RST error: the code-block directive needs a newline after it. — lhames / ViewSVN

rL:366269 - C:366267 - #63275 (Jul 16, 2019 2:44:55 PM)

  1. [ORC][docs] Trim ORCv1 to ORCv2 transition section, add a how-to section. — lhames / ViewSVN
  2. [x86] use more phadd for reductions

    This is part of what is requested by PR42023:

    There's an extension needed for FP add, but exactly how we would specify
    that using flags is not clear to me, so I left that as a TODO.
    We're still missing patterns for partial reductions when the input vector
    is 256-bit or 512-bit, but I think that's a failure of vector narrowing.
    If we can reduce the widths, then this matching should work on those tests.

    Differential Revision: https://reviews.llvm.org/D64760 — spatel / ViewSVN
  3. [clang-format] Don't detect call to ObjC class method as C++11 attribute specifier

    Previously, clang-format detected something like the following as a C++11 attribute specifier.

      @[[NSArray class]]

    instead of an array with an Objective-C method call inside. In general, when the attribute specifier checking runs, if it sees 2 identifiers in a row, it decides that the square brackets represent an Objective-C method call. However, here, `class` is tokenized as a keyword instead of an identifier, so this check fails.

    To fix this, the attribute specifier first checks whether the first square bracket has an "@" before it. If it does, then that square bracket is not the start of a attribute specifier because it is an Objective-C array literal. (The assumption is that @[[.*]] is not valid C/C++.)

    Contributed by rkgibson2.

    Reviewers: benhamilton

    Reviewed By: benhamilton

    Subscribers: aaron.ballman, cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D64632 — benhamilton / ViewSVN

rL:366264 - C:366231 - #63274 (Jul 16, 2019 2:15:35 PM)

  1. DWARF: Skip zero column for inline call sites

    D64033 <https://reviews.llvm.org/D64033> added DW_AT_call_column for
    inline sites. However, that change wasn't aware of "-gno-column-info".
    To avoid adding column info when "-gno-column-info" is used, now
    DW_AT_call_column is only added when we have non-zero column (when
    "-gno-column-info" is used, column will be zero).

    Patch by Wenlei He!

    Differential Revision: https://reviews.llvm.org/D64784 — dblaikie / ViewSVN

rL:366257 - C:366231 - #63273 (Jul 16, 2019 1:40:47 PM)

  1. AMDGPU/GlobalISel: Select G_ASHR — arsenm / ViewSVN

rL:366256 - C:366231 - #63272 (Jul 16, 2019 1:32:01 PM)

  1. AMDGPU/GlobalISel: Select G_LSHR — arsenm / ViewSVN
  2. [PowerPC][HTM] Fix impossible reg-to-reg copy assert with ttest builtin

    This is exposed by our internal testing.
    The reduced testcase will assert with "Impossible reg-to-reg copy"

    We can't use COPY to do 32-bit to 64-bit conversion.

    Reviewers: kbarton, hfinkel, nemanjai

    Reviewed By: hfinkel

    Subscribers: hiraditya, MaskRay, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64499 — jsji / ViewSVN
  3. AMDGPU/GlobalISel: Select G_SHL

    I think this manages to not break the DAG handling with the divergent
    predicates because the stadalone divergent patterns end up with a
    higher priority than the pattern on the instruction definition.

    The 16-bit versions don't work yet. — arsenm / ViewSVN

rL:366252 - C:366231 - #63271 (Jul 16, 2019 1:10:39 PM)

  1. [AMDGPU] Change register type for v32 vectors

    When it is AReg_1024 this results in unnecessary copying into
    AGPRs of a 32 element vectors even though they are not intended
    for an mfma instruction.

    Differential Revision: https://reviews.llvm.org/D64815 — rampitec / ViewSVN

rL:366249 - C:366231 - #63268 (Jul 16, 2019 12:31:17 PM)

  1. AMDGPU/GlobalISel: Fix selection of private stores — arsenm / ViewSVN

rL:366248 - C:366231 - #63267 (Jul 16, 2019 12:25:40 PM)

  1. AMDGPU/GlobalISel: Select private loads — arsenm / ViewSVN

rL:366246 - C:366231 - #63266 (Jul 16, 2019 12:02:01 PM)

  1. AMDGPU/GlobalISel: Select flat stores — arsenm / ViewSVN

rL:366242 - C:366231 - #63265 (Jul 16, 2019 11:37:12 AM)

  1. AMDGPU: Add register classes to flat store patterns

    For some reason GlobalISelEmitter needs register classes to import
    these, although it works for the load patterns. — arsenm / ViewSVN

rL:366241 - C:366231 - #63264 (Jul 16, 2019 11:27:52 AM)

  1. [IndVars] Speculative fix for an assertion failure seen in bots

    I don't have an IR sample which is actually failing, but the issue described in the comment is theoretically possible, and should be guarded against even if there's a different root cause for the bot failures. — reames / ViewSVN
  2. AMDGPU: Replace store PatFrags

    Convert the easy cases to formats understood for GlobalISel. — arsenm / ViewSVN
  3. AMDGPU/GlobalISel: Select flat loads

    Now that the patterns use the new PatFrag address space support, the
    only blocker to importing most load patterns is the addressing mode
    complex patterns. — arsenm / ViewSVN
  4. Teach `llvm-pdbutil pretty -native` about `-injected-sources`

    `pretty -native -injected-sources -injected-source-content` works with
    this patch, and produces identical output to the dia version.

    Differential Revision: https://reviews.llvm.org/D64428 — nico / ViewSVN

rL:366235 - C:366231 - #63263 (Jul 16, 2019 10:58:27 AM)

  1. [AMDGPU] Optimize atomic max/min

    Extend the atomic optimizer to handle signed and unsigned max and min
    operations, as well as add and subtract.

    Reviewers: arsenm, sheredom, critson, rampitec

    Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, jfb, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64328 — foad / ViewSVN

rL:366234 - C:366231 - #63262 (Jul 16, 2019 10:40:38 AM)

  1. AMDGPU: Redefine load PatFrags

    Rewrite PatFrags using the new PatFrag address space matching in
    tablegen. These will now work with both SelectionDAG and GlobalISel. — arsenm / ViewSVN

rL:366230 - C:366231 - #63261 (Jul 16, 2019 10:25:37 AM)

  1. fix unnamed fiefield issue and add tests for __builtin_preserve_access_index intrinsic

    The original commit is r366076. It is temporarily reverted (r366155)
    due to test failure. This resubmit makes test more robust by accepting
    regex instead of hardcoded names/references in several places.

    This is a followup patch for https://reviews.llvm.org/D61809.
    Handle unnamed bitfield properly and add more test cases.

    Fixed the unnamed bitfield issue. The unnamed bitfield is ignored
    by debug info, so we need to ignore such a struct/union member
    when we try to get the member index in the debug info.

    D61809 contains two test cases but not enough as it does
    not checking generated IRs in the fine grain level, and also
    it does not have semantics checking tests.
    This patch added unit tests for both code gen and semantics checking for
    the new intrinsic.

    Signed-off-by: Yonghong Song <yhs@fb.com> — yhs / ViewSVN
  2. AMDGPU: Fix missing immarg for mfma intrinsics — arsenm / ViewSVN

rL:366223 - C:366212 - #63260 (Jul 16, 2019 9:00:37 AM)

  1. [AMDGPU] Add the adjusted FP as a livein register.

    Reviewers: arsenm, rampitec

    Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64145 — hliao / ViewSVN
  2. [Strict FP] Allow more relaxed scheduling

    Reimplement scheduling constraints for strict FP instructions in
    ScheduleDAGInstrs::buildSchedGraph to allow for more relaxed
    scheduling.  Specifially, allow one strict FP instruction to
    be scheduled across another, as long as it is not moved across
    any global barrier.

    Differential Revision: https://reviews.llvm.org/D64412

    Reviewed By: cameron.mcinally — uweigand / ViewSVN

rL:366219 - C:366212 - #63259 (Jul 16, 2019 8:55:59 AM)

  1. Revert [tools] [llvm-nm] Default to reading from stdin not a.out

    This reverts r365889 (git commit 60c81354b1d3fced1bd284d334f118d2d792ab4b) — abrachet / ViewSVN

rL:366218 - C:366212 - #63258 (Jul 16, 2019 8:30:54 AM)

  1. Add missing test for r366215 — aemerson / ViewSVN
  2. [Remarks] Simplify and refactor the RemarkParser interface

    Before, everything was based on some kind of type erased parser
    implementation which container a lot of boilerplate code when multiple
    formats were to be supported.

    This simplifies it by:

    * the remark now owns its arguments
    * *always* returning an error from the implementation side
    * working around the way the YAML parser reports errors: catch them through
    callbacks and re-insert them in a proper llvm::Error
    * add a CParser wrapper that is used when implementing the C API to
    avoid cluttering the C++ API with useless state
    * LLVMRemarkParserGetNext now returns an object that needs to be
    released to avoid leaking resources
    * add a new API to dispose of a remark entry: LLVMRemarkEntryDispose — thegameg / ViewSVN
  3. [Remarks][NFC] Combine ParserFormat and SerializerFormat

    It's useless to have both. — thegameg / ViewSVN
  4. [ADCE] Fix non-deterministic behaviour due to iterating over a pointer set.

    Original patch by Yann Laigle-Chapuy

    Differential Revision: https://reviews.llvm.org/D64785 — aemerson / ViewSVN

rL:366214 - C:366212 - #63257 (Jul 16, 2019 8:20:40 AM)

  1. [DAGCombiner] fold (addcarry (xor a, -1), b, c) -> (subcarry b, a, !c) and flip carry.

    As per title. DAGCombiner only mathes the special case where b = 0, this patches extends the pattern to match any value of b.

    Depends on D57302

    Reviewers: hfinkel, RKSimon, craig.topper

    Subscribers: llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D59208 — deadalnix / ViewSVN

rL:366210 - C:366212 - #63256 (Jul 16, 2019 8:00:38 AM)

  1. [OpenCL] Fixing sampler initialisations for C++ mode.

    Allow conversions between integer and sampler type.

    Differential Revision: https://reviews.llvm.org/D64791 — neil.hickey / ViewSVN

rL:366210 - C:366211 - #63255 (Jul 16, 2019 7:55:39 AM)

  1. [OPENMP]Add support for analysis of if clauses.

    Added support for analysis of if clauses in the OpenMP directives to be
    able to check for the use of uninitialized variables.

    Reviewers: NoQ

    Subscribers: guansong, jfb, jdoerfert, caomhin, kkwli0, cfe-commits

    Tags: clang

    Differential Revision: https://reviews.llvm.org/D64646 — abataev / ViewSVN

rL:366210 - C:366202 - #63254 (Jul 16, 2019 7:30:37 AM)

  1. AMDGPU/GlobalISel: Fix test failures in release build

    Apparently the check for legal instructions during instruction
    select does not happen without an asserts build, so these would
    successfully select in release, and fail in debug.

    Make s16 and/or/xor legal. These can just be selected directly
    to the 32-bit operation, as is already done in SelectionDAG, so just
    make them legal. — arsenm / ViewSVN
  2. [llvm-ar][test] Add to llvm-ar test coverage

    This change adds tests to cover existing llvm-ar functionality.
    print.test is omitted due to failing on Darwin.

    Differential Revision: https://reviews.llvm.org/D64330 — gbreynoo / ViewSVN

rL:366206 - C:366202 - #63253 (Jul 16, 2019 5:55:39 AM)

  1. Reapply [llvm-ar][test] Increase llvm-ar test coverage

    This reapplies 365316 without extract.test due to failing on Darwin.

    Differential Revision: https://reviews.llvm.org/D63935 — gbreynoo / ViewSVN

rL:366205 - C:366202 - #63252 (Jul 16, 2019 5:10:36 AM)

  1. remove a duplicate declaration — sylvestre / ViewSVN

rL:366204 - C:366202 - #63251 (Jul 16, 2019 5:00:39 AM)

  1. Document the LLVM_ENABLE_BINDINGS option — sylvestre / ViewSVN

rL:366203 - C:366202 - #63250 (Jul 16, 2019 4:14:44 AM)

  1. [Object/llvm-readelf/llvm-readobj] - Improve error reporting when e_shstrndx is broken.

    When e_shstrndx is broken, it is impossible to get a section name.
    In this patch I improved the error message we show and
    added tests for Object and for llvm-readelf/llvm-readobj

    Message was changed in two places:
    1) llvm-readelf/llvm-readobj previously used a code from Object/ELF.h,
    now they have a modified version of it (it has less checks and allows
    dumping broken things).
    2) Code in Object/ELF.h is still used for generic cases.

    Differential revision: https://reviews.llvm.org/D64714 — grimar / ViewSVN
  2. [Driver] Don't pass --dynamic-linker to ld on Solaris

    I noticed that clang currently passes --dynamic-linker to ld.  This has been the case
    since Solaris 11 support was added initially back in 2012 by David Chisnall (r150580).
    I couldn't find any patch submission, let alone a justification, for this, and it seems
    completely useless: --dynamic-linker is a gld compatibility form of the option, the
    native option being -I.  First of all, however, the dynamic linker passed is simply the
    default, so there's no reason at all to specify it in the first place.

    This patch removes passing the option and adjusts the affected testcase accordingly.

    Tested on x86_64-pc-solaris2.11 and sparcv9-sun-solaris2.11.

    Differential Revision: https://reviews.llvm.org/D64493 — ro / ViewSVN

rL:366201 - C:366200 - #63249 (Jul 16, 2019 4:05:37 AM)

  1. Reapply [llvm-ar][test] Add to MRI test coverage

    This reapplies 363232 without mri-utf8.test due to failing on Darwin.

    Differential Revision: https://reviews.llvm.org/D63197 — gbreynoo / ViewSVN

rL:366198 - C:366200 - #63248 (Jul 16, 2019 3:30:37 AM)

  1. [SemaTemplate] Fix uncorrected typos after pack expansion

    This case is particularly important for clangd, as it is triggered after
    inserting the snippet for variadic functions.

    Reviewers: kadircet, ilya-biryukov

    Subscribers: llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64677 — sammccall / ViewSVN

rL:366198 - C:366197 - #63247 (Jul 16, 2019 3:15:40 AM)

  1. Remove username from git-llvm script, erroneously added in 366197 — sammccall / ViewSVN

rL:366197 - C:366197 - #63246 (Jul 16, 2019 2:34:07 AM)

  1. [AArch64] Implement __jcvt intrinsic from Armv8.3-A

    The jcvt intrinsic defined in ACLE [1] is available when ARM_FEATURE_JCVT is defined.

    This change introduces the AArch64 intrinsic, wires it up to the instruction and a new clang builtin function.
    The __ARM_FEATURE_JCVT macro is now defined when an Armv8.3-A or higher target is used.
    I've implemented the target detection logic in Clang so that this feature is enabled for architectures from armv8.3-a onwards (so -march=armv8.4-a also enables this, for example).

    make check-all didn't show any new failures.

    [1] https://developer.arm.com/docs/101028/latest/data-processing-intrinsics

    Differential Revision: https://reviews.llvm.org/D64495 — ktkachov / ViewSVN

rL:366195 - C:366194 - #63245 (Jul 16, 2019 2:15:40 AM)

  1. [NFC] Test commit: add full stop at end of comment — ktkachov / ViewSVN

rL:366191 - C:366194 - #63244 (Jul 16, 2019 2:00:38 AM)

  1. [clang-scan-view] Force utf-8 when handling report (python2 only)

    Original patch by random human <random.bored.human@gmail.com>

    Differential Revision: https://reviews.llvm.org/D64129 — serge_sans_paille / ViewSVN

rL:366191 - C:366186 - #63243 (Jul 16, 2019 12:55:40 AM)

  1. [NFC][PowerPC] Add test case for D64195 — wuzish / ViewSVN

rL:366190 - C:366186 - #63242 (Jul 16, 2019 12:05:40 AM)

  1. [DWARF] Fix the reserved values for unit length in DWARFDebugLine.

    The DWARF3 documentation had inconsistency concerning the reserved range
    for unit length values. The issue was fixed in DWARF4.

    Differential Revision: https://reviews.llvm.org/D64622 — ikudrin / ViewSVN

rL:366189 - C:366186 - #63241 (Jul 16, 2019 12:00:37 AM)

  1. [DWARF] Fix an incorrect format specifier.

    This adjusts the format specifier because PCOffset is uint16_t.

    Differential Revision: https://reviews.llvm.org/D64620 — ikudrin / ViewSVN

rL:366188 - C:366186 - #63240 (Jul 15, 2019 11:55:39 PM)

  1. [DWARF] Simplify DWARFAttribute. NFC.

    The first argument in the constructor was ignored, and the remaining
    arguments were always passed as their defaults.

    Differential Revision: https://reviews.llvm.org/D64407 — ikudrin / ViewSVN

rL:366182 - C:366186 - #63239 (Jul 15, 2019 11:25:41 PM)

  1. Finish "Adapt -fsanitize=function to SANITIZER_NON_UNIQUE_TYPEINFO"

    i.e., recent 5745eccef54ddd3caca278d1d292a88b2281528b:

    * Bump the function_type_mismatch handler version, as its signature has changed.

    * The function_type_mismatch handler can return successfully now, so
      SanitizerKind::Function must be AlwaysRecoverable (like for

    * But the minimal runtime would still unconditionally treat a call to the
      function_type_mismatch handler as failure, so disallow -fsanitize=function in
      combination with -fsanitize-minimal-runtime (like it was already done for

    * Add tests.

    Differential Revision: https://reviews.llvm.org/D61479 — sberg / ViewSVN

rL:366182 - C:366177 - #63238 (Jul 15, 2019 10:55:41 PM)

  1. [X86] In combineStore, don't convert v2f32 load/store pairs to f64 loads/stores.

    Type legalization can take care of this. This gives DAG combine
    a little more time with the original types. — ctopper / ViewSVN

rL:366179 - C:366177 - #63237 (Jul 15, 2019 10:03:38 PM)

  1. [RISCV] Match GNU tools canonical JALR and add aliases

    The canonical GNU form of JALR resembles a load/store instruction rather
    than placing the immediate offset as a separate argument, so match this
    behaviour. Also add parser-only aliases for the three-operand form, and
    add other shorter aliases also emitted by GNU tools.

    Differential Revision: https://reviews.llvm.org/D55277
    Patch by James Clarke. — asb / ViewSVN

rL:366177 - C:366177 - #63236 (Jul 15, 2019 9:50:38 PM)

  1. Fix parameter name comments using clang-tidy. NFC.

    This patch applies clang-tidy's bugprone-argument-comment tool
    to LLVM, clang and lld source trees. Here is how I created this

    $ git clone https://github.com/llvm/llvm-project.git
    $ cd llvm-project
    $ mkdir build
    $ cd build
    $ cmake -GNinja -DCMAKE_BUILD_TYPE=Debug \
        -DLLVM_ENABLE_PROJECTS='clang;lld;clang-tools-extra' \
        -DCMAKE_C_COMPILER=clang -DCMAKE_CXX_COMPILER=clang++ ../llvm
    $ ninja
    $ parallel clang-tidy -checks='-*,bugprone-argument-comment' \
        -config='{CheckOptions: [{key: StrictMode, value: 1}]}' -fix \
        ::: ../llvm/lib/**/*.{cpp,h} ../clang/lib/**/*.{cpp,h} ../lld/**/*.{cpp,h} — ruiu / ViewSVN

rL:366176 - C:366169 - #63235 (Jul 15, 2019 9:40:38 PM)

  1. [RISCV] Avoid overflow when determining number of nops for code align

    RISCVAsmBackend::shouldInsertExtraNopBytesForCodeAlign() assumed that the
    align specified would be greater than or equal to the minimum nop length, but
    that is not always the case - for example if a user specifies ".align 0" in

    Differential Revision: https://reviews.llvm.org/D63274
    Patch by Edward Jones. — asb / ViewSVN
  2. [RISCV] Fix a potential issue in shouldInsertFixupForCodeAlign()

    The bool result of shouldInsertExtraNopBytesForCodeAlign() is not checked but
    the returned nop count is unconditionally read even though it could be

    Differential Revision: https://reviews.llvm.org/D63285
    Patch by Edward Jones. — asb / ViewSVN

rL:366174 - C:366169 - #63234 (Jul 15, 2019 9:05:18 PM)

  1. [RISCV][NFC] Split PseudoCALL pattern out from instruction

    Since PseudoCALL defines AsmString, it can be generated from assembly,
    and so code-gen patterns should be defined separately to be consistent
    with the style of the RISCV backend. Other pseudo-instructions exist
    that have code-gen patterns defined directly, but these instructions are
    purely for code-gen and cannot be written in assembly.

    Differential Revision: https://reviews.llvm.org/D64012
    Patch by James Clarke. — asb / ViewSVN

rL:366173 - C:366169 - #63233 (Jul 15, 2019 8:56:00 PM)

  1. [RISCV][NFC] Fix HasStedExtA -> HasStdExtA typo in comment

    Differential Revision: https://reviews.llvm.org/D64011
    Patch by James Clarke. — asb / ViewSVN
  2. [RISCV] Make RISCVELFObjectWriter::getRelocType check IsPCRel

    Previously, this function didn't check the IsPCRel argument. But doing so is a
    useful check for errors, and also seemingly necessary for FK_Data_4 (which we
    produce a R_RISCV_32_PCREL relocation for if IsPCRel).

    Other than R_RISCV_32_PCREL, this should be NFC. Future exception handling
    related patches will include tests that capture this behaviour. — asb / ViewSVN

rL:366171 - C:366169 - #63232 (Jul 15, 2019 8:36:48 PM)

  1. hwasan: Pad arrays with non-1 size correctly.

    Spotted by eugenis.

    Differential Revision: https://reviews.llvm.org/D64783 — pcc / ViewSVN

rL:366168 - C:366169 - #63231 (Jul 15, 2019 8:20:40 PM)

  1. Revert "[OPENMP]Add support for analysis of if clauses."

    This reverts commit rL366068.
    The patch broke 86 tests under clang/test/OpenMP/ when run with address sanitizer. — tamur / ViewSVN

rL:366168 - C:366166 - #63230 (Jul 15, 2019 7:50:41 PM)

  1. AMDGPU: Avoid code predicates for extload PatFrags

    Use the MemoryVT field. This will be necessary for tablegen to
    automatically handle patterns for GlobalISel.

    Doesn't handle the d16 lo/hi patterns. Those are a special case since
    it involvess the custom node type. — arsenm / ViewSVN

rL:366164 - C:366166 - #63229 (Jul 15, 2019 7:10:39 PM)

  1. Change a lit test to permit vendor specific clang version

    A test manually checks for the string `__VERSION__ "Clang`. This needs
    to permit vendor specific variants. — lanza / ViewSVN

rL:366164 - C:366165 - #63228 (Jul 15, 2019 6:53:39 PM)

  1. reland "add -fthinlto-index= option to clang-cl"

    This is a reland of r366146, adding in the previously missing '--'
    flag that prevents filenames from being interpreted as flags.

    Original description:
    This adds a -fthinlto-index= option to clang-cl, which allows it to
    be used to drive ThinLTO backend passes. This allows clang-cl to be
    used for distributed ThinLTO.

    Tags: #clang — inglorion / ViewSVN

rL:366164 - C:366163 - #63227 (Jul 15, 2019 6:25:38 PM)

  1. Re-land "[DebugInfo] Move function from line table to the prologue (NFC)"

    In LLDB, when parsing type units, we don't need to parse the whole line
    table. Instead, we only need to parse the "support files" from the line
    table prologue.

    To make that possible, this patch moves the respective functions from
    the LineTable into the Prologue. Because I don't think users of the
    LineTable should have to know that these files come from the Prologue,

    I've left the original methods in place, and made them redirect to the

    Differential revision: https://reviews.llvm.org/D64774 — jdevlieghere / ViewSVN

rL:366162 - C:366163 - #63226 (Jul 15, 2019 6:22:11 PM)

  1. [Sema] Suppress additional warnings for C's zero initializer

    D28148 relaxed some checks for assigning { 0 } to a structure for all C
    standards, but it failed to handle structures with non-integer
    subobjects. Relax -Wmissing-braces checks for such structures, and add
    some additional tests.

    This fixes PR39931.

    Patch By: al3xtjames

    Reviewed By: Lekensteyn

    Differential Revision: https://reviews.llvm.org/D61838 — lekensteyn / ViewSVN

rL:366162 - C:366159 - #63225 (Jul 15, 2019 6:08:13 PM)

  1. [InstructionSimplify] Apply sext/trunc after pointer stripping

    - As the pointer stripping could trace through `addrspacecast` now, need
      to sext/trunc the offset to ensure it has the same width as the
      pointer after stripping.

    Reviewers: jdoerfert

    Subscribers: hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64768 — hliao / ViewSVN

rL:366160 - C:366159 - #63224 (Jul 15, 2019 6:00:42 PM)

  1. Revert "[DebugInfo] Move function from line table to the prologue (NFC)"

    This broke LLD, which I didn't have enabled. — jdevlieghere / ViewSVN
  2. Allow for vendor prefixes in a list test

    Preprocessor/init.c contains a line that explicitly checks for the

    __VERSION__ "Clang{{.*}}

    It's valid to have a toolchain configured to emit a vendor prefix
    before the word Clang. e.g.

    __VERSION__ "Vendor Clang{{.*}}

    Subscribers: fedor.sergeev, cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D64772 — lanza / ViewSVN

rL:366158 - C:366157 - #63223 (Jul 15, 2019 5:40:42 PM)

  1. [DebugInfo] Move function from line table to the prologue (NFC)

    In LLDB, when parsing type units, we don't need to parse the whole line
    table. Instead, we only need to parse the "support files" from the line
    table prologue.

    To make that possible, this patch moves the respective functions from
    the LineTable into the Prologue. Because I don't think users of the
    LineTable should have to know that these files come from the Prologue,

    I've left the original methods in place, and made them redirect to the

    Differential revision: https://reviews.llvm.org/D64774 — jdevlieghere / ViewSVN

rL:366154 - C:366157 - #63222 (Jul 15, 2019 5:08:29 PM)

  1. Temporarily revert "add -fthinlto-index= option to clang-cl"

    This is causing testsuite failures on (at least) darwin release+asserts.

    This reverts commit r366146. — echristo / ViewSVN
  2. Temporarily Revert "fix unnamed fiefield issue and add tests for __builtin_preserve_access_index intrinsic"

    The commit had tests that would only work with names in the IR.

    This reverts commit r366076. — echristo / ViewSVN

rL:366154 - C:366153 - #63221 (Jul 15, 2019 4:47:28 PM)

  1. Temporarily Revert "[SLP] Recommit: Look-ahead operand reordering heuristic."

    As there are some reported miscompiles with AVX512 and performance regressions
    in Eigen. Verified with the original committer and testcases will be forthcoming.

    This reverts commit r364964. — echristo / ViewSVN
  2. Revert "[NewPM] Port Sancov"

    This reverts commit 5652f35817f07b16f8b3856d594cc42f4d7ee29c. — leonardchan / ViewSVN
  3. [DirectoryWatcher][linux] Fix for older kernels

    IN_EXCL_UNLINK exists since Linux 2.6.36

    Differential Revision: https://reviews.llvm.org/D64764 — jkorous / ViewSVN
  4. [X86] Teach convertToThreeAddress to handle SUB with immediate

    We mostly avoid sub with immediate but there are a couple cases that can create them. One is the add 128, %rax -> sub -128, %rax trick in isel. The other is when a SUB immediate gets created for a compare where both the flags and the subtract value is used. If we are unable to linearize the SelectionDAG to satisfy the flag user and the sub result user from the same instruction, we will clone the sub immediate for the two uses. The one that produces flags will eventually become a compare. The other will have its flag output dead, and could then be considered for LEA creation.

    I added additional test cases to add.ll to show the the sub -128 trick gets converted to LEA and a case where we don't need to convert it.

    This showed up in the current codegen for PR42571.

    Differential Revision: https://reviews.llvm.org/D64574 — ctopper / ViewSVN
  5. [WebAssembly] Add missing utility methods for exnref type

    This adds missing utility methods and copy instruction handling for
    `exnref` type and also adds tests.

    `tee` instruction tests are missing because `isTee` is currently only
    used in ExplicitLocals pass and testing that pass in mir requires
    serialization of stackified registers in mir files, which is a bit
    nontrivial because `MachineFunctionInfo` only has info of vreg numbers
    (which are large integers) but not the mir's register numbers. But this
    change is quite trivial anyway.

    Reviewers: tlively

    Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64705 — aheejin / ViewSVN
  6. [llvm-readelf] Print "File: lib.a(file.o)" info when dumping archive files.

    Match GNU readelf.


    Reviewers: jhenderson, grimar, MaskRay, rupprecht

    Reviewed by: jhenderson, MaskRay, grimar

    Differential Revision: https://reviews.llvm.org/D64361 — yuanfang / ViewSVN

rL:366145 - C:366146 - #63220 (Jul 15, 2019 3:51:07 PM)

  1. add -fthinlto-index= option to clang-cl

    This adds a -fthinlto-index= option to clang-cl, which allows it to
    be used to drive ThinLTO backend passes. This allows clang-cl to be
    used for distributed ThinLTO.

    Reviewers: tejohnson, pcc, rnk

    Subscribers: mehdi_amini, steven_wu, dexonsmith, arphaman, cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D64458 — inglorion / ViewSVN
  2. [WebAssembly] Rename except_ref type to exnref

    We agreed to rename `except_ref` to `exnref` for consistency with other
    reference types in
    https://github.com/WebAssembly/exception-handling/issues/79. This also
    renames WebAssemblyInstrExceptRef.td to WebAssemblyInstrRef.td in order
    to use the file for other reference types in future.

    Reviewers: dschuff

    Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, jfb, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64703 — aheejin / ViewSVN

rL:366140 - C:366146 - #63218 (Jul 15, 2019 3:29:40 PM)

  1. add -fthinlto-index= option to clang-cl

    This adds a -fthinlto-index= option to clang-cl, which allows it to
    be used to drive ThinLTO backend passes. This allows clang-cl to be
    used for distributed ThinLTO.

    Reviewers: tejohnson, pcc, rnk

    Subscribers: mehdi_amini, steven_wu, dexonsmith, arphaman, cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D64458 — inglorion / ViewSVN
  2. [OpenCL] Make TableGen'd builtin tables and helper functions static

    Reviewers: Pierre, Anastasia

    Reviewed By: Anastasia

    Subscribers: yaxunl, cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D64608 — tstellar / ViewSVN
  3. [clang-fuzzer] Remove 'setUseOrcMCJITReplacement(false)' call.

    The default value for this option (UseMCJITReplacement) is already false, and
    OrcMCJITReplacement is going to have deprecation warnings attached in LLVM 9.0.
    Removing this call removes a spurious warning. — lhames / ViewSVN
  4. [WebAssembly] Simplify regcopy.mir

    This deletes the ll templates from the functions because they don't need
    them (mir files need ll templates only when they have function calls or
    BB names that are not numbers).

    This also renames the filename to `reg-copy.mir`, because I'm planning
    to add some more `reg-*.mir` soon.

    Reviewers: tlively

    Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64704 — aheejin / ViewSVN
  5. [WebAssembly] Assembler: support special floats: infinity / nan

    These are emitted as identifiers by the InstPrinter, so we should
    parse them as such. These could potentially clash with symbols of
    the same name, but that is out of our (the WebAssembly backend) control.

    Reviewers: dschuff

    Subscribers: sbc100, jgravelle-google, aheejin, sunfish, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64770 — aardappel / ViewSVN
  6. [DirectoryWatcher][test] Relax test assumptions

    Workaround for FSEvents sometimes sending notifications for events that happened
    before DirectoryWatcher was created.

    This caused tests to be flaky on green dragon. — jkorous / ViewSVN
  7. [DirectoryWatcher][NFC][test] Add typedef for enum — jkorous / ViewSVN

rL:366135 - C:366127 - #63217 (Jul 15, 2019 3:10:39 PM)

  1. [AMDGPU] Enable merging m0 initializations.

    Enable hoisting and merging m0 defs that are initialized with the same
    immediate value. Fixes bug where removed instructions are not considered
    to interfere with other inits, and make sure to not hoist inits before block

    Reviewers: rampitec, arsenm

    Reviewed By: rampitec

    Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64766 — kerbowa / ViewSVN

rL:366133 - C:366127 - #63216 (Jul 15, 2019 2:57:22 PM)

  1. [mips] Print BEQZL and BNEZL pseudo instructions

    One of the reasons - to be compatible with GNU tools. — atanasyan / ViewSVN
  2. AMDGPU: Use standalone MUBUF load patterns

    We already do this for the flat and DS instructions, although it is
    certainly uglier and more verbose.

    This will allow using separate pattern definitions for extload and
    zextload. Currently we get away with using a single PatFrag with
    custom predicate code to check if the extension type is a zextload or
    anyextload. The generic mechanism the global isel emitter understands
    treats these as mutually exclusive. I was considering making the
    pattern emitter accept zextload or sextload extensions for anyextload
    patterns, but in global isel, the different extending loads have
    distinct opcodes, and there is currently no mechanism for an opcode
    matcher to try multiple (and there probably is very little need for
    one beyond this case). — arsenm / ViewSVN

rL:366130 - C:366127 - #63215 (Jul 15, 2019 2:25:18 PM)

  1. [LoopUnroll+LoopUnswitch] do not transform loops containing callbr

    There is currently a correctness issue when unrolling loops containing
    callbr's where their indirect targets are being updated correctly to the
    newly created labels, but their operands are not.  This manifests in
    unrolled loops where the second and subsequent copies of callbr
    instructions have blockaddresses of the label from the first instance of
    the unrolled loop, which would result in nonsensical runtime control

    For now, conservatively do not unroll the loop.  In the future, I think
    we can pursue unrolling such loops provided we transform the cloned
    callbr's operands correctly.

    Such a transform and its legalities are being discussed in:

    Link: https://bugs.llvm.org/show_bug.cgi?id=42489
    Link: https://groups.google.com/forum/#!topic/clang-built-linux/z-hRWP9KqPI

    Reviewers: fhahn, hfinkel, efriedma

    Reviewed By: fhahn, hfinkel, efriedma

    Subscribers: efriedma, hiraditya, zzheng, dmgreen, llvm-commits, pirama, kees, nathanchance, E5ten, craig.topper, chandlerc, glider, void, srhines

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64368 — nickdesaulniers / ViewSVN

rL:366129 - C:366127 - #63214 (Jul 15, 2019 2:16:51 PM)

  1. TableGen/GlobalISel: Fix handling of truncstore patterns

    This was failing to import the AMDGPU truncstore patterns. The
    truncating stores from 32-bit to 8/16 were then somehow being
    incorrectly selected to a 4-byte store.

    A separate check is emitted for the LLT size in comparison to the
    specific memory VT, which looks strange to me but makes sense based on
    the hierarchy of PatFrags used for the default truncstore PatFrags. — arsenm / ViewSVN

rL:366128 - C:366127 - #63213 (Jul 15, 2019 2:05:33 PM)

  1. TableGen: Add address space to matchers

    Currently AMDGPU uses a CodePatPred to check address spaces from the
    MachineMemOperand. Introduce a new first class property so that the
    existing patterns can be easily modified to uses the new generated
    predicate, which will also be handled for GlobalISel.

    I would prefer these to match against the pointer type of the
    instruction, but that would be difficult to get working with
    SelectionDAG compatbility. This is much easier for now and will avoid
    a painful tablegen rewrite for all the loads and stores.

    I'm also not sure if there's a better way to encode multiple address
    spaces in the table, rather than putting the number to expect. — arsenm / ViewSVN

rL:366125 - C:366127 - #63212 (Jul 15, 2019 1:55:40 PM)

  1. [clang] allow -fthinlto-index= without -x ir

    Previously, passing -fthinlto-index= to clang required that bitcode
    files be explicitly marked by -x ir. This change makes us detect files
    with object file extensions as bitcode files when -fthinlto-index= is
    present, so that explicitly marking them is no longer necessary.
    Explicitly specifying -x ir is still accepted and continues to be part
    of the test case to ensure we continue to support it.

    Reviewers: tejohnson, rnk, pcc

    Subscribers: mehdi_amini, steven_wu, dexonsmith, arphaman, cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D64610 — inglorion / ViewSVN

rL:366125 - C:366123 - #63211 (Jul 15, 2019 1:20:41 PM)

  1. AMDGPU/GlobalISel: Allow scalar s1 and/or/xor

    If a 1-bit value is in a 32-bit VGPR, the scalar opcodes set SCC to
    whether the result is 0. If the inputs are SCC, these can be copied to
    a 32-bit SGPR to produce an SCC result. — arsenm / ViewSVN

rL:366123 - C:366123 - #63210 (Jul 15, 2019 1:05:41 PM)

  1. ARM MTE stack sanitizer.

    Add "memtag" sanitizer that detects and mitigates stack memory issues
    using armv8.5 Memory Tagging Extension.

    It is similar in principle to HWASan, which is a software implementation
    of the same idea, but there are enough differencies to warrant a new
    sanitizer type IMHO. It is also expected to have very different
    performance properties.

    The new sanitizer does not have a runtime library (it may grow one
    later, along with a "debugging" mode). Similar to SafeStack and
    StackProtector, the instrumentation pass (in a follow up change) will be
    inserted in all cases, but will only affect functions marked with the
    new sanitize_memtag attribute.

    Reviewers: pcc, hctim, vitalybuka, ostannard

    Subscribers: srhines, mehdi_amini, javed.absar, kristof.beyls, hiraditya, cryptoad, steven_wu, dexonsmith, cfe-commits, llvm-commits

    Tags: #clang, #llvm

    Differential Revision: https://reviews.llvm.org/D64169 — eugenis / ViewSVN

rL:366121 - C:366091 - #63209 (Jul 15, 2019 12:50:43 PM)

  1. AMDGPU/GlobalISel: Select G_AND/G_OR/G_XOR — arsenm / ViewSVN
  2. AMDGPU/GlobalISel: Don't constrain source register of VCC copies

    This is a hack until I come up with a better way of dealing with the
    pseudo-register banks used for boolean values. If the use instruction
    constrains the register, the selector for the def instruction won't
    see that the bank was VCC. A 1-bit SReg_32 is could ambiguously have
    been SCCRegBank or VCCRegBank in wave32.

    This is necessary to successfully select branches with and and/or/xor
    condition. — arsenm / ViewSVN
  3. AMDGPU/GlobalISel: Fix selecting vcc->vcc bank copies

    The extra test change is correct, although how it arrives there is a
    bug that needs work. With wave32, the test for isVCC ambiguously
    reports true for an SCC or VCC source. A new allocatable pseudo
    register class for SCC may be necesssary. — arsenm / ViewSVN
  4. AMDGPU/GlobalISel: Fix not constraining result reg of copies to VCC — arsenm / ViewSVN

rL:366117 - C:366091 - #63208 (Jul 15, 2019 12:45:39 PM)

  1. AMDGPU/GlobalISel: Fix handling of sgpr (not scc bank) s1 to VCC

    This was emitting a copy from a 32-bit register to a 64-bit. — arsenm / ViewSVN
  2. AMDGPU/GlobalISel: Custom legalize G_INSERT_VECTOR_ELT — arsenm / ViewSVN
  3. AMDGPU/GlobalISel: Custom legalize G_EXTRACT_VECTOR_ELT

    Turn the constant cases into G_EXTRACTs. — arsenm / ViewSVN

rL:366114 - C:366091 - #63207 (Jul 15, 2019 12:40:41 PM)

  1. AMDGPU/GlobalISel: Fix G_ICMP for wave32 — arsenm / ViewSVN
  2. GlobalISel: Implement narrowScalar for vector extract/insert indexes — arsenm / ViewSVN

rL:366110 - C:366091 - #63206 (Jul 15, 2019 12:15:42 PM)

  1. AMDGPU: Fix missing immarg from interp intrinsics — arsenm / ViewSVN

rL:366109 - C:366091 - #63205 (Jul 15, 2019 12:05:40 PM)

  1. [FileCheck] Store line numbers as optional values

    Processing of command-line definition of variable and logic around
    implicit not directives both reuse parsing code that expects a line
    number to be defined. So far, a special line number of 0 was used for
    those users of the parsing code where a line number does not make sense.
    This commit instead represents line numbers as Optional values so that
    they can be None for those cases.

    Reviewers: jhenderson, chandlerc, jdenny, probinson, grimar, arichardson, rnk

    Subscribers: JonChesterfield, rogfer01, hfinkel, kristina, rnk, tra, arichardson, grimar, dblaikie, probinson, llvm-commits, hiraditya

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64639 — thopre / ViewSVN
  2. [cmake] Don't set install rules for tblgen if building utils is disabled

    This is a follow up to D64032. Afterwards if building utils is disabled
    and cross compilation is attempted, CMake will complain that adding
    `install()` directives to targets with EXCLUDE_FROM_ALL set is "undefined".
    Indeed, it appears depending on the CMake version and the selected
    Generator, the install rule will error because the underlying target isn't
    built. Fix that by not adding the install rule if building utils is not
    requested. Note that this doesn't prevent building tblgen as a
    dependency in not cross-build, even if building tools is disabled.

    Reviewed By: smeenai
    Differential Revision: https://reviews.llvm.org/D64225 — kfischer / ViewSVN

rL:366107 - C:366091 - #63204 (Jul 15, 2019 12:00:43 PM)

  1. Expand comment about how StringsToBuckets was computed, and add more entries

    The construction was explained in
    https://reviews.llvm.org/D44810?id=139526#inline-391999 but reading the code
    shouldn't require hunting down old reviews to understand it.

    The precomputed list was missing an entry for the empty list case, and
    one entry at the very end. (The current last entry is the last one where
    3 * BucketCount fits in a signed int, but the reference implementation
    uses unsigneds as far as I can tell, so there's room for one more entry.)

    No behavior change for inputs seen in practice.

    Differential Revision: https://reviews.llvm.org/D64738 — nico / ViewSVN

rL:366106 - C:366091 - #63203 (Jul 15, 2019 11:48:05 AM)

  1. [ARM] MVE vector for 64bit types

    We need to make sure that we are sensibly dealing with vectors of types v2i64
    and v2f64, even if most of the time we cannot generate native operations for
    them. This mostly adds a lot of testing, plus fixes up a couple of the issues
    found. And, or and xor can be legal for v2i64, and shifts combining needs a
    slight fixup.

    Differential Revision: https://reviews.llvm.org/D64316 — dmgreen / ViewSVN

rL:366104 - C:366091 - #63202 (Jul 15, 2019 11:43:00 AM)

  1. [WebAssembly] Assembler: recognize .init_array as data section.

    Reviewers: sbc100

    Subscribers: dschuff, jgravelle-google, aheejin, sunfish, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64602 — aardappel / ViewSVN

rL:366103 - C:366091 - #63201 (Jul 15, 2019 11:36:54 AM)

  1. AMDGPU/GlobalISel: Widen vector extracts — arsenm / ViewSVN

rL:366102 - C:366091 - #63200 (Jul 15, 2019 11:31:35 AM)

  1. AMDGPU/GlobalISel: Handle llvm.amdgcn.if.break — arsenm / ViewSVN
  2. AMDGPU: Remove reserved value accidentally left in for gfx908 — kzhuravl / ViewSVN
  3. AMDGPU/GlobalISel: Select llvm.amdgcn.end.cf — arsenm / ViewSVN
  4. [x86] try to keep FP casted+truncated+extracted vector element out of GPRs

    inttofp (trunc (extelt X, 0)) --> inttofp (extelt (bitcast X), 0)

    We have pseudo-vectorization of scalar int to FP casts, so this tries to
    make that more likely by replacing a truncate with a bitcast. I didn't see
    any test diffs starting from 'uitofp', so I left that as a TODO. We can't
    only match the shorter trunc+extract pattern because there's an opposing
    transform somewhere, so we infinite loop. Waiting to try this during
    lowering is another possibility.

    A motivating case is shown in PR39975 and included in the test diffs here:

    Differential Revision: https://reviews.llvm.org/D64710 — spatel / ViewSVN

rL:366097 - C:366091 - #63199 (Jul 15, 2019 11:15:40 AM)

  1. [llvm-lib] Add a dependency to intrinsics_gen to the LLVMLibDriver build

    Occasionally the build of LLVMLibDriver will fail because Attributes.inc has not been generated yet. Add an explicit dependency, so that we can guarantee that the file has been generated before LLVMLibDriver is build.

    ##[error]llvm\include\llvm\IR\Attributes.h(73,0): Error C1083: Cannot open include file: 'llvm/IR/Attributes.inc': No such file or directory
    llvm\include\llvm/IR/Attributes.h(73): fatal error C1083: Cannot open include file: 'llvm/IR/Attributes.inc': No such file or directory [LLVMLibDriver.vcxproj]

    Reviewers: asmith

    Subscribers: mgorny, hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D64357 — stella.stamenova / ViewSVN

rL:366096 - C:366091 - #63198 (Jul 15, 2019 11:00:43 AM)

  1. [X86] Return UNDEF from LowerScalarImmediateShift when the shift amount is out of range.

    I think we only turn out of range shiftss to undef when
    all elements are out of range or the shift amount is a splat out
    of range. I'm not sure which, I didn't check.

    During lowering we can split a shift where some elements
    are out of range into multiple shifts. This can create a
    new shift with a splat shift amount that is out of range.

    This patch returns undef for this case.

    Fixes PR42615.

    Differential Revision: https://reviews.llvm.org/D64699 — ctopper / ViewSVN

rL:366094 - C:366091 - #63197 (Jul 15, 2019 10:50:41 AM)

  1. AMDGPU: Add 24-bit mul intrinsics

    Insert these during codegenprepare.

    This works around a DAG issue where generic combines eliminate the and
    asserting the high bits are zero, which then exposes an unknown read
    source to the mul combine. It doesn't worth the hassle of trying to
    insert an AssertZext or something to try to deal with it. — arsenm / ViewSVN
  2. Add some release notes for 9.0 release — arsenm / ViewSVN
  3. [AMDGPU] Copy missing predicate from pseudo to real

    NFC at the momemnt, needed for future commit.

    Differential Revision: https://reviews.llvm.org/D64761 — rampitec / ViewSVN
  4. Update __VERSION__ to remove the hardcoded 4.2.1 version

    Just like in https://reviews.llvm.org/D56803
    for -dumpversion

    Reviewers: rnk

    Reviewed By: rnk

    Subscribers: dexonsmith, lebedev.ri, hubert.reinterpretcast, xbolva00, fedor.sergeev, cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D63048 — sylvestre / ViewSVN

rL:366090 - C:366088 - #63196 (Jul 15, 2019 10:39:42 AM)

  1. [FunctionAttrs] Remove readonly and writeonly assertion

    There are scenarios where mutually recursive functions may cause the SCC
    to contain both read only and write only functions. This removes an
    assertion when adding read attributes which caused a crash with a the
    provided test case, and instead just doesn't add the attributes.

    Patch by Luke Lau <luke.lau@intel.com>

    Differential Revision: https://reviews.llvm.org/D60761 — jdoerfert / ViewSVN
  2. [ARM] Minor formatting in ARMInstrMVE.td. NFC — dmgreen / ViewSVN
  3. Use a unique_ptr instead of manual memory management for LineTable — nico / ViewSVN
  4. AMDGPU/GlobalISel: Select easy cases for G_BUILD_VECTOR — arsenm / ViewSVN

rL:366086 - C:366085 - #63195 (Jul 15, 2019 10:25:40 AM)

  1. AMDGPU/GlobalISel: RegBankSelect for G_CONCAT_VECTORS — arsenm / ViewSVN

rL:366082 - C:366085 - #63194 (Jul 15, 2019 10:20:41 AM)

  1. Use a unique_ptr instead of manual memory management for CustomDiagInfo — nico / ViewSVN

rL:366082 - C:366084 - #63193 (Jul 15, 2019 10:15:43 AM)

  1. Use unique_ptr instead of manual delete in one place. No behavior change. — nico / ViewSVN

rL:366082 - C:366076 - #63192 (Jul 15, 2019 10:00:41 AM)

  1. [x86] add tests for reductions that might be better with more horizontal ops; NFC — spatel / ViewSVN

rL:366081 - C:366076 - #63191 (Jul 15, 2019 9:45:41 AM)

  1. Revert "r366069: [PatternMatch] Implement matching code for LibFunc"

    Reason: the change introduced a layering violation by adding a
    dependency on IR to Analysis. — ibiryukov / ViewSVN
  2. [docs][llvm-nm] Fix inconsistent grammar — jhenderson / ViewSVN