SuccessChanges

Summary

  1. [mlir][Linalg] Introduce linalg.pad_tensor op. (details)
  2. [mlir][StandardToSPIRV] Add support for lowering uitofp to SPIR-V (details)
  3. [AArch64][GlobalISel] Implement widenScalar for signed overflow (details)
  4. [TargetLowering] Simplify some code in SimplifySetCC that tries to handle SIGN_EXTEND_INREG operand types that should never happen. NFCI (details)
  5. [AMDGPU] Test clean up (NFC) (details)
  6. Update filename to workers.py file in documentation (details)
  7. NFC: Remove simple_ilist comment mentioning ilist/iplist allocating (details)
  8. [TargetLowering] Use getBoolConstant instead of assuming zero or one for boolean contents. (details)
  9. [clang][cli] Port visibility LangOptions to marshalling system (details)
  10. [RISCV] Fix intrinsic CodeGen test cases for vrgather (details)
Commit 16d4bbef30a9e625e04653047759d5636f9e58a5 by hanchung
[mlir][Linalg] Introduce linalg.pad_tensor op.

`linalg.pad_tensor` is an operation that pads the `source` tensor
with given `low` and `high` padding config.

Example 1:

```mlir
  %pad_value = ... : f32
  %1 = linalg.pad_tensor %0 low[1, 2] high[2, 3] {
  ^bb0(%arg0 : index, %arg1 : index):
    linalg.yield %pad_value : f32
  } : tensor<?x?xf32> to tensor<?x?xf32>
```

Example 2:
```mlir
  %pad_value = ... : f32
  %1 = linalg.pad_tensor %arg0 low[2, %arg1, 3, 3] high[3, 3, %arg1, 2] {
  ^bb0(%arg2: index, %arg3: index, %arg4: index, %arg5: index):
    linalg.yield %pad_value : f32
  } : tensor<1x2x2x?xf32> to tensor<6x?x?x?xf32>
```

Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D93704
The file was modifiedmlir/test/Dialect/Linalg/invalid.mlir
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
The file was modifiedmlir/test/Dialect/Linalg/roundtrip.mlir
Commit 2cb130f7661176f2c2eaa7554f2a55863cfc0ed3 by hanchung
[mlir][StandardToSPIRV] Add support for lowering uitofp to SPIR-V

- Extend spirv::ConstantOp::getZero/One to handle float, vector of int, and vector of float.
- Refactor ZeroExtendI1Pattern to use getZero/One methods.
- Add one more test for lowering std.zexti which extends vector<4xi1> to vector<4xi64>.

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D95120
The file was modifiedmlir/test/Conversion/StandardToSPIRV/std-ops-to-spirv.mlir
The file was modifiedmlir/lib/Conversion/StandardToSPIRV/StandardToSPIRV.cpp
The file was modifiedmlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp
Commit 541d98efa222b00e16c67348810898c2fa11f398 by Amara Emerson
[AArch64][GlobalISel] Implement widenScalar for signed overflow

Implement widening for G_SADDO and G_SSUBO. Previously it was only
implemented for G_UADDO and G_USUBO. Also add legalize-add/sub tests for
narrow overflowing add/sub on AArch64.

Differential Revision: https://reviews.llvm.org/D95034
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
Commit 5660dc5968ec6dacba1917b741d660c582f69e9e by craig.topper
[TargetLowering] Simplify some code in SimplifySetCC that tries to handle SIGN_EXTEND_INREG operand types that should never happen. NFCI

There was code to handle the first operand being different than
the result type. And code to handle first operand having the
same type as the type to extend from. This should never happen
for a correctly formed SIGN_EXTEND_INREG. I've replace the
code with asserts.

I also noticed we created the same APInt twice so I've reused it.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Commit c971bcd2102b905e6469463fb8309ab3f7b2b8f2 by Christudasan.Devadasan
[AMDGPU] Test clean up (NFC)
The file was modifiedllvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
Commit f20bb857addaf5479d9b1d4ac29e315a3971ff1c by douglas.yung
Update filename to workers.py file in documentation

Commit be9f322e8dc530a56f03356aad31fa9031b27e26 moved the list of workers from
slaves.py to workers.py, but the documentation in "How To Add A Builder" was
never updated and now references a non-existing file. This fixes that.

Reviewed By: gkistanova

Differential Revision: https://reviews.llvm.org/D94886
The file was modifiedllvm/docs/HowToAddABuilder.rst
Commit 75f10c957477b269d9b954a686231342aeb8004b by nathan
NFC: Remove simple_ilist comment mentioning ilist/iplist allocating

Allocation was removed from ilist in 2016 in the git commit
b5da00533510.

Reviewed By: dexonsmith

Differential Revision: https://reviews.llvm.org/D93953
The file was modifiedllvm/include/llvm/ADT/simple_ilist.h
Commit c953a8334707951d172e8061c8dc9054eb0c5c3f by craig.topper
[TargetLowering] Use getBoolConstant instead of assuming zero or one for boolean contents.

Noticed while I was touching other nearby code. I don't have a
test where this matters because the targets I work on
use zero or one boolean contents. And the tests cases I've seen
this fire on happen before type legalization where the result type
is MVT::i1 so the distinction doesn't matter.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Commit ff5f42e413386b1b3730879abf7b35756891e1c3 by jan_svoboda
[clang][cli] Port visibility LangOptions to marshalling system

This patch introduces Clang-specific MarshallingInfoVisibility TableGen class.

Reviewed By: dexonsmith

Differential Revision: https://reviews.llvm.org/D95147
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedclang/include/clang/Driver/Options.td
Commit 4edb63bbbe338b890119a307bc323c24d0a1afc7 by shihpo.hung
[RISCV] Fix intrinsic CodeGen test cases for vrgather

1. Op2 type in vrgather.vx should be XLEN instead of SEW
2. Add double type in vrgather-rv32 cases.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D95207
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll