Commit
dab859d1bf250c4d0299ac505e2a6773c56b6503
by daveReland: [clang driver] Move default module cache from system temporary directory
This fixes a unit test. Otherwise here is the original commit:
1) Shared writable directories like /tmp are a security problem.
2) Systems provide dedicated cache directories these days anyway.
3) This also refines LLVM's cache_directory() on Darwin platforms to use
the Darwin per-user cache directory.
Reviewers: compnerd, aprantl, jakehehrlich, espindola, respindola, ilya-biryukov, pcc, sammccall
Reviewed By: compnerd, sammccall
Subscribers: hiraditya, llvm-commits, cfe-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D82362
|
 | clang/include/clang/Driver/Driver.h |
| clang/unittests/Driver/ModuleCacheTest.cpp |
| clang/docs/ReleaseNotes.rst |
| clang/lib/Driver/ToolChains/Clang.cpp |
| llvm/lib/Support/Unix/Path.inc |
| clang/test/Driver/modules-cache-path.m |
| llvm/unittests/Support/Path.cpp |
Commit
b392fb33761e983a8edb5946734427779e25bbe2
by llvm-devFix unused type alias warning. NFC.
The "using InsertPointTy" line is an unnecessary copy + paste from other builder tests.
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| llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp |
Commit
5883f6f977a9b90913451e3e3dc13e14d7cddaac
by llvm-dev[X86] Add AVX tests buildvec-insertvec.ll
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| llvm/test/CodeGen/X86/buildvec-insertvec.ll |
Commit
878a24d369ea4d627fb48f7af5edc28fd079a0c0
by llvm-dev[X86] Add PR46461 test case
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| llvm/test/CodeGen/X86/buildvec-insertvec.ll |
Commit
6bdb3ce4529ffbaad0354b052f2e9f06b4431085
by llvm-dev[DAG] reduceBuildVecExtToExtBuildVec - don't combine if it would break a splat.
reduceBuildVecExtToExtBuildVec was breaking a splat(zext(x)) pattern into buildvector(x, 0, x, 0, ..) resulting in much more complex insert+shuffle codegen.
We already go to some lengths to avoid this in SimplifyDemandedVectorElts etc. when we encounter splat buildvectors.
It should be OK to fold all splat(aext(x)) patterns - we might need to tighten this if we find a case where we mustn't introduce a buildvector(x, undef, x, undef, ..) but I can't find one.
Fixes PR46461.
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| llvm/test/CodeGen/X86/buildvec-insertvec.ll |
| llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp |
| llvm/test/CodeGen/X86/broadcastm-lowering.ll |
Commit
892df9e706e43c48854be8bf544c41a146611607
by llvm-devFileCollector.h - reduce Twine.h include to forward declaration. NFC.
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| llvm/include/llvm/Support/FileCollector.h |
| llvm/lib/Support/FileCollector.cpp |
Commit
eb50838ba08d4149182828b96956a57ec6f5f658
by mydeveloperday[clang-format] [PR462254] fix indentation of default and break correctly in whitesmiths style
Summary:
https://bugs.llvm.org/show_bug.cgi?id=46254
Reviewed By: curdeius, jbcoe
Differential Revision: https://reviews.llvm.org/D8201
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| clang/unittests/Format/FormatTest.cpp |
| clang/lib/Format/UnwrappedLineFormatter.cpp |
| clang/lib/Format/UnwrappedLineParser.cpp |
Commit
8b9e9753ea6875fb954a5bcdfed132dd75d63d29
by llvm-devThreadPool.h - remove unused BitVector.h include. NFC.
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| llvm/include/llvm/Support/ThreadPool.h |
Commit
43e3c39327f9c32bea73b2629b718e9f5fd678d1
by 1585086582Revert "[Docs] Fix typo and test git commit access. NFC."
This reverts commit c19e82c6b38b74c56d595cb69582b7c3727762b5.
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| clang-tools-extra/docs/clang-tidy/checks/readability-make-member-function-const.rst |
Commit
a43b99a1e38e2beffb68a6db93f216f511e7fd41
by mydeveloperday[clang-format] NFC 1% improvement in the overall clang-formatted status
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| clang/docs/ClangFormattedStatus.rst |
Commit
d56c6475a60aa44b040983fe4fd355399cc4c42d
by llvm-dev[X86][AVX] SimplifyDemandedVectorEltsForTargetNode - reduce width of X86ISD::VPERMILPV
If we don't need the elements of the upper lanes, reduce the width of the X86ISD::VPERMILPV node.
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| llvm/lib/Target/X86/X86ISelLowering.cpp |
| llvm/test/CodeGen/X86/var-permute-256.ll |
Commit
e855efe42407dd67f6a513927d0669cb7a66f448
by llvm-dev[X86][AVX] SimplifyDemandedVectorEltsForTargetNode - reduce width of X86ISD::VPERMIL2
If we don't need the elements of the upper lanes, reduce the width of the X86ISD::VPERMIL2 node.
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| llvm/test/CodeGen/X86/var-permute-256.ll |
| llvm/lib/Target/X86/X86ISelLowering.cpp |
Commit
74dc081ef2d830a7fbff68b230176f874f741897
by llvm-devUpdate polly tests to use -disable-basicaa to -disable-basic-aa
These were missed in rG4cd19a6e15120cb
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| polly/test/Isl/Ast/alias_simple_2.ll |
| polly/test/Isl/Ast/alias_simple_1.ll |
| polly/test/Isl/Ast/alias_simple_3.ll |
| polly/test/ScopDetect/base_pointer_setNewAccessRelation.ll |
| polly/test/ScopInfo/Alias-4.ll |
| polly/test/Isl/CodeGen/multidim-non-matching-typesize-2.ll |
| polly/test/Isl/CodeGen/multidim-non-matching-typesize.ll |
| polly/test/ScopDetect/base_pointer.ll |
Commit
f0634100cdc832605bff355330d2ccdb7f43842f
by lebedev.ri[Analysis] isDereferenceableAndAlignedPointer(): don't crash on `bitcast <1 x ???*> to ???*`
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 | llvm/test/Transforms/SimplifyCFG/1elt-ptr-vec-alignment-crash.ll |
| llvm/lib/Analysis/Loads.cpp |
Commit
66da87dcbaf91fa3393ce80c687e9c2d133ee3ca
by kai.wang[RISCV] Assemble/Disassemble v-ext instructions.
Assemble/disassemble RISC-V V extension instructions according to
latest version spec in https://github.com/riscv/riscv-v-spec/.
I have tested this patch using GNU toolchain. The encoding is aligned
to GNU assembler output. In this patch, there is a test case for each
instruction at least.
The V register definition is just for assemble/disassemble. Its type
is not important in this stage. I think it will be reviewed and modified
as we want to do codegen for scalable vector types.
This patch does not include Zvamo, Zvlsseg, and Zvediv.
Differential revision: https://reviews.llvm.org/D69987
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| llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h |
| llvm/test/MC/RISCV/rvv/fdiv.s |
| llvm/test/MC/RISCV/rvv/fsub.s |
| llvm/test/MC/RISCV/rvv/mv.s |
| llvm/test/MC/RISCV/rvv/freduction.s |
| llvm/test/MC/RISCV/rvv/vsetvl.s |
| llvm/test/MC/RISCV/rvv/fadd.s |
| llvm/test/MC/RISCV/rvv/sub.s |
| llvm/test/MC/RISCV/rvv/load.s |
| llvm/test/MC/RISCV/rvv/mul.s |
| llvm/lib/Target/RISCV/RISCVSystemOperands.td |
| llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h |
| llvm/test/MC/RISCV/rvv/reduction.s |
| llvm/test/MC/RISCV/rvv/snippet.s |
| llvm/lib/Target/RISCV/RISCVInstrInfo.h |
| llvm/test/MC/RISCV/rvv/or.s |
| llvm/lib/Target/RISCV/RISCVInstrInfoV.td |
| llvm/test/MC/RISCV/rvv/others.s |
| llvm/test/MC/RISCV/rvv/add.s |
| llvm/test/MC/RISCV/rvv/convert.s |
| llvm/lib/Target/RISCV/RISCVRegisterInfo.td |
| llvm/test/MC/RISCV/rvv/div.s |
| llvm/test/MC/RISCV/rvv/fmul.s |
| llvm/test/MC/RISCV/rvv/compare.s |
| llvm/lib/Target/RISCV/RISCVInstrFormats.td |
| llvm/test/MC/RISCV/rvv/fothers.s |
| llvm/lib/Target/RISCV/RISCVSchedRocket64.td |
| llvm/test/MC/RISCV/rvv/minmax.s |
| llvm/test/MC/RISCV/rvv/fmacc.s |
| llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp |
| llvm/test/MC/RISCV/rvv/and.s |
| llvm/test/MC/RISCV/rvv/fminmax.s |
| llvm/test/MC/RISCV/rvv/fmv.s |
| llvm/test/MC/RISCV/rvv/mask.s |
| llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp |
| llvm/test/MC/RISCV/rvv/macc.s |
| llvm/test/MC/RISCV/rvv/store.s |
| llvm/test/MC/RISCV/rvv/fcompare.s |
| llvm/lib/Target/RISCV/RISCVInstrInfo.td |
| llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp |
| llvm/lib/Target/RISCV/RISCV.td |
| llvm/lib/Target/RISCV/RISCVInstrFormatsV.td |
| llvm/test/MC/RISCV/rvv/sign-injection.s |
| llvm/lib/Target/RISCV/RISCVSchedRocket32.td |
| llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp |
| llvm/test/MC/RISCV/rvv/clip.s |
| llvm/test/MC/RISCV/rvv/invalid.s |
| llvm/lib/Target/RISCV/RISCVSubtarget.h |
| llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp |
| llvm/test/MC/RISCV/rvv/shift.s |
| llvm/test/MC/RISCV/rvv/xor.s |
Commit
d698ff92a59c0632aa6a88b72890eb401bd64faa
by kai.wang[RISCV] Support experimental v extensions.
This follows the design as discussed on the mailing lists in the
following RFC:
http://lists.llvm.org/pipermail/llvm-dev/2020-January/138364.html
Support for the vector 'v' extension v0.8.
Differential revision: https://reviews.llvm.org/D81188
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| clang/test/Driver/riscv-arch.c |
| clang/lib/Driver/ToolChains/Arch/RISCV.cpp |
Commit
393b4bd1362f6634a972157e7c2f3936f51f7356
by llvm-dev[X86] SimplifyDemandedVectorEltsForTargetNode - merge shuffle/pack lower demanded elements handling.
Generalize the vector operand extraction code for shuffle/pack ops - we can assume that the vector operands are the same width as the result, and any non-vector values can be reused directly in the smaller width op.
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| llvm/lib/Target/X86/X86ISelLowering.cpp |
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