SuccessChanges

Summary

  1. [SystemZ][z/OS] Adding initial toolchain for z/OS (details)
  2. [SystemZ][z/OS] Fix build break in z/OS toolchain (details)
  3. AMDGPU: Convert test to MIR (details)
  4. AMDGPU: Check some offsets in test (details)
  5. PowerPC: Switch test to generated checks (details)
  6. GlobalISel: Artifact combine unmerge of unmerge (details)
  7. Revert "Reapply D70800: Fix AArch64 AAPCS frame record chain" (details)
  8. GlobalISel: Implement computeKnownBits for G_UNMERGE_VALUES (details)
  9. GlobalISel: Implement computeNumSignBits for G_SEXTLOAD/G_ZEXTLOAD (details)
  10. GlobalISel: Add combines for extend operations (details)
  11. [flang] Improve compile-time shape conformance checking (details)
  12. [PowerPC] Implement instruction definitions/MC Tests for xvcvspbf16 and xvcvbf16spn (details)
  13. [DAGCombiner] Fold an AND of a masked load into a zext_masked_load (details)
  14. [libc++] Improve REQUIRES for _ExtInt test on recent Clangs (details)
  15. [builtins] Unify the softfloat division implementation (details)
  16. [PowerPC] Handle STRICT_FSETCC(S) in more cases (details)
  17. GlobalISel: Implement computeKnownBits for G_BSWAP and G_BITREVERSE (details)
  18. GlobalISel: Port smarter known bits for umin/umax from DAG (details)
  19. GlobalISel: Implement computeNumSignBits for G_SELECT (details)
  20. [tsan] Fix "failed to intercept sysctlnametomib" on FreeBSD (details)
  21. x87 FPU state instructions do not use an f32 memory location (details)
  22. [GlobalISel] Fold xor(cmp(pred, _, _), 1) -> cmp(inverse(pred), _, _) (details)
  23. [flang] Fix integer CASE constant typing (details)
  24. [flang] Version information in flang/f18 (details)
  25. [AArch64][GlobalISel] Optimize away a Not feeding a brcond by using tbz instead of tbnz. (details)
  26. [Bitstream] Use alignTo to make code more readable. NFC (details)
  27. [PowerPC][AIX] Update save/restore offset for frame and base pointers. (details)
  28. [libfuzzer] Reduce default verbosity when printing large mutation sequences (details)
  29. [gn build] port 5ffd940ac02 a bit more (details)
  30. [gn build] Port 3d90a61cf2e (details)
  31. [gn build] Port 3e1e5f54492 (details)
  32. First commit on the release/11.x branch. (details)
  33. [fuzzer] Create user provided fuzzer writeable directories when requested if they dont exist (details)
  34. [builtins] Make __div[sdt]f3 handle denormal results (details)
  35. [MemorySSA] Update phi map with replacement value. (details)
  36. Revert "[fuzzer] Create user provided fuzzer writeable directories when requested if they dont exist" (details)
  37. [libc++] Workaround timespec_get not always being available in Apple SDKs (details)
  38. [OpenMP] Consolidate error handling and debug messages in Libomptarget (details)
  39. Revert "Revert "Reapply D70800: Fix AArch64 AAPCS frame record chain"" (details)
  40. [ORC] Add unit test for HasMaterializationSideEffectsOnly failure behavior. (details)
  41. Do not emit "-tune-cpu generic" for PS4 platform (details)
  42. [Bindings] Add LLVMAddInstructionSimplifyPass (details)
  43. [MachineCopyPropagation] In isNopCopy, check the destination registers match in addition to the source registers. (details)
  44. [LV] Interleave to expose ILP for small loops with scalar reductions. (details)
  45. Revert "[libfuzzer] Reduce default verbosity when printing large mutation sequences" (details)
  46. [Loads] Add canReplacePointersIfEqual helper. (details)
  47. [NFC] Fix unused var in release build (details)
  48. [amdgpu] Run SROA after loop unrolling. (details)
  49. Revert "[GlobalISel] Fold xor(cmp(pred, _, _), 1) -> cmp(inverse(pred), _, _)" (and dependent patch "Optimize away a Not feeding a brcond by using tbz instead of tbnz.") (details)
Commit 3e1e5f54492d5bdebd40388247254e310cf62c3d by Abhina.Sreeskantharajan
[SystemZ][z/OS] Adding initial toolchain for z/OS

This patch adds the initial toolchain for z/OS that will set some defaults. In subsequent patches, we plan to add support to use the system linker and assembler.

Reviewed By: hubert.reinterpretcast

Differential Revision: https://reviews.llvm.org/D86707
The file was modifiedclang/lib/Driver/Driver.cpp
The file was addedclang/lib/Driver/ToolChains/ZOS.h
The file was addedclang/lib/Driver/ToolChains/ZOS.cpp
The file was modifiedclang/lib/Driver/CMakeLists.txt
Commit c831a14aa16a74fa94c94a351a4bc7812a8bd166 by Abhina.Sreeskantharajan
[SystemZ][z/OS] Fix build break in z/OS toolchain

Differential Revision: https://reviews.llvm.org/D86707
The file was modifiedclang/lib/Driver/ToolChains/ZOS.cpp
Commit 4a9a4885aef9529788cc32999f998254a3730179 by Matthew.Arsenault
AMDGPU: Convert test to MIR

Currently the dbg_value ends up in the relaxed branch block. A future
commit will push the dbg_value out of this block, and I'm not sure how
to coax the IR into producing the same MIR at the relevant point.
The file was addedllvm/test/CodeGen/AMDGPU/branch-relaxation-debug-info.mir
The file was removedllvm/test/CodeGen/AMDGPU/branch-relaxation-debug-info.ll
Commit 7f5b4eaae4892539f2c4c1e32c61b297363c7341 by Matthew.Arsenault
AMDGPU: Check some offsets in test

This will make updating the checks easier in a future change.
The file was modifiedllvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
Commit 0f42d185346a5c383cf4d30e02c68b39440ed9dd by Matthew.Arsenault
PowerPC: Switch test to generated checks
The file was modifiedllvm/test/CodeGen/PowerPC/vsx-args.ll
The file was modifiedllvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll
Commit 18bbd9f15eb031c5c7e58ebe0692f87fa8d5954f by Matthew.Arsenault
GlobalISel: Artifact combine unmerge of unmerge

Unmerges have the same fundamental problem as G_TRUNC, and G_TRUNC
could be implemented in terms of G_UNMERGE_VALUES. Reducing the number
of elements in unmerge results ends up producing the original unmerge
type profile, so the artifact combiner needs to eliminate the
intermediate illegal registers. This avoids infinite looping in the
legalizer in a future change.

Assuming an unmerge has each result unmerged the same way, this ends
up producing a new unmerge of the source for every definition. I'm not
sure if the artifact combiner should either insert temporary merges
here and erase the original merge, or if the combiner should look at
uses from defs rather than defs from uses for unmerges.

In a few cases this regresses from using 16-bit shifts for 8-bit
values to using 32-bit shifts, but I think these can be legalized
later (the other legalization rules don't try very hard to use 16-bit
shifts either).
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir
The file was modifiedllvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpext.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-concat-vectors.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsqrt.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir
Commit bc9a29b9ee6ade4894252b1470977142c32b4602 by paul.walker
Revert "Reapply D70800: Fix AArch64 AAPCS frame record chain"

This reverts commit e9d9a612084b47fc4277523561d61e675370c854.

This patch was previously revert by 04879086b44348cad600a0a1ccbe1f7776cc3cf9
with the reapplication being done after breaking the assert used to
ensure SP is always 16-byte aligned, which is a requirement of the AAPCS.

For extra context the latest patch caused runtime failures when
building with "-march=armv8-a+sve -mllvm -aarch64-sve-vector-bits-min=256".
The file was modifiedllvm/lib/Target/AArch64/AArch64FrameLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.cpp
The file was removedllvm/test/CodeGen/AArch64/framelayout-unaligned-fp.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
The file was removedllvm/test/CodeGen/AArch64/framelayout-fp-csr.ll
The file was removedllvm/test/CodeGen/AArch64/framelayout-frame-record.mir
Commit 92090e8bd80179ec780bb67e1e7d95eceefbdd56 by Matthew.Arsenault
GlobalISel: Implement computeKnownBits for G_UNMERGE_VALUES
The file was modifiedllvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
The file was modifiedllvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
The file was modifiedllvm/include/llvm/Support/KnownBits.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
Commit 9e7e1b2d4b13d0abb1e34feedfc004ae2b2dab3a by Matthew.Arsenault
GlobalISel: Implement computeNumSignBits for G_SEXTLOAD/G_ZEXTLOAD
The file was modifiedllvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/combine-sext-inreg.mir
Commit 061182b7baf879badc9ff82c88d383d2d9ce279b by vkeles
GlobalISel: Add combines for extend operations

https://reviews.llvm.org/D86516
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/combine-ext.mir
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
The file was modifiedllvm/include/llvm/Target/GlobalISel/Combine.td
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-s1.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-from-extend-narrow.prelegal.mir
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/combine-amdgpu-cvt-f32-ubyte.mir
Commit 1a633e72f65df1ca75c0b8f3ab916d025adc36c1 by pklausler
[flang] Improve compile-time shape conformance checking

Conformance checking of the shapes of the operands of
array expressions can't, of course, always be done at
compilation time; but when the shapes are known and
nonconformable, we should catch the errors that we can.

Differential Revision: https://reviews.llvm.org/D86887
The file was modifiedflang/test/Semantics/select-rank.f90
The file was modifiedflang/lib/Semantics/expression.cpp
Commit ca2227c1b3f52611de7d051ffea91b0c6c21e1ac by amy.kwan1
[PowerPC] Implement instruction definitions/MC Tests for xvcvspbf16 and xvcvbf16spn

This patch adds the td instruction definitions of the xvcvspbf16 and xvcvbf16spn
instructions, along with their respective MC tests.

Differential Revision: https://reviews.llvm.org/D86794
The file was modifiedllvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrPrefix.td
The file was modifiedllvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
Commit 15e880a04fcfda8eb18e9cd6cab4fb8c0d2588e9 by samuel.tebbs
[DAGCombiner] Fold an AND of a masked load into a zext_masked_load

This patch folds an AND of a masked load and build vector into a zero
extended masked load.

Differential Revision: https://reviews.llvm.org/D86789
The file was addedllvm/test/CodeGen/Thumb2/mve-zext-masked-load.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit 8df143c2cc0a3b49440cafe8a80b0f72cee6f166 by Louis Dionne
[libc++] Improve REQUIRES for _ExtInt test on recent Clangs

The previous REQUIRES: would cause the test to run only on Clang-11, not
even on following versions of Clang, which was mostly not the intent.
The file was modifiedlibcxx/test/libcxx/atomics/ext-int.verify.cpp
Commit 0e90d8d4fed8c8cac70700acfdef6fc2ca2d482d by atrosinenko
[builtins] Unify the softfloat division implementation

This patch replaces three different pre-existing implementations of
__div[sdt]f3 LibCalls with a generic one - like it is already done for
many other LibCalls.

Reviewed By: sepavloff

Differential Revision: https://reviews.llvm.org/D85031
The file was modifiedcompiler-rt/lib/builtins/int_util.h
The file was modifiedcompiler-rt/lib/builtins/divsf3.c
The file was modifiedcompiler-rt/lib/builtins/fp_lib.h
The file was modifiedcompiler-rt/test/builtins/Unit/divdf3_test.c
The file was addedcompiler-rt/lib/builtins/fp_div_impl.inc
The file was modifiedcompiler-rt/lib/builtins/divdf3.c
The file was modifiedcompiler-rt/lib/builtins/divtf3.c
Commit 29ae4485950ed76faa94dabbd13bbe91d2b5c750 by qiucofan
[PowerPC] Handle STRICT_FSETCC(S) in more cases

On -O0, i1 strict_fsetcc will be promoted to i32. We don't handle that
in TD patterns. This patch fills logic in PPCISelDAGToDAG to handle more
cases.

Reviewed By: uweigand

Differential Revision: https://reviews.llvm.org/D86595
The file was modifiedllvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
The file was addedllvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
Commit 759482ddaa5eead883ed59a26af2f1dc66a6d4d1 by Matthew.Arsenault
GlobalISel: Implement computeKnownBits for G_BSWAP and G_BITREVERSE
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modifiedllvm/include/llvm/Support/KnownBits.h
The file was modifiedllvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
Commit 35c94d3f7e577d22ade48eaf73e6d1451c27f8b2 by Matthew.Arsenault
GlobalISel: Port smarter known bits for umin/umax from DAG
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-and.mir
The file was modifiedllvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
Commit 32a8a10b429809bcd14ff7f409988afbe962f0d4 by Matthew.Arsenault
GlobalISel: Implement computeNumSignBits for G_SELECT
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/GISelKnownBits.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/combine-sext-inreg.mir
The file was modifiedllvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
Commit 7be86829216698b6f4d0e083d48d7095898fc9c8 by Alexander.Richardson
[tsan] Fix "failed to intercept sysctlnametomib" on FreeBSD

The sysctlnametomib function is called from __tsan::Initialize via
__sanitizer::internal_sysctlbyname (see stack trace below). This results
in a fatal error since sysctlnametomib has not been intercepted yet.
This patch allows internal_sysctlbyname to be called before
__tsan::Initialize() has completed. On FreeBSD >= 1300045 sysctlbyname()
is a real syscall, but for older versions it calls sysctlnametomib()
followed by sysctl(). To avoid calling the intercepted version, look up
the real sysctlnametomib() followed by internal_sysctl() if the
syscall is not available.

This reduces check-sanitizer failures from 62 to 11 for me.

==34433==FATAL: ThreadSanitizer: failed to intercept sysctlnametomib
    at /exports/users/alr48/sources/upstream-llvm-project/compiler-rt/lib/sanitizer_common/sanitizer_termination.cpp:51
    name=0x7fffffffce10, namelenp=0x7fffffffce08)
    at /exports/users/alr48/sources/upstream-llvm-project/compiler-rt/lib/tsan/../sanitizer_common/sanitizer_common_interceptors.inc:7908
    oldp=0x7fffffffcf2c, oldlenp=0x7fffffffcf20, newp=0x0, newlen=0)
    at /exports/users/alr48/sources/upstream-llvm-project/compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp:803
    at /exports/users/alr48/sources/upstream-llvm-project/compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp:2152
    at /exports/users/alr48/sources/upstream-llvm-project/compiler-rt/lib/tsan/rtl/tsan_rtl.cpp:367
    fname=0x21c731 "readlink", pc=34366042556)
    at /exports/users/alr48/sources/upstream-llvm-project/compiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp:255
    bufsiz=1024)
    at /exports/users/alr48/sources/upstream-llvm-project/compiler-rt/lib/tsan/../sanitizer_common/sanitizer_common_interceptors.inc:7151

Reviewed By: #sanitizers, vitalybuka

Differential Revision: https://reviews.llvm.org/D85292
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
Commit a57fdcdd404bd9fa69463c587ee7915dde8541a2 by epastor
x87 FPU state instructions do not use an f32 memory location

These instructions actually use a 512-byte location, where bytes 464-511 are ignored.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D86942
The file was modifiedllvm/lib/Target/X86/X86InstrFPStack.td
Commit 8ad8f484b63ca507417b58c9016d2761f2b1a1a8 by Amara Emerson
[GlobalISel] Fold xor(cmp(pred, _, _), 1) -> cmp(inverse(pred), _, _)

This is needed for an upcoming change to how we translate conditional branches
which might generate these.

Differential Revision: https://reviews.llvm.org/D86383
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-invert-cmp.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/Utils.h
The file was modifiedllvm/include/llvm/Target/GlobalISel/Combine.td
The file was modifiedllvm/lib/CodeGen/GlobalISel/Utils.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
Commit 11ddb84b69e928aa396b28ce6b5baf8bbbdd6c43 by pklausler
[flang] Fix integer CASE constant typing

Don't use just 128-bit integer as the type for integer
CASE statement constants.  Use the actual type of the
literal constants that appeared.

Differential Review: https://reviews.llvm.org/D86875
The file was modifiedflang/test/Semantics/case01.f90
The file was modifiedflang/lib/Semantics/check-case.cpp
Commit b11c52781635bd871abd6d932cfd5dcd6f311903 by richard.barton
[flang] Version information in flang/f18

Fixed some version information in flang/f18:

  - fixed the behavior of the -v switch: this flag enables verbosity with used with arguments, but just displays the version when used alone (related to this bug: https://bugs.llvm.org/show_bug.cgi?id=46017)
- added __FLANG, __FLANG_MAJOR__, __FLANG_MINOR__ and __FLANG_PATCHLEVEL__ (similar to their __F18* counterparts) for compatibility purpose

Reviewed By: AlexisPerry, richard.barton.arm, tskeith

Differential Revision: https://reviews.llvm.org/D84334
The file was addedflang/test/Preprocessing/compiler_defined_macros.F90
The file was modifiedflang/test/Driver/version_test.f90
The file was modifiedflang/tools/f18/CMakeLists.txt
The file was modifiedflang/tools/f18/f18.cpp
The file was addedflang/tools/f18/f18_version.h.in
Commit 5ded4442520d3dbb1aa72e6fe03cddef8828c618 by Amara Emerson
[AArch64][GlobalISel] Optimize away a Not feeding a brcond by using tbz instead of tbnz.

Usually brconds are fed by compares, but not always, in which case we would
miss this fold.

Differential Revision: https://reviews.llvm.org/D86413
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/select-brcond-of-not.mir
Commit 96ae43bad5b86aad90a9820d2e3c1a51f0af8a75 by craig.topper
[Bitstream] Use alignTo to make code more readable. NFC

I was recently debugging a similar issue to https://reviews.llvm.org/D86500 only with a large metadata section. Only after I finished debugging it did I discover it was fixed very recently.

My version of the fix was going to alignTo since that uses uint64_t and improves the readability of the code. So I though I would go ahead and share it.

Differential Revision: https://reviews.llvm.org/D86957
The file was modifiedllvm/lib/Bitstream/Reader/BitstreamReader.cpp
Commit fecc27db11105478c999d9ae71ea281b14be6b6a by sd.fertile
[PowerPC][AIX] Update save/restore offset for frame and base pointers.

General purpose registers 30 and 31 are handled differently when they are
reserved as the base-pointer and frame-pointer respectively. This fixes the
offset of their fixed-stack objects when there are fpr calle-saved registers.

Differential Revision: https://reviews.llvm.org/D85850
The file was modifiedllvm/test/CodeGen/PowerPC/aix-base-pointer.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCFrameLowering.cpp
The file was addedllvm/test/CodeGen/PowerPC/aix-framepointer-save-restore.ll
Commit 2665425908e00618074e42155ec922a37f7c9002 by mascasa
[libfuzzer] Reduce default verbosity when printing large mutation sequences

When using a custom mutator (e.g. thrift mutator, similar to LPM)
that calls back into libfuzzer's mutations via `LLVMFuzzerMutate`, the mutation
sequences needed to achieve new coverage can get prohibitively large.

Printing these large sequences has two downsides:

1) It makes the logs hard to understand for a human.
2) The performance cost slows down fuzzing.

In this patch I change the `PrintMutationSequence` function to take a max
number of entries, to achieve this goal. I also update `PrintStatusForNewUnit`
to default to printing only 10 entries, in the default verbosity level (1),
requiring the user to set verbosity to 2 if they want the full mutation
sequence.

For our use case, turning off verbosity is not an option, as that would also
disable `PrintStats()` which is very useful for infrastructure that analyzes
the logs in realtime. I imagine most users of libfuzzer always want those logs
in the default.

I built a fuzzer locally with this patch applied to libfuzzer.

When running with the default verbosity, I see logs like this:

    #65 NEW    cov: 4799 ft: 10443 corp: 41/1447Kb lim: 64000 exec/s: 1 rss: 575Mb L: 28658/62542 MS: 196 Custom-CrossOver-ChangeBit-EraseBytes-ChangeBit-ChangeBit-ChangeBit-CrossOver-ChangeBit-CrossOver- DE: "\xff\xff\xff\x0e"-"\xfe\xff\xff\x7f"-"\xfe\xff\xff\x7f"-"\x17\x00\x00\x00\x00\x00\x00\x00"-"\x00\x00\x00\xf9"-"\xff\xff\xff\xff"-"\xfa\xff\xff\xff"-"\xf7\xff\xff\xff"-"@\xff\xff\xff\xff\xff\xff\xff"-"E\x00"-
    #67 NEW    cov: 4810 ft: 10462 corp: 42/1486Kb lim: 64000 exec/s: 1 rss: 577Mb L: 39823/62542 MS: 135 Custom-CopyPart-ShuffleBytes-ShuffleBytes-ChangeBit-ChangeBinInt-EraseBytes-ChangeBit-ChangeBinInt-ChangeBit- DE: "\x01\x00\x00\x00\x00\x00\x01\xf1"-"\x00\x00\x00\x07"-"\x00\x0d"-"\xfd\xff\xff\xff"-"\xfe\xff\xff\xf4"-"\xe3\xff\xff\xff"-"\xff\xff\xff\xf1"-"\xea\xff\xff\xff"-"\x00\x00\x00\xfd"-"\x01\x00\x00\x05"-

Staring hard at the logs it's clear that the cap of 10 is applied.

When running with verbosity level 2, the logs look like the below:

    #66    NEW    cov: 4700 ft: 10188 corp: 37/1186Kb lim: 64000 exec/s: 2 rss: 509Mb L: 47616/61231 MS: 520 Custom-CopyPart-ChangeBinInt-ChangeBit-ChangeByte-EraseBytes-PersAutoDict-CopyPart-ShuffleBytes-ChangeBit-ShuffleBytes-CopyPart-EraseBytes-CopyPart-ChangeBinInt-CopyPart-ChangeByte-ShuffleBytes-ChangeBinInt-ShuffleBytes-ChangeBit-CMP-ShuffleBytes-ChangeBit-CrossOver-ChangeBinInt-ChangeByte-ShuffleBytes-CrossOver-EraseBytes-ChangeBinInt-InsertRepeatedBytes-PersAutoDict-InsertRepeatedBytes-InsertRepeatedBytes-CrossOver-ChangeByte-ShuffleBytes-CopyPart-ShuffleBytes-CopyPart-CrossOver-ChangeBit-ShuffleBytes-CrossOver-PersAutoDict-ChangeByte-ChangeBit-ShuffleBytes-CrossOver-ChangeByte-EraseBytes-CopyPart-ChangeBinInt-PersAutoDict-CrossOver-ShuffleBytes-CrossOver-CrossOver-EraseBytes-CrossOver-EraseBytes-CrossOver-ChangeBit-ChangeBinInt-ChangeByte-EraseBytes-ShuffleBytes-ShuffleBytes-ChangeBit-EraseBytes-ChangeBinInt-ChangeBit-ChangeBinInt-CopyPart-EraseBytes-PersAutoDict-EraseBytes-CopyPart-ChangeBinInt-ChangeByte-CrossOver-ChangeBinInt-ShuffleBytes-PersAutoDict-PersAutoDict-ChangeBinInt-CopyPart-ChangeBinInt-CrossOver-ChangeBit-ChangeBinInt-CopyPart-ChangeByte-ChangeBit-CopyPart-CrossOver-ChangeByte-ChangeBit-ChangeByte-ShuffleBytes-CMP-ChangeBit-CopyPart-ChangeBit-ChangeByte-ChangeBinInt-PersAutoDict-ChangeBinInt-CrossOver-ChangeBinInt-ChangeBit-ChangeBinInt-ChangeBinInt-PersAutoDict-ChangeBinInt-ChangeBinInt-ChangeByte-CopyPart-ShuffleBytes-ChangeByte-ChangeBit-ChangeByte-ChangeByte-EraseBytes-CrossOver-ChangeByte-ChangeByte-EraseBytes-EraseBytes-InsertRepeatedBytes-ShuffleBytes-CopyPart-CopyPart-ChangeBit-ShuffleBytes-PersAutoDict-ShuffleBytes-ChangeBit-ChangeByte-ChangeBit-ShuffleBytes-ChangeByte-ChangeBinInt-CrossOver-ChangeBinInt-ChangeBit-EraseBytes-CopyPart-ChangeByte-CrossOver-EraseBytes-CrossOver-ChangeByte-ShuffleBytes-ChangeByte-ChangeBinInt-CrossOver-ChangeByte-InsertRepeatedBytes-InsertByte-ShuffleBytes-PersAutoDict-ChangeBit-ChangeByte-ChangeBit-ShuffleBytes-ShuffleBytes-CopyPart-ShuffleBytes-EraseBytes-ShuffleBytes-ShuffleBytes-CrossOver-ChangeBinInt-CopyPart-CopyPart-CopyPart-EraseBytes-EraseBytes-ChangeByte-ChangeBinInt-ShuffleBytes-CMP-InsertByte-EraseBytes-ShuffleBytes-CopyPart-ChangeBit-CrossOver-CopyPart-CopyPart-ShuffleBytes-ChangeByte-ChangeByte-ChangeBinInt-EraseBytes-ChangeByte-ChangeBinInt-ChangeBit-ChangeBit-ChangeByte-ShuffleBytes-PersAutoDict-PersAutoDict-CMP-ChangeBit-ShuffleBytes-PersAutoDict-ChangeBinInt-EraseBytes-EraseBytes-ShuffleBytes-ChangeByte-ShuffleBytes-ChangeBit-EraseBytes-CMP-ShuffleBytes-ChangeByte-ChangeBinInt-EraseBytes-ChangeBinInt-ChangeByte-EraseBytes-ChangeByte-CrossOver-ShuffleBytes-EraseBytes-EraseBytes-ShuffleBytes-ChangeBit-EraseBytes-CopyPart-ShuffleBytes-ShuffleBytes-CrossOver-CopyPart-ChangeBinInt-ShuffleBytes-CrossOver-InsertByte-InsertByte-ChangeBinInt-ChangeBinInt-CopyPart-EraseBytes-ShuffleBytes-ChangeBit-ChangeBit-EraseBytes-ChangeByte-ChangeByte-ChangeBinInt-CrossOver-ChangeBinInt-ChangeBinInt-ShuffleBytes-ShuffleBytes-ChangeByte-ChangeByte-ChangeBinInt-ShuffleBytes-CrossOver-EraseBytes-CopyPart-CopyPart-CopyPart-ChangeBit-ShuffleBytes-ChangeByte-EraseBytes-ChangeByte-InsertRepeatedBytes-InsertByte-InsertRepeatedBytes-PersAutoDict-EraseBytes-ShuffleBytes-ChangeByte-ShuffleBytes-ChangeBinInt-ShuffleBytes-ChangeBinInt-ChangeBit-CrossOver-CrossOver-ShuffleBytes-CrossOver-CopyPart-CrossOver-CrossOver-CopyPart-ChangeByte-ChangeByte-CrossOver-ChangeBit-ChangeBinInt-EraseBytes-ShuffleBytes-EraseBytes-CMP-PersAutoDict-PersAutoDict-InsertByte-ChangeBit-ChangeByte-CopyPart-CrossOver-ChangeByte-ChangeBit-ChangeByte-CopyPart-ChangeBinInt-EraseBytes-CrossOver-ChangeBit-CrossOver-PersAutoDict-CrossOver-ChangeByte-CrossOver-ChangeByte-ChangeByte-CrossOver-ShuffleBytes-CopyPart-CopyPart-ShuffleBytes-ChangeByte-ChangeByte-ChangeBinInt-ChangeBinInt-ChangeBinInt-ChangeBinInt-ShuffleBytes-CrossOver-ChangeBinInt-ShuffleBytes-ChangeBit-PersAutoDict-ChangeBinInt-ShuffleBytes-ChangeBinInt-ChangeByte-CrossOver-ChangeBit-CopyPart-ChangeBit-ChangeBit-CopyPart-ChangeByte-PersAutoDict-ChangeBit-ShuffleBytes-ChangeByte-ChangeBit-CrossOver-ChangeByte-CrossOver-ChangeByte-CrossOver-ChangeBit-ChangeByte-ChangeBinInt-PersAutoDict-CopyPart-ChangeBinInt-ChangeBit-CrossOver-ChangeBit-PersAutoDict-ShuffleBytes-EraseBytes-CrossOver-ChangeByte-ChangeBinInt-ShuffleBytes-ChangeBinInt-InsertRepeatedBytes-PersAutoDict-CrossOver-ChangeByte-Custom-PersAutoDict-CopyPart-CopyPart-ChangeBinInt-ShuffleBytes-ChangeBinInt-ChangeBit-ShuffleBytes-CrossOver-CMP-ChangeByte-CopyPart-ShuffleBytes-CopyPart-CopyPart-CrossOver-CrossOver-CrossOver-ShuffleBytes-ChangeByte-ChangeBinInt-ChangeBit-ChangeBit-ChangeBit-ChangeByte-EraseBytes-ChangeByte-ChangeBit-ChangeByte-ChangeByte-CopyPart-PersAutoDict-ChangeBinInt-PersAutoDict-PersAutoDict-PersAutoDict-CopyPart-CopyPart-CrossOver-ChangeByte-ChangeBinInt-ShuffleBytes-ChangeBit-CopyPart-EraseBytes-CopyPart-CopyPart-CrossOver-ChangeByte-EraseBytes-ShuffleBytes-ChangeByte-CopyPart-EraseBytes-CopyPart-CrossOver-ChangeBinInt-ChangeBinInt-InsertByte-ChangeBinInt-ChangeBit-ChangeByte-CopyPart-ChangeByte-EraseBytes-ChangeByte-ChangeBit-ChangeByte-ShuffleBytes-CopyPart-ChangeBinInt-EraseBytes-CrossOver-ChangeBit-ChangeBit-CrossOver-EraseBytes-ChangeBinInt-CopyPart-CopyPart-ChangeBinInt-ChangeBit-EraseBytes-InsertRepeatedBytes-EraseBytes-ChangeBit-CrossOver-CrossOver-EraseBytes-EraseBytes-ChangeByte-CopyPart-CopyPart-ShuffleBytes-ChangeByte-ChangeBit-ChangeByte-EraseBytes-ChangeBit-ChangeByte-ChangeByte-CrossOver-CopyPart-EraseBytes-ChangeByte-EraseBytes-ChangeByte-ShuffleBytes-ShuffleBytes-ChangeByte-CopyPart-ChangeByte-ChangeByte-ChangeBit-CopyPart-ChangeBit-ChangeBinInt-CopyPart-ShuffleBytes-ChangeBit-ChangeBinInt-ChangeBit-EraseBytes-CMP-CrossOver-CopyPart-ChangeBinInt-CrossOver-CrossOver-CopyPart-CrossOver-CrossOver-InsertByte-InsertByte-CopyPart-Custom- DE: "warn"-"\x00\x00\x00\x80"-"\xfe\xff\xff\xfb"-"\xff\xff"-"\x10\x00\x00\x00"-"\xfe\xff\xff\xff"-"\xff\xff\xff\xf6"-"U\x01\x00\x00\x00\x00\x00\x00"-"\xd9\xff\xff\xff"-"\xfe\xff\xff\xea"-"\xf0\xff\xff\xff"-"\xfc\xff\xff\xff"-"warn"-"\xff\xff\xff\xff"-"\xfe\xff\xff\xfb"-"\x00\x00\x00\x80"-"\xfe\xff\xff\xf1"-"\xfe\xff\xff\xea"-"\x00\x00\x00\x00\x00\x00\x012"-"\xe2\x00"-"\xfb\xff\xff\xff"-"\x00\x00\x00\x00"-"\xe9\xff\xff\xff"-"\xff\xff"-"\x00\x00\x00\x80"-"\x01\x00\x04\xc9"-"\xf0\xff\xff\xff"-"\xf9\xff\xff\xff"-"\xff\xff\xff\xff\xff\xff\xff\x12"-"\xe2\x00"-"\xfe\xff\xff\xff"-"\xfe\xff\xff\xea"-"\xff\xff\xff\xff"-"\xf4\xff\xff\xff"-"\xe9\xff\xff\xff"-"\xf1\xff\xff\xff"-
    #48    NEW    cov: 4502 ft: 9151 corp: 27/750Kb lim: 64000 exec/s: 2 rss: 458Mb L: 50772/50772 MS: 259 ChangeByte-ShuffleBytes-ChangeBinInt-ChangeByte-ChangeByte-ChangeByte-ChangeByte-ChangeBit-CopyPart-CrossOver-CopyPart-ChangeByte-CrossOver-CopyPart-ChangeBit-ChangeByte-EraseBytes-ChangeByte-CopyPart-CopyPart-CopyPart-ChangeBit-EraseBytes-ChangeBinInt-CrossOver-CopyPart-CrossOver-CopyPart-ChangeBit-ChangeByte-ChangeBit-InsertByte-CrossOver-InsertRepeatedBytes-InsertRepeatedBytes-InsertRepeatedBytes-ChangeBinInt-EraseBytes-InsertRepeatedBytes-InsertByte-ChangeBit-ShuffleBytes-ChangeBit-ChangeBit-CopyPart-ChangeBit-ChangeByte-CrossOver-ChangeBinInt-ChangeByte-CrossOver-CMP-ChangeByte-CrossOver-ChangeByte-ShuffleBytes-ShuffleBytes-ChangeByte-ChangeBinInt-CopyPart-EraseBytes-CrossOver-ChangeBit-ChangeBinInt-InsertByte-ChangeBit-CopyPart-ChangeBinInt-ChangeByte-CrossOver-ChangeBit-EraseBytes-CopyPart-ChangeBinInt-ChangeBit-ChangeBit-ChangeByte-CopyPart-ChangeBinInt-CrossOver-PersAutoDict-ChangeByte-ChangeBit-ChangeByte-ChangeBinInt-ChangeBinInt-EraseBytes-CopyPart-CopyPart-ChangeByte-ChangeByte-EraseBytes-PersAutoDict-CopyPart-ChangeByte-ChangeByte-EraseBytes-CrossOver-CopyPart-CopyPart-CopyPart-ChangeByte-ChangeBit-CMP-CopyPart-ChangeBinInt-ChangeBinInt-CrossOver-ChangeBit-ChangeBit-EraseBytes-ChangeByte-ShuffleBytes-ChangeBit-ChangeBinInt-CMP-InsertRepeatedBytes-CopyPart-Custom-ChangeByte-CrossOver-EraseBytes-ChangeBit-CopyPart-CrossOver-CMP-ShuffleBytes-EraseBytes-CrossOver-PersAutoDict-ChangeByte-CrossOver-CopyPart-CrossOver-CrossOver-ShuffleBytes-ChangeBinInt-CrossOver-ChangeBinInt-ShuffleBytes-PersAutoDict-ChangeByte-EraseBytes-ChangeBit-CrossOver-EraseBytes-CrossOver-ChangeBit-ChangeBinInt-EraseBytes-InsertByte-InsertRepeatedBytes-InsertByte-InsertByte-ChangeByte-ChangeBinInt-ChangeBit-CrossOver-ChangeByte-CrossOver-EraseBytes-ChangeByte-ShuffleBytes-ChangeBit-ChangeBit-ShuffleBytes-CopyPart-ChangeByte-PersAutoDict-ChangeBit-ChangeByte-InsertRepeatedBytes-CMP-CrossOver-ChangeByte-EraseBytes-ShuffleBytes-CrossOver-ShuffleBytes-ChangeBinInt-ChangeBinInt-CopyPart-PersAutoDict-ShuffleBytes-ChangeBit-CopyPart-ShuffleBytes-CopyPart-EraseBytes-ChangeByte-ChangeBit-ChangeBit-ChangeBinInt-ChangeByte-CopyPart-EraseBytes-ChangeBinInt-EraseBytes-EraseBytes-PersAutoDict-CMP-PersAutoDict-CrossOver-CrossOver-ChangeBit-CrossOver-PersAutoDict-CrossOver-CopyPart-ChangeByte-EraseBytes-ChangeByte-ShuffleBytes-ChangeByte-ChangeByte-CrossOver-ChangeBit-EraseBytes-ChangeByte-EraseBytes-ChangeBinInt-CrossOver-CrossOver-EraseBytes-ChangeBinInt-CrossOver-ChangeBit-ShuffleBytes-ChangeBit-ChangeByte-EraseBytes-ChangeBit-CrossOver-CrossOver-CrossOver-ChangeByte-ChangeBit-ShuffleBytes-ChangeBit-ChangeBit-EraseBytes-CrossOver-CrossOver-CopyPart-ShuffleBytes-ChangeByte-ChangeByte-CopyPart-CrossOver-CopyPart-CrossOver-CrossOver-EraseBytes-EraseBytes-ShuffleBytes-InsertRepeatedBytes-ChangeBit-CopyPart-Custom- DE: "\xfe\xff\xff\xfc"-"\x00\x00\x00\x00"-"F\x00"-"\xf3\xff\xff\xff"-"St9exception"-"_\x00\x00\x00"-"\xf6\xff\xff\xff"-"\xfe\xff\xff\xff"-"\x00\x00\x00\x00"-"p\x02\x00\x00\x00\x00\x00\x00"-"\xfe\xff\xff\xfb"-"\xff\xff"-"\xff\xff\xff\xff"-"\x01\x00\x00\x07"-"\xfe\xff\xff\xfe"-

These are prohibitively large and of limited value in the default case (when
someone is running the fuzzer, not debugging it), in my opinion.

Reviewed By: morehouse

Differential Revision: https://reviews.llvm.org/D86658
The file was addedcompiler-rt/test/fuzzer/CustomMutatorWithLongSequencesTest.cpp
The file was modifiedcompiler-rt/lib/fuzzer/FuzzerMutate.h
The file was modifiedcompiler-rt/lib/fuzzer/FuzzerMutate.cpp
The file was modifiedcompiler-rt/test/fuzzer/fuzzer-custommutator.test
The file was modifiedcompiler-rt/lib/fuzzer/FuzzerLoop.cpp
Commit ab919eed2115017f99cd4bf7f83a051030aa7e0f by thakis
[gn build] port 5ffd940ac02 a bit more
The file was modifiedllvm/utils/gn/secondary/llvm/lib/FileCheck/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/llvm/utils/FileCheck/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/llvm/unittests/FileCheck/BUILD.gn
Commit 1914fc9ecafe558ecd3ac1903cf729b880811012 by llvmgnsyncbot
[gn build] Port 3d90a61cf2e
The file was modifiedllvm/utils/gn/secondary/llvm/tools/llvm-readobj/BUILD.gn
Commit 293fc6c2f3ed064e6b938af876b77c9ce2581a95 by llvmgnsyncbot
[gn build] Port 3e1e5f54492
The file was modifiedllvm/utils/gn/secondary/clang/lib/Driver/BUILD.gn
Commit 40fed004865566cf29301c8b0f0c80d9fb0980ef by tejohnson
First commit on the release/11.x branch.
The file was modifiedllvm/docs/ReleaseNotes.rst
Commit cb8912799d4372a3a1c0bf528bb4c4885caf4c45 by mascasa
[fuzzer] Create user provided fuzzer writeable directories when requested if they dont exist

Currently, libFuzzer will exit with an error message if a non-existent
directory is provided for any of the appropriate arguments. For cases
where libFuzzer is used in a specialized embedded environment, it would
be much easier to have libFuzzer create the directories for the user.

This patch accommodates for this scenario by allowing the user to provide
the argument `-create_missing_dirs=1` which makes libFuzzer attempt to
create the `artifact_prefix`, `exact_artifact_path`,
`features_dir` and/or corpus directory if they don't already exist rather
than throw an error and exit.

Split off from D84808 as requested [here](https://reviews.llvm.org/D84808#2208546).

Reviewed By: morehouse

Differential Revision: https://reviews.llvm.org/D86733
The file was modifiedcompiler-rt/lib/fuzzer/FuzzerFlags.def
The file was modifiedcompiler-rt/lib/fuzzer/FuzzerDriver.cpp
The file was modifiedcompiler-rt/test/fuzzer/fuzzer-dirs.test
The file was modifiedcompiler-rt/lib/fuzzer/FuzzerIO.cpp
The file was modifiedcompiler-rt/lib/fuzzer/FuzzerIO.h
Commit 93eed63d2f31888d9d8eb0712287e44771289f6f by atrosinenko
[builtins] Make __div[sdt]f3 handle denormal results

This patch introduces denormal result support to soft-float division
implementation unified by D85031.

Reviewed By: sepavloff

Differential Revision: https://reviews.llvm.org/D85032
The file was modifiedcompiler-rt/test/builtins/Unit/divdf3_test.c
The file was modifiedcompiler-rt/test/builtins/Unit/divsf3_test.c
The file was modifiedcompiler-rt/lib/builtins/fp_div_impl.inc
The file was modifiedcompiler-rt/test/builtins/Unit/divtf3_test.c
Commit c292fba46fc2919c5310c07911e3650d2b24cf28 by asbirlea
[MemorySSA] Update phi map with replacement value.
The file was modifiedllvm/lib/Analysis/MemorySSAUpdater.cpp
Commit 10670bdf5451b85c5613cec0e8a78303f8914bfb by mascasa
Revert "[fuzzer] Create user provided fuzzer writeable directories when requested if they dont exist"

This reverts commit cb8912799d4372a3a1c0bf528bb4c4885caf4c45, since the
test fails on Windows.
The file was modifiedcompiler-rt/lib/fuzzer/FuzzerIO.h
The file was modifiedcompiler-rt/lib/fuzzer/FuzzerFlags.def
The file was modifiedcompiler-rt/lib/fuzzer/FuzzerDriver.cpp
The file was modifiedcompiler-rt/lib/fuzzer/FuzzerIO.cpp
The file was modifiedcompiler-rt/test/fuzzer/fuzzer-dirs.test
Commit 99f3b231cb21abc567c93813650cd76cfa614325 by Louis Dionne
[libc++] Workaround timespec_get not always being available in Apple SDKs

timespec_get is not available in Apple SDKs when (__DARWIN_C_LEVEL >= __DARWIN_C_FULL)
isn't true, which leads to libc++ trying to import ::timespec_get into
namespace std when it's not available. This issue has been reported to
Apple's libc, but we need a workaround in the meantime.

https://llvm.org/PR47208
rdar://68157284
The file was modifiedlibcxx/include/__config
The file was addedlibcxx/test/libcxx/language.support/timespec_get.xopen.compile.pass.cpp
Commit ae95ceeb8f98d81f615c69da02f73b5ee6b1519a by huberjn
[OpenMP] Consolidate error handling and debug messages in Libomptarget

Summary:

This patch consolidates the error handling and messaging routines to a single
file omptargetmessage. The goal is to simplify the error handling interface
prior to adding more error handling support

Reviewers: jdoerfert grokos ABataev AndreyChurbanov ronlieb JonChesterfield ye-luo tianshilei1992

Subscribers: danielkiss guansong jvesely kerbowa nhaehnle openmp-commits sstefan1 yaxunl
The file was modifiedopenmp/libomptarget/include/omptarget.h
The file was modifiedopenmp/libomptarget/src/interface.cpp
The file was modifiedopenmp/libomptarget/plugins/cuda/src/rtl.cpp
The file was modifiedopenmp/libomptarget/plugins/generic-elf-64bit/src/rtl.cpp
The file was modifiedopenmp/libomptarget/src/omptarget.cpp
The file was modifiedopenmp/libomptarget/plugins/common/elf_common.c
The file was modifiedopenmp/libomptarget/plugins/amdgpu/src/rtl.cpp
The file was modifiedopenmp/libomptarget/src/rtl.cpp
The file was addedopenmp/libomptarget/include/Debug.h
The file was modifiedopenmp/libomptarget/src/api.cpp
The file was modifiedopenmp/libomptarget/plugins/ve/src/rtl.cpp
The file was modifiedopenmp/libomptarget/src/private.h
Commit 5987da8764b71cd59fec772323cc2003bd82da38 by resistor
Revert "Revert "Reapply D70800: Fix AArch64 AAPCS frame record chain""

This reverts commit bc9a29b9ee6ade4894252b1470977142c32b4602.

The reasoning that this patch was wrong was itself incorrect
(see discussion on llvm-commits). This patch does seem to be exposing
a latent SVE code generation bug on non-public tests, which should
not block a correctness fix for public, non-SVE use cases.
The file was modifiedllvm/lib/Target/AArch64/AArch64FrameLowering.cpp
The file was addedllvm/test/CodeGen/AArch64/framelayout-frame-record.mir
The file was addedllvm/test/CodeGen/AArch64/framelayout-unaligned-fp.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
The file was addedllvm/test/CodeGen/AArch64/framelayout-fp-csr.ll
Commit 3e753ce1ab5288f1fa5fb03711474ac2800e2f14 by Lang Hames
[ORC] Add unit test for HasMaterializationSideEffectsOnly failure behavior.
The file was modifiedllvm/unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp
Commit b1f394862053867cdc6b2300e725e053504519d5 by douglas.yung
Do not emit "-tune-cpu generic" for PS4 platform

For the PS4, do not emit "-tune-cpu generic" since the platform only has 1 known CPU and we do not want to prevent optimizations by tuning for a generic rather than the specific processor it contains.

Reviewed By: probinson

Differential Revision: https://reviews.llvm.org/D86965
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was modifiedclang/test/Driver/ps4-cpu-defaults.cpp
Commit 96f0b57568c3047fde0c1e4b4f52401ce34f2da2 by aeubanks
[Bindings] Add LLVMAddInstructionSimplifyPass

Reviewed By: sroland

Differential Revision: https://reviews.llvm.org/D86764
The file was modifiedllvm/lib/Transforms/Scalar/InstSimplifyPass.cpp
The file was modifiedllvm/include/llvm-c/Transforms/Scalar.h
The file was modifiedllvm/docs/ReleaseNotes.rst
Commit 4783e2c9c603ed6aeacc76bb1177056a9d307bd1 by craig.topper
[MachineCopyPropagation] In isNopCopy, check the destination registers match in addition to the source registers.

Previously if the source match we asserted that the destination
matched. But GPR <-> mask register copies on X86 can violate this
since we use the same K-registers for multiple sizes.

Fixes this ISPC issue https://github.com/ispc/ispc/issues/1851

Differential Revision: https://reviews.llvm.org/D86507
The file was modifiedllvm/lib/CodeGen/MachineCopyPropagation.cpp
The file was addedllvm/test/CodeGen/X86/machine-cp-mask-reg.mir
Commit d7e16ca28f48000d4fb3e3388d782cbd9ad02e62 by hualilia
[LV] Interleave to expose ILP for small loops with scalar reductions.

Interleave for small loops that have reductions inside,
which breaks dependencies and expose.

This gives very significant performance improvements for some benchmarks.
Because small loops could be in very hot functions in real applications.

Differential Revision: https://reviews.llvm.org/D81416
The file was addedllvm/test/Transforms/LoopVectorize/PowerPC/interleave_IC.ll
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit 7139736261e047e9cca030e2ee5912bf2a16f816 by mascasa
Revert "[libfuzzer] Reduce default verbosity when printing large mutation sequences"

This reverts commit 2665425908e00618074e42155ec922a37f7c9002 due to
buildbot failure.
The file was modifiedcompiler-rt/test/fuzzer/fuzzer-custommutator.test
The file was modifiedcompiler-rt/lib/fuzzer/FuzzerMutate.cpp
The file was modifiedcompiler-rt/lib/fuzzer/FuzzerLoop.cpp
The file was removedcompiler-rt/test/fuzzer/CustomMutatorWithLongSequencesTest.cpp
The file was modifiedcompiler-rt/lib/fuzzer/FuzzerMutate.h
Commit 0d966ae4b2ac0344e15888d0f0a81c322e3d6dd2 by flo
[Loads] Add canReplacePointersIfEqual helper.

This patch adds an initial, incomeplete and unsound implementation of
canReplacePointersIfEqual to check if a pointer value A can be replaced
by another pointer value B, that are deemed to be equivalent through
some means (e.g. information from conditions).

Note that is in general not sound to blindly replace pointers based on
equality, for example if they are based on different underlying objects.

LLVM's memory model is not completely settled as of now; see
https://bugs.llvm.org/show_bug.cgi?id=34548 for a more detailed
discussion.

The initial version of canReplacePointersIfEqual only rejects a very
specific case: replacing a pointer with a constant expression that is
not dereferenceable. Such a replacement is problematic and can be
restricted relatively easily without impacting most code. Using it to
limit replacements in GVN/SCCP/CVP only results in small differences in
7 programs out of MultiSource/SPEC2000/SPEC2006 on X86 with -O3 -flto.

This patch is supposed to be an initial step to improve the current
situation and the helper should be made stricter in the future. But this
will require careful analysis of the impact on performance.

Reviewed By: aqjune

Differential Revision: https://reviews.llvm.org/D85524
The file was modifiedllvm/lib/Analysis/Loads.cpp
The file was modifiedllvm/unittests/Analysis/LoadsTest.cpp
The file was modifiedllvm/include/llvm/Analysis/Loads.h
Commit c90f15d25a176d7990f3a10b917caf0999a85b0d by rupprecht
[NFC] Fix unused var in release build
The file was modifiedllvm/lib/Analysis/Loads.cpp
Commit 1f4e7463b5e3ff654c84371527767830e51db10d by michael.hliao
[amdgpu] Run SROA after loop unrolling.

Summary: - There are promotable `alloca`s after loop unrolling.

Reviewers: rampitec, arsenm

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, nikic, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D84252
The file was addedllvm/test/CodeGen/AMDGPU/extra-sroa-after-unroll.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/opt-pipeline.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
Commit 8693ddc74371dedc742c9f3d3e4eda1da72c13ea by rupprecht
Revert "[GlobalISel] Fold xor(cmp(pred, _, _), 1) -> cmp(inverse(pred), _, _)" (and dependent patch "Optimize away a Not feeding a brcond by using tbz instead of tbnz.")

This reverts commit 8ad8f484b63ca507417b58c9016d2761f2b1a1a8. It causes crashes when running `ninja check-llvm-codegen-aarch64-globalisel`, e.g.
http://lab.llvm.org:8011/builders/clang-with-thin-lto-ubuntu/builds/24132/steps/test-stage1-compiler/logs/stdio.
Note that the crash does not seem to reproduce in debug builds.

5ded4442520d3dbb1aa72e6fe03cddef8828c618 depends on this, so revert that too.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
The file was removedllvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-invert-cmp.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
The file was modifiedllvm/lib/CodeGen/GlobalISel/Utils.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/Utils.h
The file was modifiedllvm/include/llvm/Target/GlobalISel/Combine.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
The file was removedllvm/test/CodeGen/AArch64/GlobalISel/select-brcond-of-not.mir