SuccessChanges

Summary

  1. [GlobalISel] Disable the indexed loads combine completely unless forced. NFC. (details)
  2. Revert "[Asan] Cleanup atomic usage in allocator" (details)
  3. [Asan] Cleanup atomic usage in allocator (details)
  4. [InstSimplify] Fold degenerate abs of abs form (details)
  5. Add proper move ctor/move assign to APValue. NFCI. (details)
  6. [ARM] Regenerate tests. NFC (details)
  7. [ARM] Remove -O3 from mve intrinsic tests. NFC (details)
  8. [X86][AVX] lowerShuffleWithPERMV - adjust binary shuffle masks to account for widening on non-VLX targets (details)
  9. [SmallVector] Move error handling out of line (details)
  10. Thread safety analysis: Test and document release_generic_capability (details)
  11. Thread safety analysis: Improve documentation for scoped capabilities (details)
  12. [mlir] Add Shaped Type, Tensor Type and MemRef Type to python bindings. (details)
  13. [DSE,MemorySSA] Add a few additional debug messages. (details)
  14. [compiler-rt] Implement __clear_cache() on OpenBSD/arm (details)
  15. [ValueTracking] Avoid known bits fallback for non-zero get check (NFCI) (details)
  16. [asan_symbolize] Pass --demangle/--no-demangle instead of --demangle={True,False} (details)
  17. [PowerPC] Implement Vector Expand Mask builtins in LLVM/Clang (details)
  18. [WebAssembly] Fix incorrect assumption of simple value types (details)
Commit d0abc757495349fd053beeaea81cd954c2e457e7 by Amara Emerson
[GlobalISel] Disable the indexed loads combine completely unless forced. NFC.

The post-index matcher, before it queries the target legality, walks uses
of some instructions which in pathological cases can be massive. Since
no targets actually support indexed loads yet, disable this to stop wasting
compile time on something which is going to fail anyway.
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
Commit b2e27a86c18e13043be0ed7bf2855d313cc0ac38 by Vitaly Buka
Revert "[Asan] Cleanup atomic usage in allocator"

Crashes on PPC

This reverts commit eb87e1dbcfdf15c0711146ff3e6b2e1e40c8863a.
The file was modifiedcompiler-rt/lib/asan/asan_allocator.cpp
Commit b11db3606ca180521f8400aed730281108b350b4 by Vitaly Buka
[Asan] Cleanup atomic usage in allocator

There are no know bugs related to this, still it may fix some latent ones.
Main concerns with preexisting code:
1. Inconsistent atomic/non-atomic access to the same field.
2. Assumption that bitfield chunk_state is always the first byte without
    even taking into account endianness.

Reviewed By: morehouse

Differential Revision: https://reviews.llvm.org/D86917
The file was modifiedcompiler-rt/lib/asan/asan_allocator.cpp
Commit ff218cbc84ff3783cb5ad030397adef8c9e8d444 by nikita.ppv
[InstSimplify] Fold degenerate abs of abs form

This addresses the remaining issue from D87188. Due to a series of
folds, we may end up with abs-of-abs represented as
x == 0 ? -abs(x) : abs(x). Rather than recognizing this as a special
abs pattern and doing an abs-of-abs fold on it afterwards,
I'm directly folding this to one of the select operands in InstSimplify.

The general pattern falls into the "select with operand replaced"
category, but that fold is not powerful enough to recognize that
both hands of the select are the same for value zero.

Differential Revision: https://reviews.llvm.org/D87197
The file was modifiedllvm/lib/Analysis/InstructionSimplify.cpp
The file was modifiedllvm/test/Transforms/InstSimplify/abs_intrinsic.ll
Commit 4d0312c8e05be5353c6c29b31036647dceca3ce5 by benny.kra
Add proper move ctor/move assign to APValue. NFCI.

Swapping 64 bytes to make a move isn't cheap.
The file was modifiedclang/lib/AST/APValue.cpp
The file was modifiedclang/include/clang/AST/APValue.h
Commit d866dc374986ac1cff6b4950ea5fa3f8687fdadd by david.green
[ARM] Regenerate tests. NFC
The file was modifiedllvm/test/CodeGen/Thumb2/mve-pred-vctpvpsel.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-gather-scatter-tailpred.ll
Commit 667e800bb3a8c1bdda0cabad7549c766b3424064 by david.green
[ARM] Remove -O3 from mve intrinsic tests. NFC
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vminq.c
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vminaq.c
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vmaxq.c
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vminnmq.c
Commit ecac5c28089283fbaef1fec758535ca700095a09 by llvm-dev
[X86][AVX] lowerShuffleWithPERMV - adjust binary shuffle masks to account for widening on non-VLX targets

rGabd33bf5eff2 enabled us to pad 128/256-bit shuffles to 512-bit on non-VLX targets, but wasn't updating binary shuffles to account for the new vector width.
The file was modifiedllvm/test/CodeGen/X86/shuffle-vs-trunc-512.ll
The file was modifiedllvm/test/CodeGen/X86/shuffle-strided-with-offset-512.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 8c386c94749a78392fd763f8449ca3e55f030ffd by benny.kra
[SmallVector] Move error handling out of line

This reduces duplication and avoids emitting ice cold code into every
instance of grow().
The file was modifiedllvm/include/llvm/ADT/SmallVector.h
The file was modifiedllvm/lib/Support/SmallVector.cpp
Commit cc6713a2c35edf17cfb567284cc76b374308e5e4 by aaronpuchert
Thread safety analysis: Test and document release_generic_capability

The old locking attributes had a generic release, but as it turns out
the capability-based attributes have it as well.

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D87064
The file was modifiedclang/docs/ThreadSafetyAnalysis.rst
The file was modifiedclang/test/SemaCXX/thread-safety-annotations.h
Commit bbb3baf6205c54231257f64fd18661a13a5c97ee by aaronpuchert
Thread safety analysis: Improve documentation for scoped capabilities

They are for more powerful than the current documentation implies, this
adds

* adopting a lock,
* deferring a lock,
* manually unlocking the scoped capability,
* relocking the scoped capability, possibly in a different mode,
* try-relocking the scoped capability.

Also there is now a generic explanation how attributes on scoped
capabilities work. There has been confusion in the past about how to
annotate them (see e.g. PR33504), hopefully this clears things up.

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D87066
The file was modifiedclang/docs/ThreadSafetyAnalysis.rst
Commit 54d432aa6b835ee7e835d0626c15ca5e7eb83ab4 by stellaraccident
[mlir] Add Shaped Type, Tensor Type and MemRef Type to python bindings.

Based on the PyType and PyConcreteType classes, this patch implements the bindings of Shaped Type, Tensor Type and MemRef Type subclasses.
The Tensor Type and MemRef Type are bound as ranked and unranked separately.
This patch adds the ***GetChecked C API to make sure the python side can get a valid type or a nullptr.
Shaped type is not a kind of standard types, it is the base class for vectors, memrefs and tensors, this patch binds the PyShapedType class as the base class of Vector Type, Tensor Type and MemRef Type subclasses.

Reviewed By: stellaraccident

Differential Revision: https://reviews.llvm.org/D87091
The file was modifiedmlir/lib/CAPI/IR/StandardTypes.cpp
The file was modifiedmlir/lib/Bindings/Python/IRModules.cpp
The file was modifiedmlir/test/Bindings/Python/ir_types.py
The file was modifiedmlir/include/mlir-c/StandardTypes.h
Commit 16bb71fd4f898d296397336ecb81b79a7297933c by flo
[DSE,MemorySSA] Add a few additional debug messages.
The file was modifiedllvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
Commit 8542dab909f895a8b6812428bb5e1acf7ea15305 by brad
[compiler-rt] Implement __clear_cache() on OpenBSD/arm
The file was modifiedcompiler-rt/lib/builtins/clear_cache.c
Commit b536cbaac5f85a3a1ab8c971c300cd27e5603fda by nikita.ppv
[ValueTracking] Avoid known bits fallback for non-zero get check (NFCI)

The known bits fall back will never be able to infer a non-null
value here, so don't bother.
The file was modifiedllvm/lib/Analysis/ValueTracking.cpp
Commit ab68517e6b7e51b84c4b0e813a30258ec1ce5da5 by i
[asan_symbolize] Pass --demangle/--no-demangle instead of --demangle={True,False}

`--demangle={True,False}` were accepted but disallowed after llvm-symbolizer's switch to OptTable.
(`--demangle={true,false}` were temporarily supported but they are case sensitive.)
The file was modifiedcompiler-rt/lib/asan/scripts/asan_symbolize.py
Commit efa57f9a7adb11a14b4e0d930f49070c769fa6ac by amy.kwan1
[PowerPC] Implement Vector Expand Mask builtins in LLVM/Clang

This patch implements the vec_expandm function prototypes in altivec.h in order
to utilize the vector expand with mask instructions introduced in Power10.

Differential Revision: https://reviews.llvm.org/D82727
The file was modifiedclang/lib/Headers/altivec.h
The file was modifiedclang/test/CodeGen/builtins-ppc-p10vector.c
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrPrefix.td
The file was modifiedllvm/include/llvm/IR/IntrinsicsPowerPC.td
The file was modifiedclang/include/clang/Basic/BuiltinsPPC.def
The file was modifiedllvm/test/CodeGen/PowerPC/p10-vector-mask-ops.ll
Commit caee15a0ed52471bd329d01dc253ec9be3936c6d by tlively
[WebAssembly] Fix incorrect assumption of simple value types

Fixes PR47375, in which an assertion was triggering because
WebAssemblyTargetLowering::isVectorLoadExtDesirable was improperly
assuming the use of simple value types.

Differential Revision: https://reviews.llvm.org/D87110
The file was addedllvm/test/CodeGen/WebAssembly/pr47375.ll
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp