SuccessChanges

Summary

  1. [NFC][ASAN] Add brackets around not command Under certain execution conditions, the `not` command binds to the command the output is piped to rather than the command piping the output. In this case, that flips the return code of the FileCheck invocation, causing a failure when FileCheck succeeds.
  2. [NFC][InstCombine] Fixup commutative/negative tests with icmp preds in @llvm.umul.with.overflow tests
  3. [InstSimplify][NFC] Tests for skipping 'div-by-0' checks before inverted @llvm.umul.with.overflow It would be already handled by the non-inverted case if we were hoisting the `not` in InstCombine, but we don't (granted, we don't sink it in this case either), so this is a separate case.
  4. [NFC][PhaseOredering][SimplifyCFG] Add more runlines to umul.with.overflow tests This way it will be more obvious that the problem is both in cost threshold and in hardcoded benefit check, plus will show how the instsimplify cleans this all in the end.
  5. [TargetLowering] Add SimplifyMultipleUseDemandedBits This patch introduces the DAG version of SimplifyMultipleUseDemandedBits, which attempts to peek through ops (mainly and/or/xor so far) that don't contribute to the demandedbits/elts of a node - which means we can do this even in cases where we have multiple uses of an op, which normally requires us to demanded all bits/elts. The intention is to remove a similar instruction - SelectionDAG::GetDemandedBits - once SimplifyMultipleUseDemandedBits has matured. The InstCombine version of SimplifyMultipleUseDemandedBits can constant fold which I haven't added here yet, and so far I've only wired this up to some basic binops (and/or/xor/add/sub/mul) to demonstrate its use. We do see a couple of regressions that need to be addressed: AMDGPU unsigned dot product codegen retains an AND mask (for ZERO_EXTEND) that it previously removed (but otherwise the dotproduct codegen is a lot better). X86/AVX2 has poor handling of vector ANY_EXTEND/ANY_EXTEND_VECTOR_INREG - it prematurely gets converted to ZERO_EXTEND_VECTOR_INREG. The code owners have confirmed its ok for these cases to fixed up in future patches. Differential Revision: https://reviews.llvm.org/D63281
  6. [RISCV] Re-enable rv32i-aliases-invalid.s test We were getting test failures on some builders, which pointed to @LINE being an undefined variable. I think that these failures should have been fixed by https://reviews.llvm.org/rL366434, so I'm re-enabling the test.
  7. [Object/ELF.h] - Improve testing of the fields in ELFFile<ELFT>::sections(). This eliminates a one error untested and also introduces a error for one more possible case which lead to crash previously. Differential revision: https://reviews.llvm.org/D64987
Revision 366805 by lei:
[NFC][ASAN] Add brackets around not command

Under certain execution conditions, the `not` command binds to the command the
output is piped to rather than the command piping the output. In this case, that
flips the return code of the FileCheck invocation, causing a failure when
FileCheck succeeds.
Change TypePath in RepositoryPath in Workspace
The file was modified/compiler-rt/trunk/test/asan/TestCases/Linux/read_binary_name_regtest.c (diff)compiler-rt.src/test/asan/TestCases/Linux/read_binary_name_regtest.c
Revision 366802 by lebedevri:
[NFC][InstCombine] Fixup commutative/negative tests with icmp preds in @llvm.umul.with.overflow tests
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/Transforms/InstCombine/unsigned-mul-lack-of-overflow-check-via-udiv-of-allones.ll (diff)llvm.src/test/Transforms/InstCombine/unsigned-mul-lack-of-overflow-check-via-udiv-of-allones.ll
The file was modified/llvm/trunk/test/Transforms/InstCombine/unsigned-mul-overflow-check-via-udiv-of-allones.ll (diff)llvm.src/test/Transforms/InstCombine/unsigned-mul-overflow-check-via-udiv-of-allones.ll
Revision 366801 by lebedevri:
[InstSimplify][NFC] Tests for skipping 'div-by-0' checks before inverted @llvm.umul.with.overflow

It would be already handled by the non-inverted case if we were hoisting
the `not` in InstCombine, but we don't (granted, we don't sink it
in this case either), so this is a separate case.
Change TypePath in RepositoryPath in Workspace
The file was added/llvm/trunk/test/Transforms/InstSimplify/div-by-0-guard-before-smul_ov-not.llllvm.src/test/Transforms/InstSimplify/div-by-0-guard-before-smul_ov-not.ll
The file was added/llvm/trunk/test/Transforms/InstSimplify/div-by-0-guard-before-umul_ov-not.llllvm.src/test/Transforms/InstSimplify/div-by-0-guard-before-umul_ov-not.ll
Revision 366800 by lebedevri:
[NFC][PhaseOredering][SimplifyCFG] Add more runlines to umul.with.overflow tests

This way it will be more obvious that the problem is both
in cost threshold and in hardcoded benefit check,
plus will show how the instsimplify cleans this all in the end.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/Transforms/PhaseOrdering/unsigned-multiply-overflow-check.ll (diff)llvm.src/test/Transforms/PhaseOrdering/unsigned-multiply-overflow-check.ll
The file was modified/llvm/trunk/test/Transforms/SimplifyCFG/unsigned-multiplication-will-overflow.ll (diff)llvm.src/test/Transforms/SimplifyCFG/unsigned-multiplication-will-overflow.ll
Revision 366799 by rksimon:
[TargetLowering] Add SimplifyMultipleUseDemandedBits

This patch introduces the DAG version of SimplifyMultipleUseDemandedBits, which attempts to peek through ops (mainly and/or/xor so far) that don't contribute to the demandedbits/elts of a node - which means we can do this even in cases where we have multiple uses of an op, which normally requires us to demanded all bits/elts. The intention is to remove a similar instruction - SelectionDAG::GetDemandedBits - once SimplifyMultipleUseDemandedBits has matured.

The InstCombine version of SimplifyMultipleUseDemandedBits can constant fold which I haven't added here yet, and so far I've only wired this up to some basic binops (and/or/xor/add/sub/mul) to demonstrate its use.

We do see a couple of regressions that need to be addressed:

    AMDGPU unsigned dot product codegen retains an AND mask (for ZERO_EXTEND) that it previously removed (but otherwise the dotproduct codegen is a lot better).

    X86/AVX2 has poor handling of vector ANY_EXTEND/ANY_EXTEND_VECTOR_INREG - it prematurely gets converted to ZERO_EXTEND_VECTOR_INREG.

The code owners have confirmed its ok for these cases to fixed up in future patches.

Differential Revision: https://reviews.llvm.org/D63281
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/CodeGen/TargetLowering.h (diff)llvm.src/include/llvm/CodeGen/TargetLowering.h
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (diff)llvm.src/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modified/llvm/trunk/lib/Transforms/Vectorize/SLPVectorizer.cpp (diff)llvm.src/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was modified/llvm/trunk/test/CodeGen/AArch64/bitfield-insert.ll (diff)llvm.src/test/CodeGen/AArch64/bitfield-insert.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/idot4s.ll (diff)llvm.src/test/CodeGen/AMDGPU/idot4s.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/idot4u.ll (diff)llvm.src/test/CodeGen/AMDGPU/idot4u.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/idot8s.ll (diff)llvm.src/test/CodeGen/AMDGPU/idot8s.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/idot8u.ll (diff)llvm.src/test/CodeGen/AMDGPU/idot8u.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/sdiv.ll (diff)llvm.src/test/CodeGen/AMDGPU/sdiv.ll
The file was modified/llvm/trunk/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll (diff)llvm.src/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2012-08-07-CmpISelBug.ll (diff)llvm.src/test/CodeGen/X86/2012-08-07-CmpISelBug.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-fshl-128.ll (diff)llvm.src/test/CodeGen/X86/vector-fshl-128.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-reduce-mul-widen.ll (diff)llvm.src/test/CodeGen/X86/vector-reduce-mul-widen.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-reduce-mul.ll (diff)llvm.src/test/CodeGen/X86/vector-reduce-mul.ll
Revision 366797 by lenary:
[RISCV] Re-enable rv32i-aliases-invalid.s test

We were getting test failures on some builders, which pointed to @LINE
being an undefined variable. I think that these failures should have
been fixed by https://reviews.llvm.org/rL366434, so I'm re-enabling the
test.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/MC/RISCV/rv32i-aliases-invalid.s (diff)llvm.src/test/MC/RISCV/rv32i-aliases-invalid.s
Revision 366796 by grimar:
[Object/ELF.h] - Improve testing of the fields in ELFFile<ELFT>::sections().

This eliminates a one error untested and
also introduces a error for one more possible case
which lead to crash previously.

Differential revision: https://reviews.llvm.org/D64987
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/Object/ELF.h (diff)llvm.src/include/llvm/Object/ELF.h
The file was modified/llvm/trunk/include/llvm/ObjectYAML/ELFYAML.h (diff)llvm.src/include/llvm/ObjectYAML/ELFYAML.h
The file was modified/llvm/trunk/test/Object/invalid.test (diff)llvm.src/test/Object/invalid.test
The file was modified/llvm/trunk/tools/yaml2obj/yaml2elf.cpp (diff)llvm.src/tools/yaml2obj/yaml2elf.cpp