Started 1 yr 4 mo ago
Took 3 hr 13 min on green-dragon-18

Success Build rL:366821 - C:366823 - #58188 (Jul 23, 2019 9:58:26 AM)

  • : 366821
  • : 366823
  • : 366822
  • : 364589
  • : 366740
  • : 366776
  • : 366811
  1. [clang][NFCI] Fix random typos (detail/ViewSVN)
    by jkorous
  2. [compiler-rt][builtins] Provide __clear_cache for SPARC

    While working on, two tests were failing since __clear_cache
    aborted.  While libgcc's __clear_cache is just empty, this only happens because
    gcc (in gcc/config/sparc/sparc.c (sparc32_initialize_trampoline, sparc64_initialize_trampoline))
    emits flush insns directly.

    The following patch mimics that.

    Tested on sparcv9-sun-solaris2.11.

    Differential Revision: (detail/ViewSVN)
    by ro
  3. [CMake] Add -z defs on Solaris

    Like other ELF targets, shared objects should be linked with -z defs on Solaris.

    Tested on x86_64-pc-solaris2.11 and sparcv9-sun-solaris2.11.

    Differential Revision: (detail/ViewSVN)
    by ro
  4. [clang, test] Fix Clang :: Headers/max_align.c on 64-bit SPARC

    Clang :: Headers/max_align.c currently FAILs on 64-bit SPARC:

      error: 'error' diagnostics seen but not expected:
        File /vol/llvm/src/clang/dist/test/Headers/max_align.c Line 12: static_assert failed due to requirement '8 == _Alignof(max_align_t)' ""
      1 error generated.

    This happens because SuitableAlign isn't defined for SPARCv9 unlike SPARCv8
    (which uses the default of 64 bits).  gcc's sparc/sparc.h has

      #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64)

    This patch sets SuitableAlign to match and updates the corresponding testcase.

    Tested on sparcv9-sun-solaris2.11.

    Differential Revision: (detail/ViewSVN)
    by ro
  5. [GlobalISel][AArch64] Teach GISel to handle shifts in load addressing modes

    When we select the XRO variants of loads, we can pull in very specific shifts
    (of the size of an element). E.g.

    ldr x1, [x2, x3, lsl #3]

    This teaches GISel to handle these when they're coming from shifts

    This adds a new addressing mode function, `selectAddrModeShiftedExtendXReg`
    which recognizes this pattern.

    This also packs this up with `selectAddrModeRegisterOffset` into
    `selectAddrModeXRO`. This is intended to be equivalent to `selectAddrModeXRO`
    in AArch64ISelDAGtoDAG.

    Also update load-addressing-modes to show that all of the cases here work.

    Differential Revision: (detail/ViewSVN)
    by paquette

Started by an SCM change (6 times)

This run spent:

  • 1 hr 5 min waiting;
  • 3 hr 13 min build duration;
  • 4 hr 19 min total from scheduled to completion.
LLVM/Clang Warnings: 1 warning.
    Test Result (no failures)