FailedChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [PowerPC] Modify the hasSideEffects of MTLR and MFLR from 1 to 0 (details)
  2. [NFC][LoopFusion] Fix printing of the guard branch. Reviewer: kbarton, (details)
  3. [NFC][PowerPC] Add a function tryAndWithMask to handle all the cases (details)
  4. [Bitstream] Delete skipAbbreviatedField which duplicates (details)
  5. [PowerPC] stop folding if result rlwinm mask is wrap while original (details)
Commit 6d88b7d6e712789115c149c5abb0f359d1222545 by shkzhang
[PowerPC] Modify the hasSideEffects of MTLR and MFLR from 1 to 0
Summary: If we didn't set the value for hasSideEffects bit in our td
file, `llvm-tblgen` will set it as true for those instructions which has
no match pattern. The instructions `MTLR` and `MFLR` don't set the
hasSideEffects flag and don't have match pattern, so their
hasSideEffects flag will be set true by
`llvm-tblgen`. But in fact, we can use `[LR]` to model the two
instructions, so they should not have SideEffects.
This patch is to modify the hasSideEffects of MTLR and MFLR from 1 to 0.
Reviewed By: jsji
Differential Revision: https://reviews.llvm.org/D71390
The file was modifiedllvm/test/CodeGen/PowerPC/CSR-fit.ll
The file was modifiedllvm/test/CodeGen/PowerPC/sms-phi-3.ll
The file was modifiedllvm/test/CodeGen/PowerPC/csr-split.ll
The file was modifiedllvm/test/CodeGen/PowerPC/sms-phi-1.ll
The file was modifiedllvm/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll
The file was modifiedllvm/test/CodeGen/PowerPC/sjlj.ll
The file was modifiedllvm/test/CodeGen/PowerPC/pr43527.ll
The file was modifiedllvm/test/CodeGen/PowerPC/tocSaveInPrologue.ll
The file was modifiedllvm/test/CodeGen/PowerPC/machine-pre.ll
The file was modifiedllvm/test/CodeGen/PowerPC/pr44183.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.td
The file was modifiedllvm/test/CodeGen/PowerPC/not-fixed-frame-object.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCInstr64Bit.td
The file was modifiedllvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll
Commit d1f41b2ca9991b131f9daba6953c8b805282b83a by whitneyt
[NFC][LoopFusion] Fix printing of the guard branch. Reviewer: kbarton,
jdoerfert Reviewed By: jdoerfert Subscribers: hiraditya, llvm-commits
Tag: LLVM Differential Revision: https://reviews.llvm.org/D71878
The file was modifiedllvm/lib/Transforms/Scalar/LoopFuse.cpp
Commit e973783916d3f6d086d796affbac5ed81d0e75f8 by qshanz
[NFC][PowerPC] Add a function tryAndWithMask to handle all the cases
that 'and' with constant
More patches will be committed later to exploit more about 'and' with
constant.
Differential Revision: https://reviews.llvm.org/D71693
The file was modifiedllvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
Commit 6599d004679e04f0d9e9c5b6c8503e463db79a1f by maskray
[Bitstream] Delete skipAbbreviatedField which duplicates
readAbbreviatedField
The file was modifiedllvm/lib/Bitstream/Reader/BitstreamReader.cpp
Commit 1b57749a5334ae3d854c6f8732e741ef9f977219 by czhengsz
[PowerPC] stop folding if result rlwinm mask is wrap while original
rlwinm is not.
%1:g8rc = RLWINM8 %0:g8rc, 0, 16, 9
%2:g8rc = RLWINM8 killed %1:g8rc, 0, 0, 31
->
%2:g8rc = RLWINM8 %0:g8rc, 0, 16, 9
The above folding is wrong. Before transformation, %2:g8rc is 32 bit
value. After transformation, %2:g8rc becomes a 64 bit value. This patch
fixes above issue.
Reviewed by: steven.zhang
Differential Revision: https://reviews.llvm.org/D71833
The file was modifiedllvm/lib/Target/PowerPC/PPCMIPeephole.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/fold-rlwinm.mir