FailedChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. GlobalISel: moreElementsVector for FP min/max (details)
  2. AMDGPU/GlobalISel: Add select test for fexp2 (details)
  3. [ARM][Thumb][FIX] Add unwinding information to t4 (details)
  4. [InstCombine] propagate sign argument through nested copysigns (details)
  5. AMDGPU/GlobalISel: Select llvm.amdgcn.fmad.ftz (details)
  6. [MIPS GlobalISel] Select bitreverse. Recommit (details)
  7. [InstCombine] remove stale comment on test; NFC (details)
  8. Ignore "no-frame-pointer-elim" and "no-frame-pointer-elim-non-leaf" in (details)
  9. AMDGPU/GlobalISel: Re-use MRI available in selector (details)
  10. [test] do not parse ls output for file size; NFCI (details)
  11. [X86] Add X86ISD::PCMPGT to (details)
  12. TableGen: Fix assert on PatFrags with predicate code (details)
  13. AMDGPU/GlobalISel: Select mul24 intrinsics (details)
  14. [X86][AsmParser] re-introduce 'offset' operator (details)
  15. [OpenMP] Use the OpenMPIRBuilder for `omp cancel` (details)
  16. [OpenMP] Use the OpenMPIRBuilder for `omp parallel` (details)
  17. [PowerPC][docs] Update Embedded PowerPC docs in Compiler Writers Info (details)
  18. [libomptarget][nfc] Change unintentional target_impl prefix to kmpc_impl (details)
  19. [OpenMP][FIX] Generalize a test check line (details)
  20. Remove a redundant `default:` on an exhaustive switch(enum). (details)
  21. [CodeGen] Use CreateFNeg in buildFMulAdd (details)
  22. [CodeGen] Use IRBuilder::CreateFNeg for __builtin_conj (details)
  23. [X86] Add test case for PR44412. NFC (details)
Commit 9fd31fdbd3049e3e45fc046bedb9011d0c828e87 by arsenm2
GlobalISel: moreElementsVector for FP min/max
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
Commit 18240c3cd632521f95f2ddd08ecc4f7cf0efe3c8 by arsenm2
AMDGPU/GlobalISel: Add select test for fexp2
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fexp2.mir
Commit f33fd9648c442a23f863e03ea1c806da15278fd1 by diogo.sampaio
[ARM][Thumb][FIX] Add unwinding information to t4
Summary: Add missing part of patch D71361. Now that the stack-frame can
be operated using a addw/subw instruction, they should appear in the
unwinding list.
Reviewers: dmgreen, efriedma
Reviewed By: dmgreen
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72000
The file was modifiedllvm/test/CodeGen/Thumb2/emit-unwinding.ll
The file was modifiedllvm/lib/Target/ARM/ARMAsmPrinter.cpp
Commit 987eb8e26ccf73180b3b53b8a38d87e3e6489326 by spatel
[InstCombine] propagate sign argument through nested copysigns
This is another optimization suggested in PR44153:
https://bugs.llvm.org/show_bug.cgi?id=44153
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
The file was modifiedllvm/test/Transforms/InstCombine/copysign.ll
Commit 1247865fe024e073c206b3803096df8477a60bab by arsenm2
AMDGPU/GlobalISel: Select llvm.amdgcn.fmad.ftz
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmad.ftz.mir
Commit 98f72a5107ce781a8ec93c524c3fdb08c241f0e5 by petar.avramovic
[MIPS GlobalISel] Select bitreverse. Recommit
G_BITREVERSE is generated from llvm.bitreverse.<type> intrinsics, clang
genrates these intrinsics from __builtin_bitreverse32 and
__builtin_bitreverse64. Add lower and narrowscalar for G_BITREVERSE.
Lower G_BITREVERSE on MIPS32.
Recommit notes: Introduce temporary variables in order to make sure
instructions get inserted into MachineFunction in same order regardless
of compiler used to build llvm.
Differential Revision: https://reviews.llvm.org/D71363
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
The file was modifiedllvm/lib/Target/Mips/MipsLegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitreverse.mir
The file was addedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitreverse.ll
The file was addedllvm/test/CodeGen/Mips/GlobalISel/legalizer/bitreverse.mir
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
Commit ee3eebba0d30f9a231bb10e59f3778c72065db22 by spatel
[InstCombine] remove stale comment on test; NFC
The file was modifiedllvm/test/Transforms/InstCombine/copysign.ll
Commit 03b9f0a5e19aa68fb0a82d80e409333db7ee511c by maskray
Ignore "no-frame-pointer-elim" and "no-frame-pointer-elim-non-leaf" in
favor of "frame-pointer"
D56351 (included in LLVM 8.0.0) introduced "frame-pointer".  All tests
which use "no-frame-pointer-elim" or "no-frame-pointer-elim-non-leaf"
have been migrated to use "frame-pointer".
Implement UpgradeFramePointerAttributes to upgrade the two obsoleted
function attributes for bitcode. Their semantics are ignored.
Differential Revision: https://reviews.llvm.org/D71863
The file was modifiedllvm/lib/IR/AutoUpgrade.cpp
The file was modifiedllvm/lib/Bitcode/Reader/BitcodeReader.cpp
The file was addedllvm/test/Bitcode/upgrade-frame-pointer.ll
The file was modifiedllvm/docs/ReleaseNotes.rst
The file was modifiedllvm/include/llvm/IR/AutoUpgrade.h
The file was modifiedllvm/lib/CodeGen/TargetOptionsImpl.cpp
Commit 48e0e68edb3e8e1cd12c6ff9847cf917d55d9a1d by arsenm2
AMDGPU/GlobalISel: Re-use MRI available in selector
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
Commit 0c5bee8fdd40bbbad9d3f5cce06785c72632fbd0 by bryan.chan
[test] do not parse ls output for file size; NFCI
Parsing `ls -l` output to obtain the size of a file is unreliable; the
exact output format is not specified, and some user or group names may
contain multiple words, causing `cut -f5 -d' '` to extract an incorrect
value. `wc -c`, on the other hand, is portable, and there are
precendents of its use in test cases.
The file was modifiedllvm/test/tools/yaml2obj/ELF/custom-null-section.yaml
The file was modifiedllvm/test/tools/llvm-profdata/show-prof-size.test
Commit 47a2fd2df4f4874c28823654be500c3aba93f768 by craig.topper
[X86] Add X86ISD::PCMPGT to
SimplifyMultipleUseDemandedBitsForTargetNode.
If only the sign bit is demanded, and the LHS is all zeroes, then we can
bypass the PCMPGT.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/sadd_sat.ll
The file was modifiedllvm/test/CodeGen/X86/sadd_sat_vec.ll
The file was modifiedllvm/test/CodeGen/X86/ssub_sat.ll
The file was modifiedllvm/test/CodeGen/X86/ssub_sat_vec.ll
Commit 94d08feaeff3591a36ed548ba7c732ddedd6f983 by arsenm2
TableGen: Fix assert on PatFrags with predicate code
This assumed a single pattern if there was a predicate. Relax this a
bit, and allow multiple patterns as long as they have the same class.
This was only broken for the DAG path. GlobalISel seems to have handled
this correctly already.
The file was addedllvm/test/TableGen/predicate-patfags.td
The file was modifiedllvm/utils/TableGen/CodeGenDAGPatterns.cpp
Commit 7fa0bfe7d580e2b96b8d7f5bd0470287857e84cc by arsenm2
AMDGPU/GlobalISel: Select mul24 intrinsics
The file was modifiedllvm/lib/Target/AMDGPU/VOP2Instructions.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mul.u24.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
Commit 4a7aa252a32a94b1bb61b3dc7f027b4a27ae334f by epastor
[X86][AsmParser] re-introduce 'offset' operator
Summary: Amend MS offset operator implementation, to more closely fit
with its MS counterpart:
    1. InlineAsm: evaluate non-local source entities to their (address)
location
   2. Provide a mean with which one may acquire the address of an
assembly label via MS syntax, rather than yielding a memory reference
(i.e. "offset asm_label" and "$asm_label" should be synonymous
   3. address PR32530
Based on http://llvm.org/D37461
Fix broken test where the break appears unrelated.
- Set up appropriate memory-input rewrites for variable references.
- Intel-dialect assembly printing now correctly handles addresses by
adding "offset".
- Pass offsets as immediate operands (using "r" constraint for offsets
of locals).
Reviewed By: rnk
Differential Revision: https://reviews.llvm.org/D71436
The file was modifiedclang/lib/Sema/SemaStmtAsm.cpp
The file was modifiedllvm/include/llvm/MC/MCParser/MCTargetAsmParser.h
The file was modifiedllvm/test/CodeGen/X86/ms-inline-asm.ll
The file was modifiedllvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
The file was modifiedclang/test/CodeGen/ms-inline-asm.c
The file was modifiedllvm/lib/Target/X86/AsmParser/X86Operand.h
The file was addedllvm/test/CodeGen/X86/offset-operator.ll
The file was modifiedclang/test/Parser/ms-inline-asm.c
The file was modifiedllvm/include/llvm/MC/MCParser/MCParsedAsmOperand.h
The file was addedllvm/test/MC/X86/pr32530.s
The file was modifiedclang/test/CodeGen/ms-inline-asm.cpp
The file was modifiedllvm/lib/MC/MCParser/AsmParser.cpp
The file was modifiedclang/test/CodeGen/ms-inline-asm-64.c
The file was modifiedllvm/lib/Target/X86/X86AsmPrinter.cpp
Commit 000c6a5038bc654946b4348e586d685077b06943 by johannes
[OpenMP] Use the OpenMPIRBuilder for `omp cancel`
An `omp cancel parallel` needs to be emitted by the OpenMPIRBuilder if
the `parallel` was emitted by the OpenMPIRBuilder. This patch makes this
possible. The cancel logic is shared with the cancel barriers. Testing
is done via unit tests and the clang cancel_codegen.cpp file once D70290
lands.
Reviewed By: JonChesterfield
Differential Revision: https://reviews.llvm.org/D71948
The file was modifiedllvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
The file was modifiedllvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
The file was modifiedllvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
The file was modifiedllvm/include/llvm/Frontend/OpenMP/OMPKinds.def
Commit 10fedd94b4326225de4a8a1fc53594cebd501246 by johannes
[OpenMP] Use the OpenMPIRBuilder for `omp parallel`
This allows to use the OpenMPIRBuilder for parallel regions. Code was
extracted from D61953 and adapted to work with the new version (D70109).
All but one feature should be supported. An update of this patch will
provide test coverage and privatization other than shared.
Reviewed By: fghanim
Differential Revision: https://reviews.llvm.org/D70290
The file was modifiedclang/test/OpenMP/cancel_codegen.cpp
The file was modifiedclang/lib/CodeGen/CGStmtOpenMP.cpp
The file was modifiedclang/test/OpenMP/parallel_codegen.cpp
The file was modifiedllvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
The file was modifiedllvm/include/llvm/Frontend/OpenMP/OMPKinds.def
The file was modifiedllvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
The file was modifiedllvm/lib/Frontend/OpenMP/OMPConstants.cpp
Commit 0bd3cc42485225555a0eb60b91d8c7be22b6fd4a by Jinsong Ji
[PowerPC][docs] Update Embedded PowerPC docs in Compiler Writers Info
page
Summary: Embedded PowerPC are still actively supported, especially
SPE... So update some important references here:
* adding EREF
* adding SPE/VLE ref
Delete deprecated ones into "Other documents..".
Reviewers: #powerpc, jhibbits, hfinkel
Reviewed By: #powerpc, jhibbits
Subscribers: wuzish, merge_guards_bot, nemanjai, shchenz, steven.zhang,
llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72008
The file was modifiedllvm/docs/CompilerWriterInfo.rst
Commit bc48af8c575abdd283d391194fa40d1419df5efe by jonathanchesterfield
[libomptarget][nfc] Change unintentional target_impl prefix to kmpc_impl
The file was modifiedopenmp/libomptarget/deviceRTLs/amdgcn/src/target_impl.h
The file was modifiedopenmp/libomptarget/deviceRTLs/nvptx/src/target_impl.h
The file was modifiedopenmp/libomptarget/deviceRTLs/common/src/libcall.cu
Commit 6bd1fcd795994f484e8f974be566edbbbf23927d by johannes
[OpenMP][FIX] Generalize a test check line
The new check line is compatible with the clang code generation check
line as it allows a 64 and 32 bit value.
I hope this makes the llvm-clang-win-x-armv7l buildbot happy.
The file was modifiedclang/test/OpenMP/parallel_codegen.cpp
Commit 07be32961a694670885626e72faca6f0007f14c9 by epastor
Remove a redundant `default:` on an exhaustive switch(enum).
The file was modifiedllvm/lib/Target/X86/X86AsmPrinter.cpp
Commit 8b23b2bbd9622c5f079a71c7078d167052f6a70c by craig.topper
[CodeGen] Use CreateFNeg in buildFMulAdd
We have an fneg instruction now and should use it instead of the fsub
-0.0 idiom. Looks like we had no test that showed that we handled the
negation cases here so I've added new tests.
Differential Revision: https://reviews.llvm.org/D72010
The file was modifiedclang/lib/CodeGen/CGExprScalar.cpp
The file was modifiedclang/test/CodeGen/fp-contract-pragma.cpp
Commit 70f8dd4cf604b2be3488895ef0d261154c1c1124 by craig.topper
[CodeGen] Use IRBuilder::CreateFNeg for __builtin_conj
This replaces the fsub -0.0 idiom with an fneg instruction. We didn't
see to have a test that showed the current codegen. Just some tests for
constant folding and a test that was only checking the declare lines for
libcalls. The latter just checked that we did not have a declare for
@conj when using __builtin_conj.
Differential Revision: https://reviews.llvm.org/D72012
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was addedclang/test/CodeGen/complex-builtins-2.c
Commit 6185dc0eb3ad35e1f85f2ab1038ca978563099f4 by craig.topper
[X86] Add test case for PR44412. NFC
The file was addedllvm/test/CodeGen/X86/pr44412.ll