SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [PowerPC][NFC] Fix clang-tidy warning (details)
  2. Revert "[InstCombine] Fix infinite loop due to bitcast <-> phi (details)
  3. [Attributor][Fix] Avoid leaking memory after D68765 (details)
  4. Match code following lambdas when ignoring invisible nodes (details)
  5. Unnest struct in Matcher implementation (details)
  6. Implement additional traverse() overloads (details)
  7. [InstCombine] add/adjust tests for masked bit; NFC (details)
  8. [InstCombine] fold zext of masked bit set/clear (details)
  9. [mlir] Make code blocks more consistent (details)
  10. [CodeGen] Emit conj/conjf/confjl libcalls as fneg instructions if (details)
  11. [X86] Add test case for opposite branch condition for PR44412. NFC (details)
  12. [mlir][docs] Remove redundant path prefix (details)
  13. [OPENMP]Emit artificial threprivate vars as threadlocal, if possible. (details)
  14. [amdgpu] Fix scoreboard updating on `s_waitcnt_vscnt`. (details)
  15. Revert "[Diagnostic] Add ftabstop to -Wmisleading-indentation" (details)
  16. AMDGPU: Precommit test showing extra instructions are introduced (details)
Commit fcbf05bbdccc8a32f6a80316ea1c13be7e7eeae2 by Jinsong Ji
[PowerPC][NFC] Fix clang-tidy warning
Reported by
https://results.llvm-merge-guard.org/amd64_debian_testing_clang8-726/clang-tidy.txt
/mnt/disks/ssd0/agent/workspace/amd64_debian_testing_clang8/llvm/lib/Target/PowerPC/PPCISelLowering.cpp:11672:10:
warning: invalid case style for variable 'isEQ'
[readability-identifier-naming]
   bool isEQ = (MI.getOpcode() == PPC::ANDI_rec_1_EQ_BIT ||
        ^~~~
        IsEq
/mnt/disks/ssd0/agent/workspace/amd64_debian_testing_clang8/llvm/lib/Target/PowerPC/PPCISelLowering.cpp:11679:14:
warning: invalid case style for variable 'dl'
[readability-identifier-naming]
   DebugLoc dl = MI.getDebugLoc();
            ^~
            Dl
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
Commit 7adb5c2aca8047ae184a96869e3cfcb034fbac39 by nikita.ppv
Revert "[InstCombine] Fix infinite loop due to bitcast <-> phi
transforms"
This reverts commit 27a0795943fee0f30b995fe5165428afc2dfd402.
Seems to break test-suite.
The file was removedllvm/test/Transforms/InstCombine/pr44245.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
Commit df3b56c90544b17e645bcb1799ce60e3ae1d5c6d by johannes
[Attributor][Fix] Avoid leaking memory after D68765
The file was modifiedllvm/include/llvm/Transforms/IPO/Attributor.h
Commit d89c4cb938070a6de11e624984e5bd0e989fb334 by steveire
Match code following lambdas when ignoring invisible nodes
Reviewers: aaron.ballman
Subscribers: cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D71976
The file was modifiedclang/lib/ASTMatchers/ASTMatchFinder.cpp
The file was modifiedclang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
Commit 06fdbf3dafb76e54ea76e0eb5f690bc3d6773023 by steveire
Unnest struct in Matcher implementation
This allows implementation of the traverse() matcher to surround
matchers like unless().
The file was modifiedclang/include/clang/ASTMatchers/ASTMatchersInternal.h
Commit 69bb99914f35b887e949b72feafc5f41ee0db6e1 by steveire
Implement additional traverse() overloads
Summary: These overloads make it possible to wrap unless(), anyOf(),
has() etc with the traverse matcher.
Reviewers: aaron.ballman
Subscribers: cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D71977
The file was modifiedclang/include/clang/ASTMatchers/ASTMatchers.h
The file was modifiedclang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
The file was modifiedclang/include/clang/ASTMatchers/ASTMatchersInternal.h
Commit eb5c026ef0bc48207edaeda8115b832be631652d by spatel
[InstCombine] add/adjust tests for masked bit; NFC
The file was modifiedllvm/test/Transforms/InstCombine/zext.ll
Commit a041c4ec6f7aa659b235cb67e9231a05e0a33b7d by spatel
[InstCombine] fold zext of masked bit set/clear
This does not solve PR17101, but it is one of the underlying diffs noted
here: https://bugs.llvm.org/show_bug.cgi?id=17101#c8
We could ease the one-use checks for the 'clear'
(no 'not' op) half of the transform, but I do not know if that asymmetry
would make things better or worse.
Proofs: https://rise4fun.com/Alive/uVB
  Name: masked bit set
%sh1 = shl i32 1, %y
%and = and i32 %sh1, %x
%cmp = icmp ne i32 %and, 0
%r = zext i1 %cmp to i32
=>
%s = lshr i32 %x, %y
%r = and i32 %s, 1
  Name: masked bit clear
%sh1 = shl i32 1, %y
%and = and i32 %sh1, %x
%cmp = icmp eq i32 %and, 0
%r = zext i1 %cmp to i32
=>
%xn = xor i32 %x, -1
%s = lshr i32 %xn, %y
%r = and i32 %s, 1
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
The file was modifiedllvm/test/Transforms/InstCombine/zext.ll
Commit 430bba2a0f39b543e66119761d1526d037229936 by jpienaar
[mlir] Make code blocks more consistent
Use the same form specification for the same type of code.
The file was modifiedmlir/docs/Tutorials/Toy/Ch-4.md
The file was modifiedmlir/docs/RationaleSimplifiedPolyhedralForm.md
The file was modifiedmlir/docs/Tutorials/Toy/Ch-1.md
The file was modifiedmlir/docs/Tutorials/Toy/Ch-6.md
The file was modifiedmlir/docs/ConversionToLLVMDialect.md
The file was modifiedmlir/lib/Support/CMakeLists.txt
The file was modifiedmlir/docs/DeclarativeRewrites.md
The file was modifiedmlir/docs/Tutorials/Toy/Ch-2.md
The file was modifiedmlir/docs/Tutorials/Toy/Ch-3.md
Commit 5e5a1d27909626169c15b8f63e10d22fcbdf88d9 by craig.topper
[CodeGen] Emit conj/conjf/confjl libcalls as fneg instructions if
possible.
We already recognize the __builtin versions of these, might as well
recognize the libcall version.
Differential Revision: https://reviews.llvm.org/D72028
The file was addedclang/test/CodeGen/complex-libcalls-2.c
The file was modifiedclang/test/CodeGen/complex-libcalls.c
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
Commit 73855e43009bdd433c648e7102f122365e50e398 by craig.topper
[X86] Add test case for opposite branch condition for PR44412. NFC
The file was modifiedllvm/test/CodeGen/X86/pr44412.ll
Commit 7544cb8807b2ecb2f5186ab18d0ffa865a493a47 by jpienaar
[mlir][docs] Remove redundant path prefix
./ is not needed.
The file was modifiedmlir/docs/Tutorials/Toy/Ch-5.md
Commit 8be5a0fe12bb9114bb82986b1dcb9205699aa085 by a.bataev
[OPENMP]Emit artificial threprivate vars as threadlocal, if possible.
It may improve performance for declare reduction constructs.
The file was modifiedclang/test/OpenMP/master_taskloop_reduction_codegen.cpp
The file was modifiedclang/test/OpenMP/master_taskloop_simd_reduction_codegen.cpp
The file was modifiedclang/test/OpenMP/parallel_master_taskloop_simd_reduction_codegen.cpp
The file was modifiedclang/test/OpenMP/parallel_master_taskloop_reduction_codegen.cpp
The file was modifiedclang/test/OpenMP/taskloop_reduction_codegen.cpp
The file was modifiedclang/test/OpenMP/taskloop_simd_reduction_codegen.cpp
The file was modifiedclang/lib/CodeGen/CGOpenMPRuntime.cpp
Commit 79d401905fcf519da732b33ee9dffd18f2da3b10 by michael.hliao
[amdgpu] Fix scoreboard updating on `s_waitcnt_vscnt`.
Summary: - Other counters are accidentally cleared.
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl,
dstuttard, tpr, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D71866
The file was modifiedllvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
The file was addedllvm/test/CodeGen/AMDGPU/waitcnt-vscnt.mir
Commit b65ca8e5db6fde6ef5948136b8f576eb6d7f707f by martin
Revert "[Diagnostic] Add ftabstop to -Wmisleading-indentation"
This reverts commit b47b35ff51b355a446483777155290541ab64fae.
This caused failed asserts (Assertion `FIDAndOffset.second > ColNo &&
"Column number smaller than file offset?"' failed.) on a source file
with a single line containing
"int main (void) { for( int i = 0; i < 9; i++ ); return 0; }".
The file was modifiedclang/lib/Parse/ParseStmt.cpp
The file was modifiedclang/test/Parser/warn-misleading-indentation.cpp
Commit 64cf26548a4cef7745ebc385ac6a2d280bcaf6fe by arsenm2
AMDGPU: Precommit test showing extra instructions are introduced
The file was addedllvm/test/CodeGen/AMDGPU/fneg-fold-legalize-dag-increase-insts.ll