SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. AMDGPU/GlobalISel: Assume vcc phis for any vcc input (details)
  2. AMDGPU/GlobalISel: Legalize more odd sized loads (details)
  3. AMDGPU/GlobalISel: Refine SMRD selection rules (details)
  4. GlobalISel: Define G_READCYCLECOUNTER (details)
  5. [SCEV] Remove unused ScalarEvolutionExpander.h includes (NFC). (details)
  6. [SCEV] Move ScalarEvolutionExpander.cpp to Transforms/Utils (NFC). (details)
  7. Revert "[SCEV] Move ScalarEvolutionExpander.cpp to Transforms/Utils (details)
  8. GlobalISel: Scalarize all division operations (details)
  9. [ELF] Drop const qualifier to fix -Wrange-loop-analysis. NFC (details)
  10. [LegalizeVectorOps] Split most of ExpandStrictFPOp into a separate (details)
  11. [TargetLowering] In expandFP_TO_UINT, add proper extend or truncate for (details)
  12. [LegalizeVectorOps][X86] Enable expansion of vector fp_to_uint in (details)
Commit 5fb59f16e219162f98c78bf938ad2e6bb563567c by arsenm2
AMDGPU/GlobalISel: Assume vcc phis for any vcc input
This produces more intelligible looking results, more comparabble to the
DAG output in the simplest cases. This is probably wrong in complex
control flow, but RegBankSelect doesn't attempt analyzing if this is on
a masked path for selecting the bank yet.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
Commit d9b5063b25a7d751b4e3dcbb22565fd0d9c285ec by arsenm2
AMDGPU/GlobalISel: Legalize more odd sized loads
The attempts to widen sufficently aligned, odd sized loads wasn't
consistently applied.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
Commit 4e972224c476e05af445130e2b208e9819d220a5 by arsenm2
AMDGPU/GlobalISel: Refine SMRD selection rules
Fix selecting these for volatile global loads, and ensure the loads are
constant enough.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
Commit 1f950ced5046264655f0d37b4b94dc0ae0461cfc by arsenm2
GlobalISel: Define G_READCYCLECOUNTER
The file was modifiedllvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
The file was modifiedllvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
The file was modifiedllvm/include/llvm/Target/GenericOpcodes.td
The file was modifiedllvm/include/llvm/Support/TargetOpcodes.def
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
Commit 99f74a64a2dd75b91dc0dbd1f9a6298a1c21fd64 by flo
[SCEV] Remove unused ScalarEvolutionExpander.h includes (NFC).
The file was modifiedllvm/lib/Analysis/IVDescriptors.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCCTRLoops.cpp
The file was modifiedllvm/lib/Transforms/Utils/LoopUtils.cpp
The file was modifiedllvm/lib/Transforms/Utils/LoopUnrollAndJam.cpp
Commit 51ef53f3bd23559203fe9af82ff2facbfedc1db3 by flo
[SCEV] Move ScalarEvolutionExpander.cpp to Transforms/Utils (NFC).
SCEVExpander modifies the underlying function so it is more suitable in
Transforms/Utils, rather than Analysis. This allows using other
transform utils in SCEVExpander.
Reviewers: sanjoy.google, efriedma, reames
Reviewed By: sanjoy.google
Differential Revision: https://reviews.llvm.org/D71537
The file was modifiedllvm/lib/Transforms/Scalar/LoopDataPrefetch.cpp
The file was modifiedllvm/unittests/Analysis/ScalarEvolutionTest.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
The file was modifiedllvm/lib/CodeGen/HardwareLoops.cpp
The file was modifiedllvm/lib/Transforms/Utils/LoopUnrollRuntime.cpp
The file was addedllvm/unittests/Transforms/Utils/ScalarEvolutionExpanderTest.cpp
The file was modifiedllvm/lib/Analysis/CMakeLists.txt
The file was modifiedllvm/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp
The file was removedllvm/include/llvm/Analysis/ScalarEvolutionExpander.h
The file was modifiedllvm/lib/Transforms/Scalar/IndVarSimplify.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
The file was modifiedllvm/lib/Target/ARM/MVETailPredication.cpp
The file was modifiedllvm/unittests/Transforms/Utils/CodeMoverUtilsTest.cpp
The file was modifiedllvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
The file was removedllvm/lib/Analysis/ScalarEvolutionExpander.cpp
The file was modifiedllvm/lib/Transforms/Scalar/LoopRerollPass.cpp
The file was addedllvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
The file was modifiedllvm/lib/Transforms/Utils/CMakeLists.txt
The file was modifiedllvm/unittests/Transforms/Utils/CMakeLists.txt
The file was modifiedllvm/lib/Analysis/LoopAccessAnalysis.cpp
The file was addedllvm/include/llvm/Transforms/Utils/ScalarEvolutionExpander.h
The file was modifiedllvm/lib/Transforms/Scalar/LoopPredication.cpp
The file was modifiedllvm/lib/Transforms/Utils/LoopVersioning.cpp
The file was modifiedllvm/lib/Transforms/Utils/SimplifyIndVar.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was modifiedllvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
The file was modifiedllvm/lib/Transforms/Scalar/LoopLoadElimination.cpp
Commit b8a3c34eee06c17ae42dc00218ba4f0c815e9a2c by flo
Revert "[SCEV] Move ScalarEvolutionExpander.cpp to Transforms/Utils
(NFC)."
This reverts commit 51ef53f3bd23559203fe9af82ff2facbfedc1db3, as it
breaks some bots.
The file was modifiedllvm/unittests/Analysis/ScalarEvolutionTest.cpp
The file was modifiedllvm/lib/Transforms/Scalar/IndVarSimplify.cpp
The file was modifiedllvm/lib/CodeGen/HardwareLoops.cpp
The file was modifiedllvm/lib/Transforms/Scalar/LoopLoadElimination.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
The file was addedllvm/lib/Analysis/ScalarEvolutionExpander.cpp
The file was modifiedllvm/unittests/Transforms/Utils/CodeMoverUtilsTest.cpp
The file was modifiedllvm/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp
The file was modifiedllvm/lib/Transforms/Utils/CMakeLists.txt
The file was modifiedllvm/lib/Target/ARM/MVETailPredication.cpp
The file was modifiedllvm/lib/Analysis/LoopAccessAnalysis.cpp
The file was removedllvm/unittests/Transforms/Utils/ScalarEvolutionExpanderTest.cpp
The file was modifiedllvm/lib/Transforms/Scalar/LoopDataPrefetch.cpp
The file was modifiedllvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
The file was modifiedllvm/lib/Transforms/Scalar/LoopRerollPass.cpp
The file was modifiedllvm/lib/Transforms/Utils/SimplifyIndVar.cpp
The file was modifiedllvm/lib/Transforms/Utils/LoopUnrollRuntime.cpp
The file was modifiedllvm/lib/Analysis/CMakeLists.txt
The file was modifiedllvm/lib/Transforms/Utils/LoopVersioning.cpp
The file was modifiedllvm/lib/Transforms/Scalar/LoopPredication.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
The file was modifiedllvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
The file was removedllvm/include/llvm/Transforms/Utils/ScalarEvolutionExpander.h
The file was addedllvm/include/llvm/Analysis/ScalarEvolutionExpander.h
The file was removedllvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was modifiedllvm/unittests/Transforms/Utils/CMakeLists.txt
Commit d12f2a2998450213f065ee3c9b21275416cb7f90 by arsenm2
GlobalISel: Scalarize all division operations
This only handled G_SDIV, but they all are trivially scalarizable.
Also define placeholder AMDGPU division legalizer rules.
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-urem.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-srem.mir
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
Commit 085898d469ab782f0a26f119b109aa8eb5d37745 by maskray
[ELF] Drop const qualifier to fix -Wrange-loop-analysis. NFC
``` lld/ELF/Relocations.cpp:1622:56: warning: loop variable 'ts' of type
'const std::pair<ThunkSection *, uint32_t>' (aka 'const
pair<lld::elf::ThunkSection *, unsigned int>') creates a copy from type
'const std::pair<ThunkSection *, uint32_t>' [-Wrange-loop-analysis]
       for (const std::pair<ThunkSection *, uint32_t> ts :
isd->thunkSections)
```
Drop const qualifier to fix -Wrange-loop-analysis. We can make
-Wrange-loop-analysis warnings (DiagnoseForRangeConstVariableCopies) on
`const A` more permissive on more types (e.g. POD -> trivially
copyable), unfortunately it will not make std::pair good, because
`constexpr pair& operator=(const pair& p);` is unfortunately
user-defined.
Reviewed By: Mordante
Differential Revision: https://reviews.llvm.org/D72211
The file was modifiedlld/ELF/Relocations.cpp
Commit 285d5e6b8b1ecc70c25468b6c7458d2adadeddf3 by craig.topper
[LegalizeVectorOps] Split most of ExpandStrictFPOp into a separate
UnrollStrictFPOp method. Call that method from ExpandUINT_TO_FLOAT.
ExpandStrictFPOp calls ExpandUINT_TO_FLOAT. Previously,
ExpandUINT_TO_FLOAT returned SDValue() if it wasn't able to handle and
needed to unroll. Then ExpandStrictFPOp would detect his SDValue() and
do the unroll.
After this change, ExpandUINT_TO_FLOAT will directly call
UnrollStrictFPOp and return the unrolled result.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
Commit 16a67d252c72332423bae6597a0685248fc3501f by craig.topper
[TargetLowering] In expandFP_TO_UINT, add proper extend or truncate for
the condition to feed the DstVT select.
Previously, for vectors we created a vselect with a condition that
didn't match what the target wanted according to getSetCCResultType.
To make up for this, X86 had a special DAG combine to detect if the
condition was all sign bits and then insert its own truncate or extend.
By adding the extend/truncate here explicitly we can avoid that.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Commit 4e37d60f2a6b66ce95a039e6c929e7e38af30cd1 by craig.topper
[LegalizeVectorOps][X86] Enable expansion of vector fp_to_uint in
LegalizeVectorOps to avoid scalarization.
The code here isn't great in all caess. Particularly v4f64->v4i32 on
64-bit AVX targets. But there is some improvement in some
configurations.
There's definitely some issues with computeNumSignBits with
X86ISD::STRICT_FCMP. As well as not being able to propagate sign bits
through merge_values nodes that get created during custom legalization.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
The file was modifiedllvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll
The file was modifiedllvm/test/CodeGen/X86/vec-strict-fptoint-128.ll
The file was modifiedllvm/test/CodeGen/X86/vec-strict-fptoint-256.ll