SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [ARM,MVE] Generate the right instruction for vmaxnmq_m_f16. (details)
  2. [ARM,MVE] Support -ve offsets in gather-load intrinsics. (details)
  3. [ARM,MVE] Fix many signedness errors in MVE intrinsics. (details)
  4. Fix "use of uninitialized variable" static analyzer warning. NFCI. (details)
  5. Fix "use of uninitialized variable" static analyzer warnings. NFCI. (details)
  6. [AMDGPU] Fix "use of uninitialized variable" static analyzer warning. (details)
  7. [NFC] Fixes -Wrange-loop-analysis warnings (details)
  8. Adds -Wrange-loop-analysis to -Wall (details)
  9. [AIX] Use csect reference for function address constants (details)
  10. [ARM] Use correct TRAP opcode for thumb in FastISel (details)
  11. [ARM] Use the correct opcodes for Thumb2 segmented stack frame lowering (details)
  12. [llvm-libc] Fix missing virtual destructor (details)
  13. [AIX] Use csect reference for function address constants (details)
  14. [lldb/CMake] Autodetect Python dependency (details)
  15. [lldb/Test] Temporarily skip TestFoundationDisassembly on the ASan bot. (details)
  16. [clang-tidy] new check: bugprone-signed-char-misuse (details)
  17. [gn build] Port 350da402ef6 (details)
  18. [llvm-readelf] Print EI_ABIVERSION as decimal instead of hexadecimal (details)
  19. [lldb/Test] Move @skipIfAsan from test class to test methods. (details)
  20. Make check-llvm run 50% faster on macOS, 18% faster on Windows. (details)
  21. [CMake] Add $ORIGIN/../../../../lib to rpath if BUILD_SHARED_LIBS or (details)
  22. [lldb/CMake] Only set PYTHON_HOME on Windows (details)
  23. [lldb/Docs] Fix capitalization typo. (details)
  24. [libc] Move all tests to a top level `test` directory. (details)
  25. [lld] Fix trivial typos in comments (details)
  26. [PowerPC][LoopVectorize] Extend getRegisterClassForType to consider (details)
  27. [X86] Fix an 8 bit testb being selected when folding a volatile i32 load (details)
  28. Lower TAGPstack with negative offset to SUBG. (details)
  29. [OpenMP] Fix incorrect property of __has_attribute() macro (details)
  30. [x86] add tests for concat self + shuffle; NFC (details)
  31. [NFC] Test commit, whitespace change (details)
  32. [NFC] Test commit, revert whitespace change (details)
  33. [OPENMP50]Support lastprivate conditional updates in inc/dec unary ops. (details)
  34. [X86] Rename vec-strict-*-cmp.ll to vec-strict-cmp-*.ll to match other (details)
  35. [LegalizeTypes] Add widening support for STRICT_FSETCC/FSETCCS (details)
  36. [lldb/Docs] Describe optional dependencies on build page. (details)
  37. [X86] Improve v4i32->v4f64 uint_to_fp for AVX1/AVX2 targets. (details)
  38. llc/MIR: Fix setFunctionAttributes for MIR functions (details)
  39. AMDGPU: Use ImmLeaf for inline immediate predicates (details)
  40. AMDGPU: Use ImmLeaf (details)
  41. AMDGPU: Fix legalizing f16 fpow (details)
  42. GlobalISel: Start adding computeNumSignBits to GISelKnownBits (details)
  43. GlobalISel: Correct result type for G_FCMP in lowerFPTOUI (details)
  44. GlobalISel: Fix unsupported legalize action (details)
  45. [Diagnostic] make Wmisleading-indendation not warn about labels (details)
  46. [PowerPC][NFC] Rename record instructions to use _rec suffix instead of (details)
  47. [FileCheck] Remove FileCheck prefix in API (details)
  48. Don't rely on 'l'(ell) modifiers to indicate a label reference (details)
  49. [CMake] Pass symlink dependency to add_llvm_install_targets explicitly (details)
  50. [NSArray] Remove a very old and deprecated formatter. (details)
  51. [msan] Check qsort input. (details)
  52. [X86] Move an enum definition into a header to simplify future patches (details)
  53. Change the patterns to include the prefix '= ' so we don't pass (details)
  54. GlobalISel: Implement lower for G_INTRINSIC_ROUND (details)
  55. TableGen/GlobalISel: Handle default operands that are used (details)
  56. AMDGPU/GlobalISel: Replace handling of boolean values (details)
  57. AMDGPU/GlobalISel: Select G_UADDE/G_USUBE (details)
  58. Use FileCheck instead of grep (details)
  59. Add Triple::isX86() (details)
  60. [NFC] Fixes -Wrange-loop-analysis warnings (details)
  61. [msan] Fix underflow in qsort interceptor. (details)
  62. [CodeGen][ObjC] Push the properties of a protocol before pushing the (details)
  63. AMDGPU/GlobalISel: Legalize G_READCYCLECOUNTER (details)
  64. [WebAssembly] Fix landingpad-only case in Emscripten EH (details)
  65. AMDGPU: Use default operands for clamp/omod (details)
  66. Always deduce the lengths of contained parameter packs when deducing a (details)
  67. AMDGPU: Select llvm.amdgcn.interp.p2.f16 directly (details)
  68. AMDGPU: Add run line to int_to_fp tests (details)
  69. [NFC][Test] Add a test to verify the DAGCombine of fma (details)
  70. [mlir][Linalg] Add a linalg.reshape op (details)
  71. AMDGPU/GlobalISel: Fix unused variable warning in release (details)
  72. [MC] Add parameter `Address` to MCInstPrinter::printInst (details)
Commit b99ef32d041c992d0cb192bdee3e16b9a56de3a9 by simon.tatham
[ARM,MVE] Generate the right instruction for vmaxnmq_m_f16.
Summary: Due to a copy-paste error in the isel patterns, the predicated
version of this intrinsic was expanding to the `VMAXNMT.F32` instruction
instead of `VMAXNMT.F16`. Similarly for vminnm.
Reviewers: dmgreen, miyuki, MarkMurrayARM
Reviewed By: dmgreen
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72269
The file was modifiedllvm/test/CodeGen/Thumb2/mve-intrinsics/vminnmq.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-intrinsics/vmaxnmq.ll
The file was modifiedllvm/lib/Target/ARM/ARMInstrMVE.td
Commit 4978296cd8e4d10724cfa41f0308d256c0fd490c by simon.tatham
[ARM,MVE] Support -ve offsets in gather-load intrinsics.
Summary: The ACLE intrinsics with `gather_base` or `scatter_base` in the
name are wrappers on the MVE load/store instructions that take a vector
of base addresses and an immediate offset. The immediate offset can be
up to 127 times the alignment unit, and it can be positive or negative.
At the MC layer, we got that right. But in the Sema error checking for
the wrapping intrinsics, the offset was erroneously constrained to be
positive.
To fix this I've adjusted the `imm_mem7bit` class in the Tablegen that
defines the intrinsics. But that causes integer literals like
`0xfffffffffffffe04` to appear in the autogenerated calls to
`SemaBuiltinConstantArgRange`, which provokes a compiler warning because
that's out of the non-overflowing range of an `int64_t`. So I've also
tweaked `MveEmitter` to emit that as `-0x1fc` instead.
Updated the tests of the Sema checks themselves, and also adjusted a
random sample of the CodeGen tests to actually use negative offsets and
prove they get all the way through code generation without causing a
crash.
Reviewers: dmgreen, miyuki, MarkMurrayARM
Reviewed By: dmgreen
Subscribers: kristof.beyls, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D72268
The file was modifiedclang/utils/TableGen/MveEmitter.cpp
The file was modifiedclang/test/Sema/arm-mve-immediates.c
The file was modifiedclang/include/clang/Basic/arm_mve_defs.td
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c
The file was modifiedllvm/test/CodeGen/Thumb2/mve-intrinsics/scatter-gather.ll
Commit 34817e04feeb00dcd0515e5810218587438bd5a8 by simon.tatham
[ARM,MVE] Fix many signedness errors in MVE intrinsics.
Summary: Running an end-to-end test last week I noticed that a lot of
the ACLE intrinsics that operate differently on vectors of signed and
unsigned integers were ending up generating the signed version of the
instruction unconditionally. This is because the IR intrinsics had no
way to distinguish signed from unsigned: the LLVM type system just calls
them both `v8i16` (or whatever), so you need either separate intrinsics
for signed and unsigned, or a flag parameter that tells ISel which one
to choose.
This patch fixes all the problems of that kind that I've noticed, by
adding an i32 flag parameter to many of the IR intrinsics which is set
to 1 for unsigned (matching the existing practice in cases where we got
it right), and conditioning all the isel patterns on that flag. So the
fundamental change is in `IntrinsicsARM.td`, changing the low-level IR
intrinsics API; there are knock-on changes in
`arm_mve.td` (adjusting code gen for the ACLE intrinsics to use the
modified API) and in `ARMInstrMVE.td` (adjusting isel to expect the new
unsigned flags). The rest of this patch is boringly updating tests.
Reviewers: dmgreen, miyuki, MarkMurrayARM
Reviewed By: dmgreen
Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D72270
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vqaddq.c
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vqsubq.c
The file was modifiedllvm/test/CodeGen/Thumb2/mve-intrinsics/vhsubq.ll
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vhsubq.c
The file was modifiedllvm/test/CodeGen/Thumb2/mve-intrinsics/vrhaddq.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-intrinsics/vminq.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-intrinsics/vmulltq.ll
The file was modifiedclang/include/clang/Basic/arm_mve.td
The file was modifiedllvm/test/CodeGen/Thumb2/mve-intrinsics/vmaxq.ll
The file was modifiedllvm/lib/Target/ARM/ARMInstrMVE.td
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vhaddq.c
The file was modifiedllvm/include/llvm/IR/IntrinsicsARM.td
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vabdq.c
The file was modifiedllvm/test/CodeGen/Thumb2/mve-intrinsics/vhaddq.ll
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c
The file was modifiedllvm/test/CodeGen/Thumb2/mve-intrinsics/vqsubq.ll
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vminnmq.c
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vmullbq.c
The file was modifiedllvm/test/CodeGen/Thumb2/mve-intrinsics/vrmulhq.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-intrinsics/vminnmq.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-intrinsics/vmullbq.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-intrinsics/vqaddq.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-intrinsics/vmaxnmq.ll
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vmaxq.c
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vminq.c
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vmulltq.c
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vmulhq.c
The file was modifiedllvm/test/CodeGen/Thumb2/mve-intrinsics/vabdq.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-intrinsics/vmulhq.ll
Commit ea5abf14530634d05b9d1dc6d5d7d5f7934f0ea3 by llvm-dev
Fix "use of uninitialized variable" static analyzer warning. NFCI.
The file was modifiedllvm/lib/CodeGen/LiveDebugVariables.cpp
Commit 5bcc747393be963620d152e1637b0d2ca79bd3c2 by llvm-dev
Fix "use of uninitialized variable" static analyzer warnings. NFCI.
Add "unreachable" default cases like we do for the other switch()s in
X86MCInstLower::Lower
The file was modifiedllvm/lib/Target/X86/X86MCInstLower.cpp
Commit ea2c159f966be363d5c19df8d116d471604f7db5 by llvm-dev
[AMDGPU] Fix "use of uninitialized variable" static analyzer warning.
NFCI.
Add "unreachable" default case to
AMDGPUTargetStreamer::getArchNameFromElfMach
The file was modifiedllvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
Commit 1d549cff48cd52b9967c3a70eeb61abf86444ac3 by koraq
[NFC] Fixes -Wrange-loop-analysis warnings
This avoids new warnings due to D68912 adds -Wrange-loop-analysis to
-Wall.
Differential Revision: https://reviews.llvm.org/D72210
The file was modifiedmlir/lib/Dialect/Linalg/Utils/Utils.cpp
The file was modifiedpolly/lib/Analysis/ScopGraphPrinter.cpp
Commit eec0240f97180ea876193dcfa3cb03cb652d9fe3 by koraq
Adds -Wrange-loop-analysis to -Wall
This makes the range loop warnings part of -Wall.
Fixes PR32823: Warn about accidental coping of data in range based for
Differential Revision: https://reviews.llvm.org/D68912
Recomitted after fixing the warnings it created.
The file was modifiedclang/include/clang/Basic/DiagnosticGroups.td
The file was modifiedclang/test/Misc/warning-wall.c
The file was modifiedclang/test/SemaCXX/warn-range-loop-analysis.cpp
Commit 61b5e727b7ccfca7e0cbb0ed70f9e828cd1514bd by diggerlin
[AIX] Use csect reference for function address constants
SUMMARY: We currently emit a reference for function address constants as
labels; for example:
foo_ptr:
.long foo however, there may be no such label in the case where the
function is undefined. Although the label exists when the function is
defined, we will (to be consistent) also use a csect reference in that
case.
Reviewers: daltenty,hubert.reinterpretcast,jasonliu,Xiangling_L
Subscribers: cebowleratibm, wuzish, nemanjai
Differential Revision: https://reviews.llvm.org/D71144
The file was modifiedllvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
The file was addedllvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
Commit 0eb981b8ce70d07b1b1fb39b969a6fe9509840c1 by david.green
[ARM] Use correct TRAP opcode for thumb in FastISel
We were previously unconditionally using the ARM::TRAP opcode, even
under Thumb. My understanding is that these are essentially the same
thing (they both result in a trap under Thumb), but the ARM::TRAP opcode
is marked as requiring IsARM, so it is more correct to use ARM::tTRAP.
Differential Revision: https://reviews.llvm.org/D72075
The file was modifiedllvm/lib/Target/ARM/ARMFastISel.cpp
The file was modifiedllvm/test/CodeGen/ARM/load_store_opt_clobber_cpsr.mir
Commit f88d52728b9c7f91e4cfec657c0fc60be07d2cb4 by david.green
[ARM] Use the correct opcodes for Thumb2 segmented stack frame lowering
The segmented stack lowering code appears to be using ARM opcodes under
Thumb2. The MRC opcode will be the same for Thumb and ARM, but t2LDR
seems wrong. Either way, using the correct thumb vs arm opcodes is more
correct.
Differential Revision: https://reviews.llvm.org/D72074
The file was modifiedllvm/test/CodeGen/Thumb2/segmented-stacks.ll
The file was modifiedllvm/lib/Target/ARM/ARMFrameLowering.cpp
Commit 3e1f3b164cc0b4be486eebf24cca79c9f9c8c1f7 by gchatelet
[llvm-libc] Fix missing virtual destructor
Summary: This patch adds a virtual destructor to the Command class.
Reviewers: sivachandra
Subscribers: mgorny, MaskRay, libc-commits
Tags: #libc-project
Differential Revision: https://reviews.llvm.org/D72253
The file was addedlibc/utils/HdrGen/Command.cpp
The file was modifiedlibc/utils/HdrGen/Command.h
The file was modifiedlibc/utils/HdrGen/CMakeLists.txt
Commit 83ec9b51ed21b39063f0e0e7b272e66ae57bbcba by diggerlin
[AIX] Use csect reference for function address constants
SUMMARY: We currently emit a reference for function address constants as
labels; for example:
foo_ptr:
.long foo however, there may be no such label in the case where the
function is undefined. Although the label exists when the function is
defined, we will (to be consistent) also use a csect reference in that
case.
Address one comment https://reviews.llvm.org/D71144#inline-653255
Reviewers: daltenty,hubert.reinterpretcast,jasonliu,Xiangling_L
Subscribers: cebowleratibm, wuzish, nemanjai
Differential Revision: https://reviews.llvm.org/D71144
The file was modifiedllvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
Commit b3757f3091d1c718a91f5b06b7364b2af28339fa by Jonas Devlieghere
[lldb/CMake] Autodetect Python dependency
Python was the last remaining "optional" dependency for LLDB. This moves
the code to find Python into FindPythonInterpAndLibs using the same
principles as FindCursesAndPanel.
Differential revision: https://reviews.llvm.org/D72107
The file was addedlldb/cmake/modules/FindPythonInterpAndLibs.cmake
The file was modifiedlldb/cmake/modules/LLDBConfig.cmake
The file was addedlldb/lldb/cmake/modules/FindPythonInterpAndLibs.cmake
Commit 8eba3fbb12fc179959f709aa93f9af8d902fb6d7 by Jonas Devlieghere
[lldb/Test] Temporarily skip TestFoundationDisassembly on the ASan bot.
This test is timing out on the sanitized bot on GreenDragon. Temporarily
disable it to increase the signal-to-noise ration.
The file was modifiedlldb/packages/Python/lldbsuite/test/lang/objc/foundation/TestFoundationDisassembly.py
Commit 350da402ef6b8b2473ff74822e8267bf2716c661 by tamas.zolnai
[clang-tidy] new check: bugprone-signed-char-misuse
Summary: This check searches for signed char -> integer conversions
which might indicate programming error, because of the misinterpretation
of char values. A signed char might store the non-ASCII characters as
negative values. The human programmer probably expects that after an
integer conversion the converted value matches with the character code
(a value from [0..255]), however, the actual value is in
[-128..127] interval.
See also: STR34-C. Cast characters to unsigned char before converting to
larger integer sizes
<https://wiki.sei.cmu.edu/confluence/display/c/STR34-C.+Cast+characters+to+unsigned+char+before+converting+to+larger+integer+sizes>
By now this check is limited to assignment / variable declarations. If
we would catch all signed char -> integer conversion, then it would
produce a lot of findings and also false positives. So I added only this
use case now, but this check can be extended with additional use cases
later. The CERT documentation mentions another use case when the char is
used for array subscript. Next to that a third use case can be the
signed char - unsigned char comparison, which also a use case where
things happen unexpectedly because of conversion to integer.
Reviewers: alexfh, hokein, aaron.ballman
Reviewed By: aaron.ballman
Subscribers: sylvestre.ledru, whisperity, Eugene.Zelenko, mgorny,
xazax.hun, cfe-commits
Tags: #clang, #clang-tools-extra
Differential Revision: https://reviews.llvm.org/D71174
The file was modifiedclang-tools-extra/clang-tidy/bugprone/CMakeLists.txt
The file was addedclang-tools-extra/test/clang-tidy/checkers/bugprone-signed-char-misuse-funsigned-char.cpp
The file was addedclang-tools-extra/test/clang-tidy/checkers/bugprone-signed-char-misuse-with-option.cpp
The file was addedclang-tools-extra/test/clang-tidy/checkers/bugprone-signed-char-misuse.cpp
The file was addedclang-tools-extra/clang-tidy/bugprone/SignedCharMisuseCheck.cpp
The file was modifiedclang-tools-extra/docs/ReleaseNotes.rst
The file was addedclang-tools-extra/test/clang-tidy/checkers/bugprone-signed-char-misuse-fsigned-char.cpp
The file was modifiedclang-tools-extra/docs/clang-tidy/checks/list.rst
The file was addedclang-tools-extra/docs/clang-tidy/checks/bugprone-signed-char-misuse.rst
The file was modifiedclang-tools-extra/clang-tidy/bugprone/BugproneTidyModule.cpp
The file was addedclang-tools-extra/clang-tidy/bugprone/SignedCharMisuseCheck.h
Commit ba4ca37b814a368f66328e9aee5cc479bf28d727 by llvmgnsyncbot
[gn build] Port 350da402ef6
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clang-tidy/bugprone/BUILD.gn
Commit 896b84ac2c70ad69075c2496f8f89247704fff0b by maskray
[llvm-readelf] Print EI_ABIVERSION as decimal instead of hexadecimal
This matches GNU readelf and llvm-readobj.
Reviewed By: jhenderson
Differential Revision: https://reviews.llvm.org/D72234
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp
The file was modifiedllvm/test/tools/llvm-readobj/ELF/file-header-abi-version.test
The file was modifiedlld/test/ELF/mips-n32-rels.s
The file was modifiedllvm/test/tools/llvm-readobj/ELF/gnu-file-headers.test
The file was modifiedllvm/test/tools/llvm-objcopy/ELF/partitions.test
Commit 3abc2927cb2372349fbbc0b62382c85d7d000f2c by Jonas Devlieghere
[lldb/Test] Move @skipIfAsan from test class to test methods.
skipTestIfFn can only be used to decorate a test method.
The file was modifiedlldb/packages/Python/lldbsuite/test/lang/objc/foundation/TestFoundationDisassembly.py
Commit f6544934b94932f1d2231238046f83ba8b083040 by thakis
Make check-llvm run 50% faster on macOS, 18% faster on Windows.
While looking at cycle time graphs of some of my bots, I noticed that
327894859cc made check-llvm noticeably slower on macOS and Windows.
As it turns out, the 5 substitutions added in that change were enough to
cause lit to thrash the build-in cache in re.compile()
(re.sub() is implemented as re.compile().sub()), and apparently
applySubstitutions() is on the cricital path and slow when all regexes
need to compile all the time.
(See `_MAXCACHE = 512` in cpython/Lib/re.py)
Supporting full regexes for lit substitutions seems a bit like overkill,
but for now add a simple unbounded cache to recover the lost
performance.
No intended behavior change.
The file was modifiedllvm/utils/lit/lit/TestRunner.py
Commit bbfebd7b8a671c9649305b8a5f72e93dd1ef60e1 by maskray
[CMake] Add $ORIGIN/../../../../lib to rpath if BUILD_SHARED_LIBS or
LLVM_LINK_LLVM_DYLIB on *nix
Summary: lib/python2.7/dist-packages/lldb/_lldb.so is a symlink to
lib/liblldb.so, which depends on lib/libLLVM*.so
(-DBUILD_SHARED_LIBS=ON) or lib/libLLVM-10git.so
(-DLLVM_LINK_LLVM_DYLIB=ON). Add an additional rpath
`$ORIGIN/../../../../lib` so that _lldb.so can be loaded from Python.
This fixes an import error from
lib/python2.7/dist-packages/lldb/__init__.py
  from . import _lldb
ImportError: libLLVMAArch64CodeGen.so.10git: cannot open shared object
file: No such file or directory
The following configurations will work:
* -DBUILD_SHARED_LIBS=ON
* -DBUILD_SHARED_LIBS=OFF -DLLVM_LINK_LLVM_DYLIB=ON
* -DBUILD_SHARED_LIBS=OFF -DLLVM_LINK_LLVM_DYLIB=ON
-DCLANG_LINK_CLANG_DYLIB=ON
(-DCLANG_LINK_CLANG_DYLIB=ON depends on -DLLVM_LINK_LLVM_DYLIB=ON)
Reviewed By: labath
Differential Revision: https://reviews.llvm.org/D71800
The file was modifiedlldb/source/API/CMakeLists.txt
Commit 8c8ffd461d16681cb1fc764bedfa8b09fde260aa by Jonas Devlieghere
[lldb/CMake] Only set PYTHON_HOME on Windows
My earlier change for Python auto-detection caused PYTHON_HOME to be set
unconditionally, while before the change this only happened for Windows.
This caused the PythonDataObjectsTest to fail with an import error.
The file was modifiedlldb/cmake/modules/LLDBConfig.cmake
Commit 0239526cccf8aa708e29eeb7e49de8f6dc6c1a5f by Jonas Devlieghere
[lldb/Docs] Fix capitalization typo.
This has been bothering me for way too long.
The file was modifiedlldb/docs/resources/build.rst
Commit 5b24c088171d3bd7a8ff559c82926e5d4b04f032 by sivachandra
[libc] Move all tests to a top level `test` directory.
A toplevel target, `check-libc` has also been added.
Reviewers: abrachet, phosek
Tags: #libc-project
Differential Revision: https://reviews.llvm.org/D72177
The file was modifiedlibc/src/errno/CMakeLists.txt
The file was addedlibc/test/src/string/strcat_test.cpp
The file was addedlibc/test/src/string/strcpy_test.cpp
The file was addedlibc/test/config/linux/CMakeLists.txt
The file was addedlibc/test/src/errno/CMakeLists.txt
The file was addedlibc/test/src/CMakeLists.txt
The file was removedlibc/src/errno/errno_test.cpp
The file was addedlibc/test/CMakeLists.txt
The file was addedlibc/test/src/sys/mman/mmap_test.cpp
The file was modifiedlibc/CMakeLists.txt
The file was addedlibc/test/config/linux/x86_64/CMakeLists.txt
The file was modifiedlibc/src/sys/mman/CMakeLists.txt
The file was removedlibc/src/sys/mman/mmap_test.cpp
The file was addedlibc/test/config/CMakeLists.txt
The file was removedlibc/src/string/strcpy/strcpy_test.cpp
The file was removedlibc/config/linux/x86_64/syscall_test.cpp
The file was addedlibc/test/src/string/CMakeLists.txt
The file was modifiedlibc/src/string/strcpy/CMakeLists.txt
The file was addedlibc/test/src/sys/mman/CMakeLists.txt
The file was addedlibc/test/src/sys/CMakeLists.txt
The file was modifiedlibc/docs/source_layout.rst
The file was removedlibc/src/string/strcat/strcat_test.cpp
The file was modifiedlibc/src/string/strcat/CMakeLists.txt
The file was addedlibc/test/config/linux/x86_64/syscall_test.cpp
The file was addedlibc/test/src/errno/errno_test.cpp
The file was modifiedlibc/config/linux/x86_64/CMakeLists.txt
The file was modifiedlibc/src/string/CMakeLists.txt
Commit 7ae3d335467a24faa80ebd9b31446c649570ca0c by maskray
[lld] Fix trivial typos in comments
Reviewed By: ruiu, MaskRay
Differential Revision: https://reviews.llvm.org/D72196
The file was modifiedlld/lib/Driver/DarwinLdDriver.cpp
The file was modifiedlld/docs/WebAssembly.rst
The file was modifiedlld/ELF/ICF.cpp
The file was modifiedlld/ELF/OutputSections.cpp
The file was modifiedlld/lib/ReaderWriter/MachO/MachOLinkingContext.cpp
The file was modifiedlld/ELF/Arch/X86.cpp
The file was modifiedlld/test/ELF/linkerscript/assert.s
The file was modifiedlld/test/ELF/ppc64-bsymbolic-toc-restore.s
The file was modifiedlld/wasm/SymbolTable.cpp
The file was modifiedlld/lib/ReaderWriter/MachO/File.h
The file was modifiedlld/lib/ReaderWriter/MachO/CompactUnwindPass.cpp
The file was modifiedlld/lib/ReaderWriter/MachO/MachONormalizedFileToAtoms.cpp
The file was modifiedlld/ELF/InputSection.cpp
The file was modifiedlld/ELF/InputFiles.cpp
The file was modifiedlld/include/lld/Core/Atom.h
The file was modifiedlld/include/lld/Core/Reference.h
The file was modifiedlld/lib/ReaderWriter/MachO/MachONormalizedFileBinaryWriter.cpp
The file was modifiedlld/lib/ReaderWriter/YAML/ReaderWriterYAML.cpp
The file was modifiedlld/test/wasm/export-optional-lazy.ll
The file was modifiedlld/wasm/InputChunks.h
The file was modifiedlld/Common/Filesystem.cpp
The file was modifiedlld/docs/windows_support.rst
The file was modifiedlld/wasm/Symbols.h
The file was modifiedlld/wasm/InputFiles.cpp
The file was modifiedlld/wasm/Config.h
The file was modifiedlld/lib/Core/Resolver.cpp
The file was modifiedlld/test/ELF/aarch64-movw-tprel.s
The file was modifiedlld/lib/ReaderWriter/MachO/GOTPass.cpp
The file was modifiedlld/include/lld/Core/Instrumentation.h
The file was modifiedlld/test/wasm/signature-mismatch-unknown.ll
The file was modifiedlld/include/lld/ReaderWriter/MachOLinkingContext.h
Commit e29a2e6be4e114b4233a2e0feedb74b2f34cf782 by Jinsong Ji
[PowerPC][LoopVectorize] Extend getRegisterClassForType to consider
double and other floating point type
In https://reviews.llvm.org/D67148, we use isFloatTy to test floating
point type, otherwise we return GPRRC. So 'double' will be classified as
GPRRC, which is not accurate.
This patch covers other floating point types.
Reviewed By: #powerpc, nemanjai
Differential Revision: https://reviews.llvm.org/D71946
The file was modifiedllvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
The file was modifiedllvm/test/Transforms/LoopVectorize/PowerPC/reg-usage.ll
Commit df3f4e0d77e53193acd423d1b02d3fd3bf065bf7 by Amara Emerson
[X86] Fix an 8 bit testb being selected when folding a volatile i32 load
pattern.
Differential Revision: https://reviews.llvm.org/D71581
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
The file was addedllvm/test/CodeGen/X86/select-testb-volatile-load.ll
Commit 40a80a0a19f4ed1b5d4a2e842c5541da36342c14 by eugenis
Lower TAGPstack with negative offset to SUBG.
Summary: This never really occurs in the current codegen, so only a MIR
test is possible.
Reviewers: ostannard, pcc
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72123
The file was modifiedllvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
The file was addedllvm/test/CodeGen/AArch64/addg_subg.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.cpp
Commit 19433b199d1ccc8798475dbe9084fc66360ec5d5 by kkwli0
[OpenMP] Fix incorrect property of __has_attribute() macro
__has_attribute(fallthough) -> __has_attribute(fallthrough)
Submitted by: kiszk (Kazuaki Ishizaki <ishizaki@jp.ibm.com>)
Differential Revision: https://reviews.llvm.org/D72287
The file was modifiedopenmp/runtime/src/kmp_os.h
Commit 22cec48dacc681230984d9fe78af7e31d89529f1 by spatel
[x86] add tests for concat self + shuffle; NFC
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll
Commit b73fea6a7cfd87fe07b9c05ba153042198b5d873 by wan.yu
[NFC] Test commit, whitespace change
As per the Developer Policy, upon obtaining commit access.
The file was modifiedclang/lib/Driver/ToolChains/AIX.cpp
Commit 02f694b69a8b30db7b5d43670da5ab3b9f31bb81 by wan.yu
 [NFC] Test commit, revert whitespace change
As per the Developer Policy, upon obtaining commit access.
The file was modifiedclang/lib/Driver/ToolChains/AIX.cpp
Commit 7b518dcb291e740c3e957d93c2b4046bc8a97f00 by a.bataev
[OPENMP50]Support lastprivate conditional updates in inc/dec unary ops.
Added support for checking of updates of variables used in unary
pre(pos) inc/dec expressions.
The file was modifiedclang/lib/CodeGen/CGStmtOpenMP.cpp
The file was modifiedclang/test/OpenMP/for_lastprivate_codegen.cpp
The file was modifiedclang/lib/CodeGen/CGExprScalar.cpp
The file was modifiedclang/test/OpenMP/sections_lastprivate_codegen.cpp
The file was modifiedclang/lib/CodeGen/CGExpr.cpp
The file was modifiedclang/lib/CodeGen/CGOpenMPRuntime.cpp
The file was modifiedclang/lib/CodeGen/CGOpenMPRuntime.h
Commit ca868002d31b013b1d5998177ea4252ffcd84b67 by craig.topper
[X86] Rename vec-strict-*-cmp.ll to vec-strict-cmp-*.ll to match other
strict files wich have the size at the end. NFC
The file was removedllvm/test/CodeGen/X86/vec-strict-512-cmp.ll
The file was addedllvm/test/CodeGen/X86/vec-strict-cmp-256.ll
The file was removedllvm/test/CodeGen/X86/vec-strict-128-cmp.ll
The file was addedllvm/test/CodeGen/X86/vec-strict-cmp-128.ll
The file was addedllvm/test/CodeGen/X86/vec-strict-cmp-512.ll
The file was removedllvm/test/CodeGen/X86/vec-strict-256-cmp.ll
Commit 62f3403bfc17906aba555d6100e0136363f6a649 by craig.topper
[LegalizeTypes] Add widening support for STRICT_FSETCC/FSETCCS
This patch adds widening which really just scalarizes because we don't
have a strategy for the extra elements we would need to pad with.
Differential Revision: https://reviews.llvm.org/D72193
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
The file was addedllvm/test/CodeGen/X86/vec-strict-cmp-sub128.ll
Commit 317cbdad4d1b9ea7ec703072aba34eeb62c9d3af by Jonas Devlieghere
[lldb/Docs] Describe optional dependencies on build page.
List the different CMake flags controlling the optional dependencies as
per the discussion on the mailing list:
http://lists.llvm.org/pipermail/lldb-dev/2020-January/015867.html
The file was modifiedlldb/docs/resources/build.rst
Commit 6a0564adcfe65956cb1099e8ec6c4801655007c4 by craig.topper
[X86] Improve v4i32->v4f64 uint_to_fp for AVX1/AVX2 targets.
Use zext+or+fsub to do the conversion. Similar to D71971.
Differential Revision: https://reviews.llvm.org/D71971
The file was modifiedllvm/test/CodeGen/X86/vec-strict-inttofp-256.ll
The file was modifiedllvm/test/CodeGen/X86/vec_int_to_fp.ll
The file was modifiedllvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll
The file was modifiedllvm/test/CodeGen/X86/vec_uint_to_fp.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 5518a02a83e855edeff7d8b4db685ec5d1b4144e by arsenm2
llc/MIR: Fix setFunctionAttributes for MIR functions
A random set of attributes are implemented by llc/opt forcing the string
attributes on the IR functions before processing anything. This would
not happen for MIR functions, which have not yet been created at this
point.
Use a callback in the MIR parser, purely to avoid dealing with the
ugliness that the command line flags are in a .inc file, and would
require allowing access to these flags from multiple places (either from
the MIR parser directly, or a new utility pass to implement these
flags). It would probably be better to cleanup the flag handling into a
separate library.
This is in preparation for treating more command line flags with a
corresponding function attribute in a more uniform way. The fast math
flags in particular have a messy system where the command line flag sets
the behavior from a function attribute if present, and otherwise the
command line flag. This means if any other pass tries to inspect the
function attributes directly, it will be inconsistent with the intended
behavior. This is also inconsistent with the current behavior of -mcpu
and -mattr, which overwrites any pre-existing function attributes. I
would like to move this to consistenly have the command line flags not
overwrite any pre-existing attributes, and to always ensure the command
line flags are consistent with the function attributes.
The file was modifiedllvm/include/llvm/CodeGen/CommandFlags.inc
The file was addedllvm/test/CodeGen/MIR/AMDGPU/llc-target-cpu-attr-from-cmdline.mir
The file was modifiedllvm/include/llvm/CodeGen/MIRParser/MIRParser.h
The file was addedllvm/test/CodeGen/MIR/AMDGPU/llc-target-cpu-attr-from-cmdline-ir.mir
The file was modifiedllvm/tools/llc/llc.cpp
The file was modifiedllvm/lib/CodeGen/MIRParser/MIRParser.cpp
Commit 14d25052a2902dacdd73aa1714ba1fb639c1dedd by arsenm2
AMDGPU: Use ImmLeaf for inline immediate predicates
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.td
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
Commit a506efff18224a0c73db42bed8679413514c28b1 by arsenm2
AMDGPU: Use ImmLeaf
This solves one GlobalISel importer error, but the pattern still fails
for another reason.
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.td
Commit 7f2db2917da9e4fe43976b7abe37400812ed5dea by arsenm2
AMDGPU: Fix legalizing f16 fpow
The existing test only covered one case for r600. The use of mul_legacy
also looks suspicious to me, but leave it for now. The patterns are also
not making use of source modifiers.
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was addedllvm/test/CodeGen/AMDGPU/fpow.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
Commit 0b093f02120e212b9c1305eae626e9b5e99b92fa by arsenm2
GlobalISel: Start adding computeNumSignBits to GISelKnownBits
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/GISelKnownBits.h
The file was modifiedllvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
The file was modifiedllvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp
Commit 1060b9e23b8f9d2802835896947ec281ba3b4f6b by arsenm2
GlobalISel: Correct result type for G_FCMP in lowerFPTOUI
Using the final result type doesn't make any sense. Use the natural
default boolean type for the select condition.
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fptosi_and_fptoui.ll
Commit ee6b8722ffa101b57af9029c84691cb7e8a43799 by arsenm2
GlobalISel: Fix unsupported legalize action
This would complain about invalid legalizer rules otherwise.
Mark some operations as unsupported for AMDGPU. This currently seems to
produce the same legalize error as when no rules are defined, but
eventually this should produce a proper user facing error.
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-jump-table.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
Commit f5329bfc76bb6fc30a589e8238aabc005c52e5d6 by tyker
[Diagnostic] make Wmisleading-indendation not warn about labels
Reviewers: aaron.ballman, xbolva00
Reviewed By: aaron.ballman
Subscribers: nickdesaulniers, nathanchance
Differential Revision: https://reviews.llvm.org/D72202
The file was modifiedclang/test/Parser/warn-misleading-indentation.cpp
The file was modifiedclang/lib/Parse/ParseStmt.cpp
Commit 24ee4edee8e00bb7ad3d3cda17d02a442456ff3e by Jinsong Ji
[PowerPC][NFC] Rename record instructions to use _rec suffix instead of
o
We use o suffix to indicate record form instuctions,
(as it is similar to dot '.' in mne?)
This was fine before, as we did not support XO-form. However, with
https://reviews.llvm.org/D66902, we now have XO-form support.
It becomes confusing now to still use 'o' for record form, and it is
weird to have something like 'Oo' .
This patch rename all 'o' instructions to use '_rec' instead. Also
rename `isDot` to `isRecordForm`.
Reviewed By: #powerpc, hfinkel, nemanjai, steven.zhang, lkail
Differential Revision: https://reviews.llvm.org/D70758
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.h
The file was modifiedllvm/lib/Target/PowerPC/PPCInstr64Bit.td
The file was modifiedllvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrVSX.td
The file was modifiedllvm/test/CodeGen/PowerPC/ifcvt-diamond-ret.mir
The file was modifiedllvm/lib/Target/PowerPC/P9InstrResources.td
The file was modifiedllvm/test/CodeGen/PowerPC/block-placement.mir
The file was modifiedllvm/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrHTM.td
The file was modifiedllvm/test/CodeGen/PowerPC/fold-rlwinm.mir
The file was modifiedllvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrFormats.td
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrAltivec.td
The file was modifiedllvm/lib/Target/PowerPC/PPCMIPeephole.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.td
The file was modifiedllvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
The file was modifiedllvm/test/CodeGen/PowerPC/peephole-miscompile-extswsli.mir
Commit d8fd92eaaa34b463a573ed1b216f93a3d1ff6eef by thomasp
[FileCheck] Remove FileCheck prefix in API
Summary: When FileCheck was made a library, types in the public API were
renamed to add a FileCheck prefix, such as Pattern to FileCheckPattern.
Many types were moved into a private interface and thus don't need this
prefix anymore. This commit removes those unneeded prefixes.
Reviewers: jhenderson, jdenny, probinson, grimar, arichardson, rnk
Reviewed By: jhenderson
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72186
The file was modifiedllvm/lib/Support/FileCheck.cpp
The file was modifiedllvm/lib/Support/FileCheckImpl.h
The file was modifiedllvm/unittests/Support/FileCheckTest.cpp
Commit 83d690a149802d40c711d4fb5a058dd1ebe4aa23 by isanbard
Don't rely on 'l'(ell) modifiers to indicate a label reference
Summary: It's not necessary to use an 'l'(ell) modifier when referencing
a label. Treat block addresses and MBB references as if the modifier is
used anyway. This prevents us from generating references to ficticious
labels.
Reviewers: jyknight, nickdesaulniers, hfinkel
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D71849
The file was modifiedllvm/test/CodeGen/X86/callbr-asm.ll
The file was modifiedllvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
Commit 71a2a62163cfafbc31cd827106506c73ff49e8b5 by phosek
[CMake] Pass symlink dependency to add_llvm_install_targets explicitly
The install-${name}-stripped targets don't strip when ${name} is being
symlinked, e.g. llvm-ar or llvm-objcopy. The problem is that
llvm_install_symlink passes install-${dest} as a dependency of
install-${name}, e.g. install-llvm-ar becomes a dependency of both
install-llvm-ranlib and install-llvm-ranlib-stripped. What this means is
that when installing a distribution that contains both llvm-ar and
llvm-ranlib is that first the stripped version of llvm-ar is installed
(by the install-llvm-ar-stripped target) and then it's overwritten by an
unstripped version of llvm-ar bnecause install-llvm-ranlib-stripped has
install-llvm-ranlib as a dependency as mentioned earlier. To avoid this
issue, rather than passing the install-${dest} as dependency, we
introduce a new argument to add_llvm_install_targets for symlink target
which expands it into an appropriate dependency, i.e. install-${dest}
for install-${name} target and install-${dest}-stripped for
install-${name}-stripped.
Differential Revision: https://reviews.llvm.org/D71951
The file was modifiedllvm/cmake/modules/AddLLVM.cmake
Commit 59fadc14eeb1d63177b76147b26348a106ac1f9b by ditaliano
[NSArray] Remove a very old and deprecated formatter.
Checked with the Foundation folks.
The file was modifiedlldb/source/Plugins/Language/ObjC/NSArray.cpp
Commit b5e7f95cfbeb28ff8b966a2b7e38a03f32410030 by eugenis
[msan] Check qsort input.
Summary: Qsort interceptor suppresses all checks by unpoisoning the data
in the wrapper of a comparator function, and then unpoisoning the output
array as well.
This change adds an explicit run of the comparator on all elements of
the input array to catch any sanitizer bugs.
Reviewers: vitalybuka
Subscribers: #sanitizers, llvm-commits
Tags: #sanitizers, #llvm
Differential Revision: https://reviews.llvm.org/D71780
The file was modifiedcompiler-rt/test/msan/qsort.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
Commit 08d17cb065da46be02d36ebeaac1106ee330935b by listmail
[X86] Move an enum definition into a header to simplify future patches
[NFC]
The file was modifiedllvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
The file was modifiedllvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
Commit 450073c639d7f182e48ec8b1b588212194089a52 by Jason Molenda
Change the patterns to include the prefix '= ' so we don't pass
errantly. Looking at a sometimes-passing test case on a platform where
random values were being returned - sometimes the expected digit ('1' or
'2') would be included in the random returned value.  Add a prefix to
reduce the likelihood of this a bit.
The file was modifiedlldb/packages/Python/lldbsuite/test/commands/expression/call-overridden-method/TestCallOverriddenMethod.py
Commit f3de8ab5ccedefb3165dae2511650d6a60e905cf by arsenm2
GlobalISel: Implement lower for G_INTRINSIC_ROUND
Mostly copied from AMDGPU lowering implementation, except used G_SITOFP
instead of directly creating a select on -1.0, 0.0.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was removedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-round.mir
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
Commit 26f714ff43e3498ae2528ad8c9875de77a529472 by arsenm2
TableGen/GlobalISel: Handle default operands that are used
Copy the logic from the existing handling in the DAG matcher emittter.
This will enable some AMDGPU pattern cleanups without breaking
GlobalISel tests, and eventually handle importing more patterns.
The test is a bit annoying since the sections seem to randomly sort
themselves if anything else is added in the future.
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp
The file was addedllvm/test/TableGen/DefaultOpsGlobalISel.td
Commit 4e85ca9562a588eba491e44bcbf73cb2f419780f by arsenm2
AMDGPU/GlobalISel: Replace handling of boolean values
This solves selection failures with generated selection patterns, which
would fail due to inferring the SGPR reg bank for virtual registers with
a set register class instead of VCC bank. Use instruction selection
would constrain the virtual register to a specific class, so when the
def was selected later the bank no longer was set to VCC.
Remove the SCC reg bank. SCC isn't directly addressable, so it requires
copying from SCC to an allocatable 32-bit register during selection, so
these might as well be treated as 32-bit SGPR values.
Now any scalar boolean value that will produce an outupt in SCC should
be widened during RegBankSelect to s32. Any s1 value should be a vector
boolean during selection. This makes the vcc register bank unambiguous
with a normal SGPR during selection.
Summary of how this should now work:
- G_TRUNC is always a no-op, and never should use a vcc bank result.
- SALU boolean operations should be promoted to s32 in RegBankSelect
apply mapping
- An s1 value means vcc bank at selection. The exception is for
legalization artifacts that use s1, which are never VCC. All other
contexts should infer the VCC register classes for s1 typed
registers. The LLT for the register is now needed to infer the
correct register class. Extensions with vcc sources should be
legalized to a select of constants during RegBankSelect.
- Copy from non-vcc to vcc ensures high bits of the input value are
cleared during selection.
- SALU boolean inputs should ensure the inputs are 0/1. This includes
select, conditional branches, and carry-ins.
There are a few somewhat dirty details. One is that G_TRUNC/G_*EXT
selection ignores the usual register-bank from register class functions,
and can't handle truncates with VCC result banks. I think this is OK,
since the artifacts are specially treated anyway. This does require some
care to avoid producing cases with vcc. There will also be no 100%
reliable way to verify this rule is followed in selection in case of
register classes, and violations manifests themselves as invalid copy
instructions much later.
Standard phi handling also only considers the bank of the result
register, and doesn't insert copies to make the source banks match. This
doesn't work for vcc, so we have to manually correct phi inputs in this
case. We should add a verifier check to make sure there are no phis with
mixed vcc and non-vcc register bank inputs.
There's also some duplication with the LegalizerHelper, and some code
which should live in the helper. I don't see a good way to share special
knowledge about what types to use for intermediate operations depending
on the bank for example. Using the helper to replace extensions with
selects also seems somewhat awkward to me.
Another issue is there are some contexts calling getRegBankFromRegClass
that apparently don't have the LLT type for the register, but I haven't
yet run into a real issue from this.
This also introduces new unnecessary instructions in most cases, since
we don't yet try to optimize out the zext when the source is known to
come from a compare.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.mir
The file was removedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi-invalid.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-brcond.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s64.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kill.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-brcond.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBanks.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.vote.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usubo.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uaddo.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usubo.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.private.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.shared.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uaddo.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir
Commit d4c9e13324443c0324148156d54d2c7c81393327 by arsenm2
AMDGPU/GlobalISel: Select G_UADDE/G_USUBE
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usube.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uadde.gfx10.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usube.gfx10.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uadde.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
Commit c6fd16af2be98b49d663285e3808ecde61bec614 by Akira
Use FileCheck instead of grep
The file was modifiedclang/test/CodeGenObjC/encode-test-2.m
Commit 6904cd948674df7f55843519695dbc95157a9429 by maskray
Add Triple::isX86()
Reviewed By: craig.topper, skan
Differential Revision: https://reviews.llvm.org/D72247
The file was modifiedllvm/lib/IR/AutoUpgrade.cpp
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedclang/lib/AST/MicrosoftMangle.cpp
The file was modifiedclang/lib/Driver/ToolChains/Darwin.cpp
The file was modifiedllvm/include/llvm/ADT/Triple.h
The file was modifiedclang/lib/Driver/ToolChains/FreeBSD.cpp
The file was modifiedclang/lib/Parse/ParseStmtAsm.cpp
The file was modifiedllvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
Commit 5e0e0e3ff05f57b9495db57b6b205492d34cb5a8 by koraq
[NFC] Fixes -Wrange-loop-analysis warnings
This avoids new warnings due to D68912 adds -Wrange-loop-analysis to
-Wall.
The file was modifiedllvm/unittests/Support/ReverseIterationTest.cpp
Commit 7ba4595c86be88bf9ebb7261ba49ed4626e5f585 by eugenis
[msan] Fix underflow in qsort interceptor.
The file was modifiedcompiler-rt/test/msan/qsort.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
Commit 20f005d25f488fa1dc69d6792700e014c6a5d165 by Akira
[CodeGen][ObjC] Push the properties of a protocol before pushing the
properties of the protocol it inherits
This fixes a bug where the type string for a @dynamic property of an
@implementation didn't have 'D' in it when the protocol it conforms to
redeclares the property declared in the base protocol.
rdar://problem/45503561
The file was modifiedclang/lib/CodeGen/CGObjCMac.cpp
The file was modifiedclang/test/CodeGenObjC/encode-test-2.m
Commit 52afc93c38c4dc6071172e2f580d364592d92dda by arsenm2
AMDGPU/GlobalISel: Legalize G_READCYCLECOUNTER
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/readcyclecounter.ll
Commit 21f7b362095f7497aa87ccc334fe18bbc072854c by aheejin
[WebAssembly] Fix landingpad-only case in Emscripten EH
Summary: Previously we didn't set `Changed` to true when there are only
landing pads but not invokes. This fixes it and we set `Changed` to true
whenever we have landing pads. (There can't be invokes without landing
pads, so that case is covered too)
The test case for this has to be a separate file because this pass is a
`ModulePass` and `Changed` is computed based on the whole module.
Reviewers: tlively
Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish,
llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72308
The file was addedllvm/test/CodeGen/WebAssembly/lower-em-exceptions-lpad-only.ll
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
Commit e93b1ffc8490d943690726370a0e9277fd78520d by arsenm2
AMDGPU: Use default operands for clamp/omod
We have a lot of complex pattern variants that just set the source
modifiers that are really handled, and then set the output modifiers to
0. We're unlikely to ever match output modifiers from the use
instruction side, and we already match clamp/omod in a separate pass.
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.td
Commit 907cefe721437fa8950c1b6c1c028038b175f921 by richard
Always deduce the lengths of contained parameter packs when deducing a
pack expansion.
Previously, if all parameter / argument pairs for a pack expansion
deduction were non-deduced contexts, we would not deduce the arity of
the pack, and could end up deducing a different arity (leading to
failures during substitution) or defaulting to an arity of 0 (leading to
bad diagnostics about passing the wrong number of arguments to a
variadic function). Instead, we now always deduce the arity for all
involved packs any time we deduce a pack expansion.
This will result in less substitution happening in some cases, which
could avoid non-SFINAEable errors, and should generally improve the
quality of diagnostics when passing initializer lists to variadic
functions.
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/test/SemaTemplate/deduction.cpp
The file was modifiedclang/test/CXX/drs/dr13xx.cpp
The file was modifiedclang/lib/Sema/SemaOverload.cpp
The file was modifiedclang/lib/Sema/SemaTemplateDeduction.cpp
The file was modifiedclang/test/CXX/temp/temp.fct.spec/temp.deduct/temp.deduct.type/p5-0x.cpp
The file was modifiedclang/test/SemaTemplate/alias-templates.cpp
The file was modifiedclang/test/SemaTemplate/pack-deduction.cpp
Commit 452f6243c9be73a476f796b1425bfc58749b9805 by arsenm2
AMDGPU: Select llvm.amdgcn.interp.p2.f16 directly
This will enable automatic GlobalISel support in a future commit.
The file was modifiedllvm/lib/Target/AMDGPU/VOP3Instructions.td
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
Commit e8d9d202bc93f64c5225f15af2e6b9957100fd60 by arsenm2
AMDGPU: Add run line to int_to_fp tests
This wasn't catching a regression on targets with legal i16 triggered in
a future commit.
The file was modifiedllvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
Commit d877229b5b21c833e2344eda7c07f9c49d4dc453 by qshanz
[NFC][Test] Add a test to verify the DAGCombine of fma
The file was addedllvm/test/CodeGen/PowerPC/fma-combine.ll
Commit e3750cafdb17f5b7431f18c0229bfb597dde4c88 by ntv
[mlir][Linalg] Add a linalg.reshape op
Summary: This diff adds a new operation to linalg to allow reshaping of
an existing view into a new view in the same buffer at the same offset.
More specifically: The `linalg.reshape` op produces a new view whose
sizes are a reassociation of the original `view`. Depending on whether
or not the reassociated MemRefType is contiguous, the resulting memref
may require explicit alloc and copies.
A reassociation is defined as a continous grouping of dimensions and is
represented with a affine map array attribute. In the future,
non-continous groupings may be allowed (i.e. permutations, reindexings
etc).
For now, it is assumed that either:
1. a reassociation produces and consumes contiguous MemRefType or,
2. the reshape op will be folded into its consumers (by changing the
shape
    of the computations). All other cases are undefined behavior and a
reshape op may not lower to LLVM if it cannot be proven statically that
it does not require alloc+copy.
A reshape may either collapse or expand dimensions, depending on the
relationship between source and target memref ranks. The verification
rule is that the reassociation maps are applied to the memref with the
larger rank to obtain the memref with the smaller rank. In the case of a
dimension expansion, the reassociation maps can be interpreted as
inverse maps.
Examples:
```mlir
  // Dimension collapse (i, j) -> i' and k -> k'
  %1 = linalg.reshape %0 [(i, j, k) -> (i, j),
                          (i, j, k) -> (k)] :
    memref<?x?x?xf32, stride_spec> into memref<?x?xf32, stride_spec_2>
```
```mlir
  // Dimension expansion i -> (i', j') and (k) -> (k')
  %1 = linalg.reshape %0 [(i, j, k) -> (i, j),
                          (i, j, k) -> (k)] :
    memref<?x?xf32, stride_spec> into memref<?x?x?xf32, stride_spec_2>
```
The relevant invalid and roundtripping tests are added.
Reviewers: AlexEichenberger, ftynse, rriddle, asaadaldien, yangjunpro
Subscribers: kiszk, merge_guards_bot, mehdi_amini, jpienaar, burmako,
shauheen, antiagainst, arpith-jacob, mgester, lucyrfox, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72168
The file was modifiedmlir/include/mlir/Dialect/Linalg/EDSC/Intrinsics.h
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
The file was modifiedmlir/test/Dialect/Linalg/roundtrip.mlir
The file was modifiedmlir/lib/IR/StandardTypes.cpp
The file was modifiedmlir/include/mlir/IR/StandardTypes.h
The file was modifiedmlir/include/mlir/IR/AffineExpr.h
The file was modifiedmlir/test/Dialect/Linalg/invalid.mlir
Commit dc7b84c66c10f47adf22baab0103eb9f6593cd72 by arsenm2
AMDGPU/GlobalISel: Fix unused variable warning in release
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
Commit aa708763d30384c0da0b0779be96ba45f65773df by maskray
[MC] Add parameter `Address` to MCInstPrinter::printInst
printInst prints a branch/call instruction as `b offset` (there are many
variants on various targets) instead of `b address`.
It is a convention to use address instead of offset in most external
symbolizers/disassemblers. This difference makes `llvm-objdump -d`
output unsatisfactory.
Add `uint64_t Address` to printInst(), so that it can pass the argument
to printInstruction(). `raw_ostream &OS` is moved to the last to be
consistent with other print* methods.
The next step is to pass `Address` to printInstruction() (generated by
tablegen from the instruction set description). We can gradually migrate
targets to print addresses instead of offsets.
In any case, downstream projects which don't know `Address` can pass 0
as the argument.
Reviewed By: jhenderson
Differential Revision: https://reviews.llvm.org/D72172
The file was modifiedllvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
The file was modifiedllvm/tools/llvm-mca/Views/BottleneckAnalysis.cpp
The file was modifiedllvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
The file was modifiedllvm/tools/llvm-mca/llvm-mca.cpp
The file was modifiedllvm/include/llvm/MC/MCStreamer.h
The file was modifiedllvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.h
The file was modifiedllvm/tools/llvm-cfi-verify/lib/FileAnalysis.cpp
The file was modifiedllvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h
The file was modifiedllvm/tools/llvm-objdump/llvm-objdump.cpp
The file was modifiedllvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.h
The file was modifiedllvm/lib/Target/BPF/MCTargetDesc/BPFInstPrinter.h
The file was modifiedllvm/tools/llvm-mca/Views/InstructionInfoView.cpp
The file was modifiedllvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp
The file was modifiedllvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp
The file was modifiedllvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
The file was modifiedllvm/lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.cpp
The file was modifiedllvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
The file was modifiedllvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.h
The file was modifiedllvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.h
The file was modifiedllvm/lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.cpp
The file was modifiedllvm/lib/Target/XCore/MCTargetDesc/XCoreInstPrinter.cpp
The file was modifiedllvm/lib/MC/MCStreamer.cpp
The file was modifiedllvm/lib/Target/ARC/MCTargetDesc/ARCInstPrinter.cpp
The file was modifiedllvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.h
The file was modifiedllvm/lib/MC/MCAsmStreamer.cpp
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
The file was modifiedllvm/lib/Target/BPF/MCTargetDesc/BPFInstPrinter.cpp
The file was modifiedllvm/lib/MC/MCDisassembler/Disassembler.cpp
The file was modifiedllvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
The file was modifiedllvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
The file was modifiedllvm/include/llvm/MC/MCInstPrinter.h
The file was modifiedllvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
The file was modifiedllvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
The file was modifiedllvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
The file was modifiedllvm/tools/llvm-mca/Views/TimelineView.cpp
The file was modifiedllvm/lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
The file was modifiedllvm/lib/Target/XCore/MCTargetDesc/XCoreInstPrinter.h
The file was modifiedllvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.cpp
The file was modifiedllvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
The file was modifiedllvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.h
The file was modifiedllvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h
The file was modifiedllvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h
The file was modifiedllvm/tools/llvm-objdump/MachODump.cpp
The file was modifiedllvm/tools/llvm-mca/Views/ResourcePressureView.cpp
The file was modifiedllvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp
The file was modifiedllvm/lib/Target/ARC/MCTargetDesc/ARCInstPrinter.h
The file was modifiedllvm/tools/llvm-exegesis/lib/Analysis.cpp
The file was modifiedllvm/lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.h
The file was modifiedllvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h
The file was modifiedllvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.cpp
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp