SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [lldb/SWIG] Add missing '\' in macros again (details)
  2. [lldb/Lua] Make lldb.debugger et al available to Lua (details)
  3. [NFCI][LoopUnrollAndJam] Changing LoopUnrollAndJamPass to a function (details)
  4. Improve support of GNU mempcpy (details)
  5. [OpenCL][Docs] Rename C++ for OpenCL label (details)
  6. [lldb/Bindings] Move bindings into their own subdirectory (details)
  7. [clangd] Adjust diagnostic range to be inside main file (details)
  8. [lldb/SWIG] Fix capitalization for case sensitive file systems. (details)
  9. [Clang] Handle target-specific builtins returning aggregates. (details)
  10. [Support][NFC] Add a comment about the semantics of MF_HUGE_HINT flag (details)
  11. [NFC,format] Sort switch cases alphabetically (details)
  12. [Support][NFC] Make some helper functions "static" in Memory.inc (details)
  13. [lldb/SWIG] Undo incorrect substitution (details)
  14. [SystemZ] Fix matching another pattern for nxgrk (PR44496) (details)
  15. [x86] add tests for 2-way splat copy; NFC (details)
  16. [Support][NFC] Add an explicit unit test for Process::getPageSize() (details)
  17. [TargetLowering][X86] TeachSimplifyDemandedBits to handle cases where (details)
  18. [demangle] Copy back some NFC commits from LLVM (details)
  19. [PowerPC] The VK_PLT symbolref modifier is only used on 32-bit ELF. (details)
  20. [X86] AMD Znver2 (Rome) Scheduler enablement (details)
  21. [ms] [X86] Use "P" modifier on all branch-target operands in inline X86 (details)
  22. [clang] Enforce triple in mempcpy test (details)
  23. [GlobalISel][AArch64] Import + select LDR*roW and STR*roW patterns (details)
  24. [X86] Add ueq/one fp128 quiet compare tests. NFC (details)
  25. Re-apply "[ELF] Allow getErrPlace() to work before Out::bufferStart is (details)
  26. MipsDelaySlotFiller: Update registers def-uses for BUNDLE instructions (details)
  27. [mlir] NFC: Move the state for managing SSA value names out of (details)
  28. [libc++] Explicitly enumerate std::string external instantiations. (details)
  29. [clang-tidy] Refresh the add_new_check.py now that we use a table + (details)
  30. [clangd] Handle DeducedTemplateSpecializationType in TargetFinder (details)
  31. phab doc: remove the svn section (details)
  32. phab doc: also document 'arc land' (details)
  33. phab doc: Replace or remove references to svn (details)
  34. AMDGPU/GlobalISel: Widen 16-bit shift amount sources (details)
  35. AMDGPU/GlobalISel: Fix argument lowering for vectors of pointers (details)
  36. GlobalISel: Don't assert on MoreElements creating vectors (details)
  37. TableGen/GlobalISel: Address fixme (details)
  38. GlobalISel: Move getLLTForMVT/getMVTForLLT (details)
  39. Add gdb pretty printer for MutableArrayRef, remove ConstArrayRef. (details)
  40. Add builtins for aligning and checking alignment of pointers and (details)
  41. [mlir] mlir-cpu-runner test's cblas_interface should export functions on (details)
  42. [mlir] add a missing dependency for Linalg conversion (details)
  43. [AArch64][GlobalISel] Implement selection of <2 x float> vector splat. (details)
  44. CodeGen: Use LLT instead of EVT in getRegisterByName (details)
  45. GlobalISel: Fix else after return (details)
  46. DAG: Don't use unchecked dyn_cast (details)
  47. GlobalISel: Handle llvm.read_register (details)
  48. TableGen/GlobalISel: Add way for SDNodeXForm to work on timm (details)
  49. TableGen/GlobalISel: Fix pattern matching of immarg literals (details)
  50. [lldb/Lua] Add lua typemaps for INOUT params (details)
  51. [mlir] Use getDenseElementBitwidth instead of (details)
  52. When diagnosing the lack of a viable conversion function, also list (details)
  53. AVR: Update for getRegisterByName change (details)
  54. [lldb] Remove spurious file (details)
  55. [AMDGPU] Fix bundle scheduling (details)
  56. When reading Aux file in chunks, read consecutive byte ranges (details)
  57. [ELF] Fix includeInDynsym() when an undefined weak is merged with a lazy (details)
  58. AMDGPU/GlobalISel: Fix G_EXTRACT_VECTOR_ELT mapping for s-v case (details)
  59. AMDGPU/GlobalISel: Select G_EXTRACT_VECTOR_ELT (details)
  60. Relax opcode checks in test for G_READCYCLECOUNTER to check for only a (details)
  61. CWG2352: Allow qualification conversions during reference binding. (details)
  62. [NFC] Style cleanup (details)
Commit 93a1e9c90c96a9130352bf358d7777f0379ebb48 by Jonas Devlieghere
[lldb/SWIG] Add missing '\' in macros again
Making the string conversion operator a macro unintentionally dropped
the backslash before '\n' and '\r' and was therefore incorrectly
stripping 'n' and 'r' from the object description.
The file was modifiedlldb/scripts/macros.swig
Commit 45c971f7eef18ef2b77a5f64133dbd7bd5939d5f by Jonas Devlieghere
[lldb/Lua] Make lldb.debugger et al available to Lua
The Python script interpreter makes the current debugger, target,
process, thread and frame available to interactive scripting sessions
through convenience variables. This patch does the same for Lua.
Differential revision: https://reviews.llvm.org/D71801
The file was modifiedlldb/source/Plugins/ScriptInterpreter/Lua/ScriptInterpreterLua.h
The file was addedlldb/test/Shell/ScriptInterpreter/Lua/Inputs/nested_sessions.in
The file was addedlldb/test/Shell/ScriptInterpreter/Lua/convenience_variables.test
The file was modifiedlldb/source/Plugins/ScriptInterpreter/Lua/ScriptInterpreterLua.cpp
The file was addedlldb/test/Shell/ScriptInterpreter/Lua/independent_state.test
The file was addedlldb/test/Shell/ScriptInterpreter/Lua/Inputs/independent_state.in
The file was modifiedlldb/source/Plugins/ScriptInterpreter/Lua/Lua.cpp
The file was addedlldb/test/Shell/ScriptInterpreter/Lua/Inputs/nested_sessions_2.in
The file was addedlldb/test/Shell/ScriptInterpreter/Lua/nested_sessions.test
The file was modifiedlldb/source/Plugins/ScriptInterpreter/Lua/Lua.h
Commit d27a15fed79c8e8484825ce6c3ce1682daeb1547 by whitneyt
[NFCI][LoopUnrollAndJam] Changing LoopUnrollAndJamPass to a function
pass.
Summary: This patch changes LoopUnrollAndJamPass to a function pass, and
keeps the loops traversal order same as defined in
FunctionToLoopPassAdaptor LoopPassManager.h.
The next patch will change the loop traversal to outer to inner order,
so more loops can be transform.
Discussion in llvm-dev mailing list:
https://groups.google.com/forum/#!topic/llvm-dev/LF4rUjkVI2g Reviewer:
dmgreen, jdoerfert, Meinersbur, kbarton, bmahjour, etiotto Reviewed By:
dmgreen Subscribers: hiraditya, zzheng, llvm-commits Tag: LLVM
Differential Revision: https://reviews.llvm.org/D72230
The file was modifiedllvm/include/llvm/Transforms/Scalar/LoopUnrollAndJamPass.h
The file was modifiedllvm/lib/Transforms/Scalar/LoopUnrollAndJamPass.cpp
The file was modifiedllvm/test/Transforms/LoopUnrollAndJam/pragma-explicit.ll
The file was modifiedllvm/lib/Passes/PassBuilder.cpp
The file was modifiedllvm/test/Transforms/LoopUnrollAndJam/unroll-and-jam.ll
The file was modifiedllvm/lib/Passes/PassRegistry.def
The file was modifiedllvm/test/Transforms/LoopUnrollAndJam/dependencies.ll
The file was modifiedllvm/test/Transforms/LoopUnrollAndJam/disable.ll
Commit cee4a1c957426e9477c8579ff960c8c2bd4af9e2 by sguelton
Improve support of GNU mempcpy
- Lower to the memcpy intrinsic
- Raise warnings when size/bounds are known
Differential Revision: https://reviews.llvm.org/D71374
The file was modifiedclang/lib/Sema/SemaChecking.cpp
The file was modifiedclang/include/clang/Basic/Builtins.def
The file was modifiedclang/lib/AST/Decl.cpp
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was modifiedclang/test/Analysis/bstring.c
The file was addedclang/test/CodeGen/mempcpy-libcall.c
Commit 241f335b268dc19a0dfb85686a7c82fb339421a8 by sven.vanhaastregt
[OpenCL][Docs] Rename C++ for OpenCL label
To avoid potential confusion with OpenCL C++.
The file was modifiedclang/docs/UsersManual.rst
Commit 6498aff249a1c3c6bad33137df3b90e2973722d6 by Jonas Devlieghere
[lldb/Bindings] Move bindings into their own subdirectory
All the code required to generate the language bindings for Python and
Lua lives under scripts, even though the majority of this code aren't
scripts at all, and surrounded by scripts that are totally unrelated.
I've reorganized these files and moved everything related to the
language bindings into a new top-level directory named bindings. This
makes the corresponding files self contained and much more discoverable.
Differential revision: https://reviews.llvm.org/D72437
The file was addedlldb/bindings/interface/SBExecutionContext.i
The file was addedlldb/bindings/interface/SBStream.i
The file was addedlldb/bindings/python.swig
The file was removedlldb/scripts/interface/SBThreadCollection.i
The file was removedlldb/scripts/interface/SBTypeSynthetic.i
The file was addedlldb/bindings/interface/SBQueue.i
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The file was addedlldb/bindings/interface/SBProcess.i
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The file was removedlldb/scripts/interface/SBTypeSummary.i
The file was addedlldb/bindings/interface/SBBroadcaster.i
The file was addedlldb/bindings/lua.swig
The file was addedlldb/bindings/interface/SBLineEntry.i
The file was removedlldb/scripts/interface/SBThread.i
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The file was modifiedlldb/docs/CMakeLists.txt
The file was addedlldb/bindings/interface/SBTypeSummary.i
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The file was removedlldb/scripts/interface/SBLaunchInfo.i
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The file was removedlldb/scripts/interface/SBTrace.i
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The file was removedlldb/scripts/macros.swig
The file was modifiedlldb/CMakeLists.txt
The file was addedlldb/bindings/interface/SBUnixSignals.i
The file was removedlldb/scripts/interface/SBMemoryRegionInfo.i
The file was removedlldb/scripts/interface/SBExpressionOptions.i
The file was removedlldb/scripts/interface/SBStream.i
The file was addedlldb/bindings/CMakeLists.txt
The file was addedlldb/bindings/interface/SBCommandReturnObject.i
The file was removedlldb/scripts/interface/SBValue.i
The file was addedlldb/bindings/interface/SBMemoryRegionInfo.i
The file was removedlldb/scripts/Python/python-wrapper.swig
The file was addedlldb/bindings/interface/SBDeclaration.i
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The file was addedlldb/bindings/interface/SBBreakpointName.i
The file was addedlldb/bindings/interface/SBLanguageRuntime.i
The file was removedlldb/scripts/interface/SBError.i
The file was addedlldb/bindings/python/python-typemaps.swig
The file was addedlldb/bindings/interface/SBTypeFormat.i
The file was removedlldb/scripts/lldb.swig
The file was addedlldb/bindings/macros.swig
The file was removedlldb/scripts/interface/SBMemoryRegionInfoList.i
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The file was addedlldb/bindings/python/createPythonInit.py
The file was addedlldb/bindings/interface/SBHostOS.i
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The file was addedlldb/bindings/python/python-swigsafecast.swig
The file was addedlldb/bindings/interface/SBSymbolContextList.i
The file was removedlldb/scripts/interface/SBThreadPlan.i
The file was addedlldb/bindings/interface/SBType.i
The file was addedlldb/bindings/interface/SBProcessInfo.i
The file was removedlldb/scripts/interface/SBQueueItem.i
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The file was removedlldb/scripts/interface/SBData.i
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The file was addedlldb/bindings/interface/SBSection.i
The file was addedlldb/bindings/interface/SBFileSpec.i
The file was addedlldb/bindings/interface/SBSourceManager.i
The file was addedlldb/bindings/interface/SBTrace.i
The file was addedlldb/bindings/interface/SBThread.i
The file was removedlldb/scripts/interface/SBType.i
The file was addedlldb/bindings/interface/SBThreadPlan.i
The file was removedlldb/scripts/interface/SBDebugger.i
The file was addedlldb/bindings/interface/SBThreadCollection.i
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The file was removedlldb/scripts/interface/SBProcessInfo.i
The file was removedlldb/scripts/interface/SBStructuredData.i
The file was addedlldb/bindings/interface/SBSymbol.i
The file was removedlldb/scripts/Python/python-swigsafecast.swig
The file was removedlldb/scripts/interface/SBBreakpoint.i
The file was addedlldb/bindings/interface/SBError.i
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The file was modifiedlldb/source/API/CMakeLists.txt
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The file was addedlldb/bindings/interface/SBDebugger.i
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The file was addedlldb/bindings/interface/SBFileSpecList.i
The file was addedlldb/bindings/interface/SBTypeEnumMember.i
The file was removedlldb/scripts/interface/SBExecutionContext.i
The file was removedlldb/scripts/Python/python-extensions.swig
The file was removedlldb/scripts/Python/createPythonInit.py
The file was removedlldb/scripts/interface/SBCommandReturnObject.i
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The file was addedlldb/bindings/interface/SBSymbolContext.i
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The file was removedlldb/scripts/interface/SBCommandInterpreter.i
The file was addedlldb/bindings/python/python-extensions.swig
The file was addedlldb/bindings/interface/SBVariablesOptions.i
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The file was removedlldb/scripts/lldb_lua.swig
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The file was removedlldb/scripts/interface/SBInstruction.i
The file was addedlldb/bindings/interface/SBBreakpointLocation.i
The file was removedlldb/scripts/Python/python-typemaps.swig
The file was removedlldb/scripts/interface/SBPlatform.i
The file was removedlldb/scripts/interface/SBCommunication.i
The file was addedlldb/bindings/interface/SBTypeNameSpecifier.i
The file was removedlldb/scripts/interface/SBSourceManager.i
The file was addedlldb/bindings/interface/SBAddress.i
The file was removedlldb/scripts/interface/SBTypeFormat.i
The file was removedlldb/scripts/interface/SBModule.i
The file was removedlldb/scripts/interface/SBModuleSpec.i
The file was addedlldb/bindings/interface/SBExpressionOptions.i
The file was removedlldb/scripts/interface/SBQueue.i
The file was addedlldb/bindings/interface/SBCommandInterpreter.i
The file was removedlldb/scripts/interface/SBFrame.i
The file was addedlldb/bindings/interface/SBTraceOptions.i
The file was removedlldb/scripts/interface/SBProcess.i
The file was removedlldb/scripts/CMakeLists.txt
The file was addedlldb/bindings/interface/SBModuleSpec.i
The file was addedlldb/bindings/interface/SBTarget.i
The file was addedlldb/bindings/interface/SBFrame.i
The file was addedlldb/bindings/headers.swig
The file was addedlldb/bindings/interface/SBWatchpoint.i
The file was removedlldb/scripts/interface/SBValueList.i
Commit 189aa5b7a4584677ad628ecc2c369db61d4d2515 by kadircet
[clangd] Adjust diagnostic range to be inside main file
Summary: LSP requires diagnostics to lay inside main file. In clangd we
keep diagnostics in three different cases:
- already in main file
- adjusted to a header included in main file
- has a note covering some range in main file
In the last case, we were not adjusting the diagnostics range to be in
main file, therefore these diagnostics ended up pointing some arbitrary
locations.
This patch fixes that issue by adjusting the range of diagnostics to be
the first note inside main file when converting to LSP.
Reviewers: ilya-biryukov
Subscribers: MaskRay, jkorous, arphaman, usaxena95, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D72458
The file was modifiedclang-tools-extra/clangd/unittests/DiagnosticsTests.cpp
The file was modifiedclang-tools-extra/clangd/Diagnostics.cpp
Commit 5e0bf6772e2ca450d3433fca8b47ce7bac5a6cc7 by Jonas Devlieghere
[lldb/SWIG] Fix capitalization for case sensitive file systems.
When moving the Python directory I renamed it to python (lowercase) but
didn't update the python.swig file.
The file was modifiedlldb/bindings/python.swig
Commit 06d07ec4a372b55e6fb77bf0b97964bde16a3184 by simon.tatham
[Clang] Handle target-specific builtins returning aggregates.
Summary: A few of the ARM MVE builtins directly return a structure type.
This causes an assertion failure at code-gen time if you try to assign
the result of the builtin to a variable, because the `RValue` created in
`EmitBuiltinExpr` from the `llvm::Value` produced by codegen is always
made by `RValue::get()`, which creates a non-aggregate `RValue` that
will fail an assertion when `AggExprEmitter::withReturnValueSlot` calls
`Src.getAggregatePointer()`. A similar failure occurs if you try to use
the struct return value directly to extract one field, e.g.
`vld2q(address).val[0]`.
The existing code-gen tests for those MVE builtins pass the returned
structure type directly to the C `return` statement, which apparently
managed to avoid that particular code path, so we didn't notice the
crash.
Now `EmitBuiltinExpr` checks the evaluation kind of the builtin's return
value, and does the necessary handling for aggregate returns. I've added
two extra test cases, both of which crashed before this change.
Reviewers: dmgreen, rjmccall
Reviewed By: rjmccall
Subscribers: kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D72271
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vld24.c
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
Commit ed6daa2e1d32e940ac4bd8c31ae05154c5ed9bd3 by riccibrun
[Support][NFC] Add a comment about the semantics of MF_HUGE_HINT flag
The file was modifiedllvm/include/llvm/Support/Memory.h
Commit 356b33516c2e0ef241066dded16d7ecc1f7aa8cc by simon.moll
[NFC,format] Sort switch cases alphabetically
This patch brings the switch cases of `llvm/lib/Support/Triple.cpp` back
into alphabetical order. This was noted during the the review of
https://reviews.llvm.org/D69103
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D72452
The file was modifiedllvm/lib/Support/Triple.cpp
Commit 2fe45e029ddfa65880cfe5c3501db12a81cdcbd2 by riccibrun
[Support][NFC] Make some helper functions "static" in Memory.inc
The file was modifiedllvm/lib/Support/Unix/Memory.inc
The file was modifiedllvm/lib/Support/Windows/Memory.inc
Commit 7bbd4076c1984165568c978ff15b77dbfe52b6f0 by Jonas Devlieghere
[lldb/SWIG] Undo incorrect substitution
The Python directory for the script interpreter is still capitalized.
The file was modifiedlldb/bindings/python.swig
Commit b51fa8670f3d9346cad068aa7300d63eb051069d by ulrich.weigand
[SystemZ] Fix matching another pattern for nxgrk (PR44496)
SystemZDAGToDAGISel::Select will attempt to split logical instruction
with a large immediate constant.  This must not happen if the result
matches one of the z15 combined operations, so the code checks for
those.  However, one of them was missed, causing invalid code to be
generated in the test case for PR44496.
The file was modifiedllvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
The file was modifiedllvm/test/CodeGen/SystemZ/not-01.ll
Commit 460cbabe170e481d4468ef77de1fb08b02a0f2a3 by spatel
[x86] add tests for 2-way splat copy; NFC
Based on code in PR42024: https://bugs.llvm.org/show_bug.cgi?id=42024
The file was modifiedllvm/test/CodeGen/X86/vector-interleave.ll
Commit 002be6cfa2b1de064d672dac6db53c01e9f150b0 by riccibrun
[Support][NFC] Add an explicit unit test for Process::getPageSize()
It turns out that it was only tested indirectly. For now test only on
Linux X86-64 and aarch64.
The file was modifiedllvm/unittests/Support/ProcessTest.cpp
Commit b705fe5686a886e200fd57410c6bc9bad5c21c0e by craig.topper
[TargetLowering][X86] TeachSimplifyDemandedBits to handle cases where
only the sign bit is demanded from a SETCC and can be passed through
If we're doing a compare that only tests the sign bit and only the sign
bit is demanded, we can just bypass the node. This removes one of the
blend dependencies in our v2i64->v2f32 uint_to_fp codegen on pre-sse4.2
targets.
Differential Revision: https://reviews.llvm.org/D72356
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/vec_int_to_fp.ll
Commit 183b5d38d7cffc10ff9f4914b8879ed5b1976e40 by erik.pilkington
[demangle] Copy back some NFC commits from LLVM
The file was modifiedlibcxxabi/src/demangle/ItaniumDemangle.h
The file was modifiedlibcxxabi/src/demangle/Utility.h
Commit 1a1dbea24df51e441f3517abb8e251df0029dad7 by sd.fertile
[PowerPC] The VK_PLT symbolref modifier is only used on 32-bit ELF.
[NFC]
Fix a conditional that guarded code for execution only on 32-bit ELF by
checking that the Subtarget was not 64-bit and not-Darwin. By adding a
new target ABI (AIX), the condition is no longer correct. This code is
dead for AIX, due to a 'report_fatal_error' for thread local storage
usage earlier in the pipeline, but needs to be modifed as part of
Darwins removal from the PowerPC backend.
The file was modifiedllvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
Commit 3408940f736955402b7676e3b8bab6906cc82637 by Ganesh.Gopalasubramanian
[X86] AMD Znver2 (Rome) Scheduler enablement
The patch gives out the details of the znver2 scheduler model. There are
few improvements with respect to execution units, latencies and
throughput when compared with znver1. The tests that were present for
znver1 for llvm-mca tool were replicated. The latencies, execution
units, timeline and throughput information are updated for znver2.
Reviewers: craig.topper, Simon Pilgrim
Differential Revision: https://reviews.llvm.org/D66088
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-movbe.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update-2.s
The file was modifiedllvm/test/tools/llvm-mca/X86/sqrt-rsqrt-rcp-memop.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-clflushopt.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-adx.s
The file was modifiedllvm/test/tools/llvm-mca/X86/read-after-ld-1.s
The file was modifiedllvm/test/tools/llvm-mca/X86/read-after-ld-2.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-cmpxchg.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update-3.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-x86_32.s
The file was modifiedllvm/test/MC/X86/x86_long_nop.s
The file was modifiedllvm/test/tools/llvm-mca/X86/variable-blend-read-after-ld-1.s
The file was modifiedllvm/lib/Target/X86/X86InstrInfo.td
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-ssse3.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-x87.s
The file was modifiedllvm/test/tools/llvm-mca/X86/fma3-read-after-ld-2.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update-7.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-pclmul.s
The file was modifiedllvm/lib/Target/X86/X86.td
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver1/resources-clzero.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-mwaitx.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-sse4a.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-aes.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-sse42.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-sse41.s
The file was modifiedllvm/test/tools/llvm-mca/X86/cpus.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-sse3.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-popcnt.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update-4.s
The file was modifiedllvm/test/tools/llvm-mca/X86/variable-blend-read-after-ld-2.s
The file was modifiedllvm/test/tools/llvm-mca/X86/register-file-statistics.s
The file was modifiedllvm/test/tools/llvm-mca/X86/scheduler-queue-usage.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Generic/resources-clzero.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-prefetchw.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-avx1.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-lzcnt.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-rdrand.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update-6.s
The file was modifiedllvm/test/tools/llvm-mca/X86/bzhi-read-after-ld.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-clzero.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-sse2.s
The file was addedllvm/lib/Target/X86/X86ScheduleZnver2.td
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-mmx.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-cmov.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-bmi2.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-f16c.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-lea.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-sha.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-fma.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-avx2.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-bmi1.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-fsgsbase.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-x86_64.s
The file was modifiedllvm/test/tools/llvm-mca/X86/fma3-read-after-ld-1.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-sse1.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-rdseed.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update-5.s
The file was modifiedllvm/test/tools/llvm-mca/X86/bextr-read-after-ld.s
Commit 1c545f6dbcbb3ada2dfef2c6afbc1ca8939135cb by epastor
[ms] [X86] Use "P" modifier on all branch-target operands in inline X86
assembly.
Summary: Extend D71677 to apply to all branch-target operands, rather
than special-casing call instructions.
Also add a regression test for llvm.org/PR44272, since this finishes
fixing it.
Reviewers: thakis, rnk
Reviewed By: thakis
Subscribers: merge_guards_bot, hiraditya, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D72417
The file was modifiedclang/test/CodeGen/ms-inline-asm-64.c
The file was modifiedllvm/include/llvm/MC/MCParser/MCParsedAsmOperand.h
The file was modifiedllvm/lib/Target/X86/X86InstrInfo.td
The file was modifiedllvm/lib/Target/X86/AsmParser/X86Operand.h
The file was modifiedllvm/lib/MC/MCParser/AsmParser.cpp
The file was modifiedllvm/include/llvm/MC/MCInstrDesc.h
The file was modifiedllvm/utils/TableGen/X86RecognizableInstr.cpp
The file was modifiedllvm/utils/TableGen/InstrInfoEmitter.cpp
The file was modifiedllvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
The file was modifiedllvm/lib/Target/X86/X86InstrControl.td
Commit b35f5d4914c979282010c0618a331d11a58493ac by sguelton
[clang] Enforce triple in mempcpy test
Fixes
http://lab.llvm.org:8011/builders/llvm-clang-win-x-armv7l/builds/2597
The file was modifiedclang/test/CodeGen/mempcpy-libcall.c
Commit 9949b1a1753aa0f229c5b55ea01ec96f48164d9e by Jessica Paquette
[GlobalISel][AArch64] Import + select LDR*roW and STR*roW patterns
This adds support for selecting a large chunk of the load/store *roW
patterns.
This is pretty much a straight port of
AArch64DAGToDAGISel::SelectAddrModeWRO into GISel. The code is very
similar to the XRO code. The main difference is that in the *roW
patterns, we want to try and fold in an extend, and *possibly* a shift
along with it. A good portion of this patch is refactoring the existing
XRO code.
- Add selectAddrModeWRO
- Factor out the code from selectAddrModeShiftedExtendXReg which is used
by both
selectAddrModeXRO and selectAddrModeWRO into selectExtendedSHL.
This is similar to the function of the same name in
AArch64DAGToDAGISel.
- Add support for extends to the factored out code in selectExtendedSHL.
- Teach getExtendTypeForInst how to handle AND masks that are intended
to be
used in loads/stores (necessary for this addressing mode.)
- Make getExtendTypeForInst not static because moving it made an
annoying diff
and I wanted to have the WRO/XRO functions close to each other while I
was
writing the code.
Differential Revision: https://reviews.llvm.org/D72426
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/load-wro-addressing-modes.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/store-wro-addressing-modes.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrFormats.td
Commit 4e003aad42d985dade66cd5928d64dd09edecceb by craig.topper
[X86] Add ueq/one fp128 quiet compare tests. NFC
The ONE expansion calls OGT/OLT libcalls which will signal for QNAN. The
UEQ expansion uses unord and eq libcalls which won't signal. We should
probably use those libcalls for ONE with appropriate logic.
Quiet OGT/OLT/OLE/OGE have similar issue, but not sure how to fix those
yet.
The file was modifiedllvm/test/CodeGen/X86/fp128-compare.ll
The file was modifiedllvm/test/CodeGen/X86/fp128-libcalls-strict.ll
Commit 1444e6e2e6f6b76cc9d5aab8b1877926aa6d5597 by Alexander.Richardson
Re-apply "[ELF] Allow getErrPlace() to work before Out::bufferStart is
set"
This time with a fix for the UBSAN failure.
Differential Revision: https://reviews.llvm.org/D70659
The file was modifiedlld/test/ELF/mips-jalr-non-functions.s
The file was modifiedlld/ELF/Target.cpp
Commit 646ca7d7e72e8408b3fa3472018eb9d1c2643ff5 by Alexander.Richardson
MipsDelaySlotFiller: Update registers def-uses for BUNDLE instructions
Summary: In commit b91f239485fb7bb8d29be3e0b60660a2de7570a9 I updated
the MipsDelaySlotFiller to skip BUNDLE instructions. However, in
addition to not considering BUNDLE instructions for the delay slot, we
also need to ensure that the register def-use information is updated.
Not updating this information caused run-time crashes (when using the
out-of-tree CHERI backend) since later definitions could be overwritten
with earlier register values.
Reviewers: atanasyan Reviewed By: atanasyan Differential Revision:
https://reviews.llvm.org/D72254
The file was addedllvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts-def-use.mir
The file was modifiedllvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
Commit fc3367dd5ed4698036c421b23cf4f52cf8aedcae by riverriddle
[mlir] NFC: Move the state for managing SSA value names out of
OperationPrinter and into a new class SSANameState.
Summary: This reduces the complexity of OperationPrinter and simplifies
the code by quite a bit. The SSANameState is now held by ModuleState.
This is in preparation for a future revision that molds ModuleState into
something that can be used by users for caching the printer state, as
well as for implementing printAsOperand style methods.
Depends On D72292
Reviewed By: antiagainst
Differential Revision: https://reviews.llvm.org/D72293
The file was modifiedmlir/lib/IR/AsmPrinter.cpp
Commit 61bd19206f61ace4b007838a2ff8884a13ec0374 by eric
[libc++] Explicitly enumerate std::string external instantiations.
The external instantiation of std::string is a problem for libc++.
   Additions and removals of inline functions in string can cause ABI
   breakages, including introducing new symbols.
    This patch aims to:
     (1) Make clear which functions are explicitly instatiated.
     (2) Prevent new functions from being accidentally instantiated.
     (3) Allow a migration path for adding or removing functions from
the
     explicit instantiation over time.
    Although this new formulation is uglier, it is preferable from a
   maintainability and readability standpoint because it explicitly
   enumerates the functions we've chosen to expose in our ABI. Changing
   this list is non-trivial and requires thought and planning.
    (3) is achieved by making it possible to control the extern template
declaration
   separately from it's definition. Meaning we could add a new
definition to
   the dylib, wait for it to roll out, then add the extern template
   declaration to the header. Similarly, we could remove existing extern
   template declarations while still keeping the definition to prevent
ABI
   breakages.
The file was modifiedlibcxx/include/string
The file was modifiedlibcxx/include/__string
The file was modifiedlibcxx/include/__config
The file was modifiedlibcxx/src/string.cpp
Commit c348a2674b5753afde6842d5a6ee75db111167e3 by sledru
[clang-tidy] Refresh the add_new_check.py now that we use a table +
autofix
Reviewers: alexfh
Reviewed By: alexfh
Subscribers: njames93, xazax.hun, mgorny, cfe-commits
Tags: #clang, #clang-tools-extra
Differential Revision: https://reviews.llvm.org/D72421
The file was modifiedclang-tools-extra/clang-tidy/add_new_check.py
Commit 6a69d3c6b3da3d4e7709d11fd52b8e5540265280 by zeratul976
[clangd] Handle DeducedTemplateSpecializationType in TargetFinder
Summary: This is a workaround for
https://bugs.llvm.org/show_bug.cgi?id=42914. Once that is fixed, the
handling in VisitDeducedTyped() should be sufficient.
Fixes https://github.com/clangd/clangd/issues/242
Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, kadircet,
usaxena95, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D72119
The file was modifiedclang-tools-extra/clangd/FindTarget.cpp
The file was modifiedclang-tools-extra/clangd/unittests/FindTargetTests.cpp
Commit 004ae200a5a818ea87d71e4e686939dec4a8d757 by sledru
phab doc: remove the svn section
The file was modifiedllvm/docs/Phabricator.rst
Commit dbfc516d1f1685b4d11910bceab6625ada4399a2 by sledru
phab doc: also document 'arc land'
The file was modifiedllvm/docs/Phabricator.rst
Commit 0c195ef7c62db1234e3854f8798e1ef413808b18 by sledru
phab doc: Replace or remove references to svn
The file was modifiedllvm/docs/Phabricator.rst
Commit 35ad66fae811c36823b2b91368f142c9d35b8414 by arsenm2
AMDGPU/GlobalISel: Widen 16-bit shift amount sources
This should be legal, but will require future selection work. 16-bit
shift amounts were already removed from being legal, but this didn't
adjust the transformation rules.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
Commit 767aa507a464e46b9a5aaed8cfec0a621f8fc599 by arsenm2
AMDGPU/GlobalISel: Fix argument lowering for vectors of pointers
When these arguments are broken down by the EVT based callbacks, the
pointer information is lost. Hack around this by coercing the register
types to be the expected pointer element type when building the remerge
operations.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
Commit fba1fbb9c7367990a0561a36dbf600fc51847246 by arsenm2
GlobalISel: Don't assert on MoreElements creating vectors
If the original type was a scalar, it should be valid to add elements to
turn it into a vector.
Tests included with following legalization change.
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp
Commit f937b43fdb30b67facf616ad394976b08001ee89 by arsenm2
TableGen/GlobalISel: Address fixme
Don't call computeAvailableFunctionFeatures for every instruction.
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp
The file was modifiedllvm/test/TableGen/GlobalISelEmitter.td
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
Commit 595ac8c46ea54c6d5dc96e2f35a5759988a657be by arsenm2
GlobalISel: Move getLLTForMVT/getMVTForLLT
As an intermediate step, some TLI functions can be converted to using
LLT instead of MVT. Move this somewhere out of GlobalISel so DAG
functions can use these.
The file was modifiedllvm/include/llvm/CodeGen/LowLevelType.h
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/Utils.h
The file was modifiedllvm/lib/CodeGen/LowLevelType.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/Utils.cpp
Commit 0f5f28d000f73b4d0282c579477a4e31402a863e by csigg
Add gdb pretty printer for MutableArrayRef, remove ConstArrayRef.
Reviewers: dblaikie
Reviewed By: dblaikie
Subscribers: merge_guards_bot, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72136
The file was modifiedllvm/utils/gdb-scripts/prettyprinters.py
Commit 8c387cbea76b169f1f8ecc7693797e96567ed896 by Alexander.Richardson
Add builtins for aligning and checking alignment of pointers and
integers
This change introduces three new builtins (which work on both pointers
and integers) that can be used instead of common bitwise arithmetic:
__builtin_align_up(x, alignment), __builtin_align_down(x, alignment) and
__builtin_is_aligned(x, alignment).
I originally added these builtins to the CHERI fork of LLVM a few years
ago to handle the slightly different C semantics that we use for CHERI
[1]. Until recently these builtins (or sequences of other builtins) were
required to generate correct code. I have since made changes to the
default C semantics so that they are no longer strictly necessary (but
using them does generate slightly more efficient code). However, based
on our experience using them in various projects over the past few
years, I believe that adding these builtins to clang would be useful.
These builtins have the following benefit over bit-manipulation and
casts via uintptr_t:
- The named builtins clearly convey the semantics of the operation.
While
checking alignment using __builtin_is_aligned(x, 16) versus
((x & 15) == 0) is probably not a huge win in readably, I personally
find
__builtin_align_up(x, N) a lot easier to read than (x+(N-1))&~(N-1).
- They preserve the type of the argument (including const qualifiers).
When
using casts via uintptr_t, it is easy to cast to the wrong type or
strip
qualifiers such as const.
- If the alignment argument is a constant value, clang can check that it
is
a power-of-two and within the range of the type. Since the semantics of
these builtins is well defined compared to arbitrary bit-manipulation,
it is possible to add a UBSAN checker that the run-time value is a
valid
power-of-two. I intend to add this as a follow-up to this change.
- The builtins avoids int-to-pointer casts both in C and LLVM IR.
In the future (i.e. once most optimizations handle it), we could use
the new
llvm.ptrmask intrinsic to avoid the ptrtoint instruction that would
normally
be generated.
- They can be used to round up/down to the next aligned value for both
integers and pointers without requiring two separate macros.
- In many projects the alignment operations are already wrapped in
macros (e.g.
roundup2 and rounddown2 in FreeBSD), so by replacing the macro
implementation
with a builtin call, we get improved diagnostics for many call-sites
while
only having to change a few lines.
- Finally, the builtins also emit assume_aligned metadata when used on
pointers.
This can improve code generation compared to the uintptr_t casts.
[1] In our CHERI compiler we have compilation mode where all pointers
are implemented as capabilities (essentially unforgeable 128-bit fat
pointers). In our original model, casts from uintptr_t (which is a
128-bit capability) to an integer value returned the "offset" of the
capability (i.e. the difference between the virtual address and the base
of the allocation). This causes problems for cases such as checking the
alignment: for example, the expression `if ((uintptr_t)ptr & 63) == 0`
is generally used to check if the pointer is aligned to a multiple of 64
bytes. The problem with offsets is that any pointer to the beginning of
an allocation will have an offset of zero, so this check always succeeds
in that case (even if the address is not correctly aligned). The same
issues also exist when aligning up or down. Using the alignment builtins
ensures that the address is used instead of the offset. While I have
since changed the default C semantics to return the address instead of
the offset when casting, this offset compilation mode can still be used
by passing a command-line flag.
Reviewers: rsmith, aaron.ballman, theraven, fhahn, lebedev.ri, nlopes,
aqjune Reviewed By: aaron.ballman, lebedev.ri Differential Revision:
https://reviews.llvm.org/D71499
The file was addedclang/test/SemaCXX/builtin-align-cxx.cpp
The file was modifiedclang/lib/CodeGen/CodeGenFunction.h
The file was modifiedclang/lib/AST/ExprConstant.cpp
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was modifiedclang/docs/LanguageExtensions.rst
The file was modifiedclang/lib/Sema/SemaChecking.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticASTKinds.td
The file was modifiedclang/include/clang/Basic/Builtins.def
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was addedclang/test/CodeGen/builtin-align-array.c
The file was addedclang/test/CodeGen/builtin-align.c
The file was addedclang/test/Sema/builtin-align.c
The file was addedclang/test/CodeGen/builtin-align-assumption.c
Commit ea67737b166fc6cb5fd98874fbd2b4639b2d7ecd by zinenko
[mlir] mlir-cpu-runner test's cblas_interface should export functions on
Windows
This change fixes the build on Windows, so that cblas_interface.dll
exports functions correctly and an implib is created and installed
correctly.
Currently, LLVM cannot be consumed on Windows after it has been
installed in a location because cblas_interface.lib is not
created/installed, thus failing the import check in `LLVMExports.cmake`.
Differential Revision: https://reviews.llvm.org/D72384
The file was modifiedmlir/test/mlir-cpu-runner/include/cblas.h
The file was modifiedmlir/test/mlir-cpu-runner/include/mlir_runner_utils.h
The file was modifiedmlir/test/mlir-cpu-runner/CMakeLists.txt
The file was modifiedmlir/test/mlir-cpu-runner/cblas_interface.cpp
The file was addedmlir/test/mlir-cpu-runner/include/cblas_interface.h
Commit 016bf03ef6fcd9dce43b0c17971f76323f07a684 by zinenko
[mlir] add a missing dependency for Linalg conversion
We were seeing some occasional build failures that would come and go. It
appeared to be this missing dependence.
Differential Revision: https://reviews.llvm.org/D72419
The file was modifiedmlir/lib/Conversion/LinalgToLLVM/CMakeLists.txt
Commit cc95bb1f57c674c0efdfc134eab8ed8c50f2a6e3 by Amara Emerson
[AArch64][GlobalISel] Implement selection of <2 x float> vector splat.
Also requires making G_IMPLICIT_DEF of v2s32 legal.
Differential Revision: https://reviews.llvm.org/D72422
The file was modifiedllvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
The file was modifiedllvm/test/CodeGen/AArch64/arm64-rev.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/opt-shuffle-splat.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
Commit 255cc5a7603fef251192daab2a3336acbcd9aa1c by arsenm2
CodeGen: Use LLT instead of EVT in getRegisterByName
Only PPC seems to be using it, and only checks some simple cases and
doesn't distinguish between FP. Just switch to using LLT to simplify use
from GlobalISel.
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.h
The file was modifiedllvm/lib/Target/Mips/MipsISelLowering.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/lib/Target/Mips/MipsISelLowering.h
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.h
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
The file was modifiedllvm/lib/Target/Lanai/LanaiISelLowering.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetLowering.h
The file was modifiedllvm/lib/Target/Hexagon/HexagonISelLowering.h
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/lib/Target/Sparc/SparcISelLowering.cpp
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.h
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.h
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonISelLowering.cpp
The file was modifiedllvm/lib/Target/Lanai/LanaiISelLowering.h
The file was modifiedllvm/lib/Target/Sparc/SparcISelLowering.h
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.h
Commit ac53a5f1dc21916f1072031703e0e1833e963454 by arsenm2
GlobalISel: Fix else after return
The file was modifiedllvm/lib/CodeGen/LowLevelType.cpp
Commit f33f3d98e9e6322846c3b997260faf3e1165e0dd by arsenm2
DAG: Don't use unchecked dyn_cast
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Commit 0ea3c7291fb8d463d9c7ae6aaec7a432ef366a51 by arsenm2
GlobalISel: Handle llvm.read_register
Compared to the attempt in bdcc6d3d2638b3a2c99ab3b9bfaa9c02e584993a,
this uses intermediate generic instructions.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/read_register.ll
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
The file was modifiedllvm/include/llvm/Target/GenericOpcodes.td
The file was modifiedllvm/include/llvm/Support/TargetOpcodes.def
Commit b4a647449fa01bd4e29bce5afef51770cddec664 by arsenm2
TableGen/GlobalISel: Add way for SDNodeXForm to work on timm
The current implementation assumes there is an instruction associated
with the transform, but this is not the case for
timm/TargetConstant/immarg values. These transforms should directly
operate on a specific MachineOperand in the source instruction. TableGen
would assert if you attempted to define an equivalent GISDNodeXFormEquiv
using timm when it failed to find the instruction matcher.
Specially recognize SDNodeXForms on timm, and pass the operand index to
the render function.
Ideally this would be a separate render function type that looks like
void renderFoo(MachineInstrBuilder, const MachineOperand&), but this
proved to be somewhat mechanically painful. Add an optional operand
index which will only be passed if the transform should only look at the
one source operand.
Theoretically it would also be possible to only ever pass the
MachineOperand, and the existing renderers would check the parent. I
think that would be somewhat ugly for the standard usage which may want
to inspect other operands, and I also think MachineOperand should
eventually not carry a pointer to the parent instruction.
Use it in one sample pattern. This isn't a great example, since the
transform exists to satisfy DAG type constraints. This could also be
avoided by just changing the MachineInstr's arbitrary choice of operand
type from i16 to i32. Other patterns have nontrivial uses, but this
serves as the simplest example.
One flaw this still has is if you try to use an SDNodeXForm defined for
imm, but the source pattern uses timm, you still see the "Failed to
lookup instruction" assert. However, there is now a way to avoid it.
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ds.swizzle.mir
The file was modifiedllvm/lib/Target/ARM/ARMInstructionSelector.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUGISel.td
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.td
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
The file was addedllvm/test/TableGen/GlobalISelEmitter-SDNodeXForm-timm.td
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
The file was modifiedllvm/test/TableGen/GlobalISelEmitter.td
The file was modifiedllvm/include/llvm/Target/GlobalISel/Target.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was modifiedllvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp
The file was modifiedllvm/lib/Target/AMDGPU/DSInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
Commit 10edb1d0d4a15812a71f8953bba96a4f1fc9d0af by arsenm2
TableGen/GlobalISel: Fix pattern matching of immarg literals
For arguments that are not expected to be materialized with G_CONSTANT,
this was emitting predicates which could never match. It was first
adding a meaningless LLT check, which would always fail due to the
operand not being a register.
Infer the cases where a literal should check for an immediate operand,
instead of a register This avoids needing to invent a special way of
representing timm literal values.
Also handle immediate arguments in GIM_CheckLiteralInt. The comments
stated it handled isImm() and isCImm(), but that wasn't really true.
This unblocks work on the selection of all of the complicated AMDGPU
intrinsics in future commits.
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp
The file was modifiedllvm/utils/TableGen/CodeGenIntrinsics.h
The file was addedllvm/test/TableGen/GlobalISelEmitter-immarg-literal-pattern.td
The file was modifiedllvm/utils/TableGen/CodeGenTarget.cpp
The file was modifiedllvm/test/TableGen/Common/GlobalISelEmitterCommon.td
The file was modifiedllvm/utils/TableGen/CodeGenInstruction.cpp
The file was modifiedllvm/utils/TableGen/CodeGenInstruction.h
Commit 58b3dec6c108eb9ae4af2cde5c831743d5605c79 by Jonas Devlieghere
[lldb/Lua] Add lua typemaps for INOUT params
The file was modifiedlldb/bindings/lua.swig
The file was addedlldb/bindings/lua/lua-typemaps.swig
Commit 68c8b6c4cd117cc962155298f0e1d45056ecc001 by riverriddle
[mlir] Use getDenseElementBitwidth instead of
Type::getElementTypeBitWidth.
Summary: Some data values have a different storage width than the
corresponding MLIR type, e.g. bfloat is currently stored as a double.
Reviewed By: nicolasvasilache
Differential Revision: https://reviews.llvm.org/D72478
The file was modifiedmlir/lib/IR/Attributes.cpp
The file was modifiedmlir/unittests/IR/AttributeTest.cpp
Commit 25195541349b1d6dfc03bf7511483110bda69b29 by richard
When diagnosing the lack of a viable conversion function, also list
explicit functions that are not candidates.
It's not always obvious that the reason a conversion was not possible is
because the function you wanted to call is 'explicit', so explicitly say
if that's the case.
It would be nice to rank the explicit candidates higher in the
diagnostic if an implicit conversion sequence exists for their
arguments, but unfortunately we can't determine that without potentially
triggering non-immediate-context errors that we're not permitted to
produce.
The file was modifiedclang/test/PCH/cxx-explicit-specifier.cpp
The file was modifiedclang/test/CXX/drs/dr1xx.cpp
The file was modifiedclang/test/CXX/expr/expr.prim/expr.prim.lambda/p11-1y.cpp
The file was modifiedclang/test/CXX/drs/dr15xx.cpp
The file was modifiedclang/test/SemaCXX/copy-initialization.cpp
The file was modifiedclang/test/CXX/dcl.decl/dcl.init/p14-0x.cpp
The file was modifiedclang/lib/Sema/SemaOverload.cpp
The file was modifiedclang/test/CXX/special/class.inhctor/p3.cpp
The file was modifiedclang/test/SemaCXX/converting-constructor.cpp
The file was modifiedclang/test/SemaCXX/convert-to-bool.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/test/SemaCXX/conversion-function.cpp
The file was modifiedclang/test/SemaCXX/explicit.cpp
The file was modifiedclang/include/clang/Sema/Overload.h
The file was modifiedclang/include/clang/AST/DeclCXX.h
The file was modifiedclang/lib/Sema/SemaInit.cpp
The file was modifiedclang/test/CXX/basic/basic.lookup/basic.lookup.qual/namespace.qual/p2.cpp
The file was modifiedclang/test/CXX/dcl.decl/dcl.init/dcl.init.ref/p5.cpp
The file was modifiedclang/test/CXX/over/over.match/over.match.funcs/over.match.copy/p1.cpp
The file was modifiedclang/test/SemaCXX/default1.cpp
The file was modifiedclang/test/SemaCXX/cxx2a-explicit-bool.cpp
Commit 5fe4679cc9cfb4941b766db07bf3cd928075d204 by arsenm2
AVR: Update for getRegisterByName change
The file was modifiedllvm/lib/Target/AVR/AVRISelLowering.cpp
The file was modifiedllvm/lib/Target/AVR/AVRISelLowering.h
Commit b81c8c6976b987a25fc54fa2bf3524919759a898 by Jonas Devlieghere
[lldb] Remove spurious file
The file was removedlldb/lldb/cmake/modules/FindPythonInterpAndLibs.cmake
Commit cd69e4c74c174101817c9f6b7c02374ac6a7476f by Stanislav.Mekhanoshin
[AMDGPU] Fix bundle scheduling
Bundles coming to scheduler considered free, i.e. zero latency. Fixed.
Differential Revision: https://reviews.llvm.org/D72487
The file was modifiedllvm/test/CodeGen/AMDGPU/setcc-opt.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/uint_to_fp.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/misched-killflags.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/packed-op-sel.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/zero_extend.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/sub.i16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/selectcc-opt.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/min.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/sint_to_fp.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.init.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/wave32.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.h
The file was modifiedllvm/test/CodeGen/AMDGPU/scratch-simple.ll
Commit 02113918ed6b5e514afd7d1e007131d36ac13f1d by Jason Molenda
When reading Aux file in chunks, read consecutive byte ranges
qemu has a very small maximum packet size (4096) and it actually only
uses half of that buffer for some implementation reason, so when lldb
asks for the register target definitions, the x86_64 definition is
larger than 4096/2 and we need to fetch it in two parts.
This patch and test is fixing a bug in
GDBRemoteCommunicationClient::ReadExtFeature when reading a target file
in multiple parts.  lldb was assuming that it would always get back the
maximum packet size response (4096) instead of using the actual size
received and asking for the next group of bytes.
We now have two tests in gdb_remote_client for unique features of qemu -
TestNestedRegDefinitions.py would test the ability of lldb to follow
multiple levels of xml includes; I opted to create a separate
TestRegDefinitionInParts.py test to test this wrinkle in qemu's gdb
remote serial protocol stub implementation. Instead of combining both
tests into a single test file.
<rdar://problem/49537922>
The file was modifiedlldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
The file was addedlldb/packages/Python/lldbsuite/test/functionalities/gdb_remote_client/TestRegDefinitionInParts.py
Commit 375371cc8bff7ba02d0a2203f80de5e640fcadf1 by maskray
[ELF] Fix includeInDynsym() when an undefined weak is merged with a lazy
definition
An undefined weak does not fetch the lazy definition. A lazy weak symbol
should be considered undefined, and thus preemptible if .dynsym exists.
D71795 is not quite an NFC. It errors on an R_X86_64_PLT32 referencing
an undefined weak symbol. isPreemptible is false (incorrect) => R_PLT_PC
is optimized to R_PC => in isStaticLinkTimeConstant, an error is emitted
when an R_PC is applied on an undefined weak (considered absolute).
The file was modifiedlld/test/ELF/weak-undef-lib.s
The file was modifiedlld/ELF/Symbols.cpp
Commit 5cabb8357aeb3bbecaef4825c3a594f86ef94c8d by arsenm2
AMDGPU/GlobalISel: Fix G_EXTRACT_VECTOR_ELT mapping for s-v case
If an SGPR vector is indexed with a VGPR, the actual indexing will be
done on the SGPR and produce an SGPR. A copy needs to be inserted inside
the waterwall loop to the VGPR result.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
Commit 35c3d101aee240f6c034f25ff6800fda22a89987 by arsenm2
AMDGPU/GlobalISel: Select G_EXTRACT_VECTOR_ELT
Doesn't try to do the fold into the base register of an add of a
constant in the index like the DAG path does.
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
Commit 3727ca313783e23696caeae53c688409555ab0fc by douglas.yung
Relax opcode checks in test for G_READCYCLECOUNTER to check for only a
number instead of a specific number.
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
Commit f041e9ad706aee7987c5299427c33424fcabbd0d by richard
CWG2352: Allow qualification conversions during reference binding.
The language wording change forgot to update overload resolution to rank
implicit conversion sequences based on qualification conversions in
reference bindings. The anticipated resolution for that oversight is
implemented here -- we order candidates based on qualification
conversion, not only on top-level cv-qualifiers, including ranking
reference bindings against non-reference bindings if they differ in
non-top-level qualification conversions.
For OpenCL/C++, this allows reference binding between pointers with
differing (nested) address spaces. This makes the behavior of reference
binding consistent with that of implicit pointer conversions, as is the
purpose of this change, but that pre-existing behavior for pointer
conversions is itself probably not correct. In any case, it's now
consistently the same behavior and implemented in only one place.
This reinstates commit de21704ba96fa80d3e9402f12c6505917a3885f4,
reverted in commit d8018233d1ea4234de68d5b4593abd773db79484, with
workarounds for some overload resolution ordering problems introduced by
CWG2352.
The file was modifiedclang/test/SemaOpenCL/address-spaces-conversions-cl2.0.cl
The file was modifiedclang/www/make_cxx_dr_status
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/lib/Sema/SemaExprCXX.cpp
The file was modifiedclang/test/CXX/drs/dr4xx.cpp
The file was modifiedclang/test/CXX/drs/dr23xx.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/lib/Sema/SemaOverload.cpp
The file was modifiedclang/lib/Sema/SemaInit.cpp
The file was modifiedclang/test/SemaObjCXX/arc-overloading.mm
The file was modifiedclang/test/SemaCXX/ref-init-ambiguous.cpp
The file was modifiedclang/www/cxx_dr_status.html
Commit 02c5983310dcd627aecb521e03a16122f42e8a01 by shengchen.kan
[NFC] Style cleanup
The file was modifiedllvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp