FailedChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [BPF] Fix a bug for __builtin_preserve_field_info() processing (details)
  2. [AMDGPU][NFC] Remove redundant condition (details)
  3. [Hexagon][NFC] Remove redundant condition (details)
  4. [LLDB][NFC] Remove redundant condition (details)
  5. [LLDB][Clang Integration][NFC] Remove redundant condition (details)
  6. [Sema][NFC] Remove Redundant Condition (details)
  7. [clang-tidy] New util `Aliasing` factored out from `bugprone-infinite-loop` (details)
  8. [Analyzer] Fix errors in iterator modeling (details)
  9. [Analyzer] Handle pointer implemented as iterators in iterator checkers (details)
  10. [gn build] Port 4da65c2920b (details)
  11. [clang][CrossTU] Invalidate parent map after get cross TU definition. (details)
  12. [Alignment][NFC] Migrate MachineFrameInfo::CreateStackObject to Align (details)
  13. Correctly track GCOVProfiling IR update (details)
  14. [ARM][LowOverheadLoops] Handle reductions (details)
  15. [AMDGPU] Spill more than wavesize CSR SGPRs (details)
  16. [ThinLTO] Always parse module level inline asm with At&t dialect (PR46503) (details)
  17. [clangd] Config: compile Fragment -> CompiledFragment -> Config (details)
  18. [analyzer][CrossTU] Lower CTUImportThreshold default value (details)
  19. [gn build] Port f12cd99c440 (details)
  20. [SVE] Relax merge requirement for IR based divides. (details)
  21. [AMDGPU] Correct AMDGPUUsage.rst DW_AT_LLVM_lane_pc example (details)
  22. [NFC][ARM] Add test. (details)
  23. [lldb] Scalar re-fix UB in float->int conversions (details)
  24. [Alignment][NFC] Migrate MachineFrameInfo::CreateSpillStackObject to Align (details)
  25. [DebugInfo] Do not emit entry values for composite locations (details)
  26. [llvm-readobj] - Simplify and refine hash table tests (details)
  27. [llvm-readobj] - Don't crash when checking the number of dynamic symbols. (details)
  28. [clangd] Fix name conflict again, unbreak GCC. NFC (details)
  29. [AArch64][SVE] Add reg+imm addressing mode for unpredicated loads (details)
  30. AMDGPU/GlobalISel: Select init_exec intrinsic (details)
  31. [StackSafety,NFC] Remove unneded constexpr (details)
  32. [StackSafety,NFC] Remove expensive assert (details)
  33. [Driver][ARM] parse version of arm/thumb architecture correctly (details)
  34. [lldb/api] Improve error reporting in SBBreakpoint::AddName (NFCI) (details)
  35. Revert "[lldb/api] Improve error reporting in SBBreakpoint::AddName (NFCI)" (details)
  36. [lldb/api] Improve error reporting in SBBreakpoint::AddName (NFCI) (details)
  37. [clangd] Set gRPC deadlines to all remote index requests (details)
  38. [Analyzer] Quick fix for broken tests on Windows (details)
  39. [RISCV][NFC] Add Test for (select (or B1, B2), X, Y) (details)
  40. [RISCV] Implement Hooks to avoid chaining SELECT (details)
  41. AttrBuilder::merge/remove - use const& for iterator values in for-range loops. (details)
  42. Fix Wdocumentation warnings due to outdated parameter list. NFC. (details)
  43. Fix Wdocumentation warnings by only tagging a param id once per doxygen comment block. NFC. (details)
  44. [X86][SSE] Add test showing incorrect sign-extension by targetShrinkDemandedConstant (details)
  45. [llvm-size] Output REL, RELA and STRTAB sections when allocatable (details)
  46. [X86][SSE] Fix targetShrinkDemandedConstant constant vector sign extensions (details)
  47. Pass stripNonLineTableDebugInfo remapDebugLoc lambda DebugLoc arg by const reference not value. (details)
  48. [PowerPC] Fix for PC Relative call protocol (details)
  49. Pass DIEnumerator APInt args by const reference not value. (details)
  50. [llvm-readobj] - Simplify the symbols.test (details)
  51. [clang-tidy] fix cppcoreguidelines-init-variables with catch variables (details)
  52. Revert "[StackSafety,NFC] Remove unneded constexpr" (details)
  53. [lldb] Add basic -flimit-debug-info support to expression evaluator (details)
  54. [mlir][Linalg] Add an option to use Alloca instead of malloc/free pairs. (details)
  55. [lldb] Fix NSDate test after Scalar change (details)
  56. [CodeGen] Fix up warnings in visitEXTRACT_SUBVECTOR (details)
  57. Implement AVX ABI Warning/error (details)
  58. [cmake][Windows] Add libpath to CMAKE_MODULE_LINKER_FLAGS too (details)
  59. [Alignment][NFC] Migrate TargetTransformInfo::CreateVariableSizedObject to Align (details)
  60. [Alignment][NFC] Transition and simplify calls to DL::getABITypeAlignment (details)
  61. [Alignment] TargetLowering::hasPairedLoad must use Align for RequiredAlignment (details)
  62. Limit x86 test to require target to fix buildbot (from 2831a317b) (details)
  63. [RISCV] Temporarily move riscv-expand-pseudo pass to PreEmitPass2 (details)
  64. [clangd] Fix race in FileIndex that sometimes temporarily lost updates. (details)
  65. [VE] Support symbol with offset value (details)
  66. [lldb] Attempt to fix TestLimitDebugInfo on windows (details)
  67. Revert "[RISCV] Temporarily move riscv-expand-pseudo pass to PreEmitPass2" (details)
  68. [lldb] Replace StringConvert with llvm::to_integer when parsing integer values in CommandObjects (details)
  69. [RISCV] Temporarily move riscv-expand-pseudo pass to PreEmitPass2 (details)
  70. [RISCV] Add mcountinhibit CSR (details)
Commit 7f6bc84a97f617f9cf148a96ce72567cfa6066f9 by yhs
[BPF] Fix a bug for __builtin_preserve_field_info() processing

Andrii discovered a problem where a simple case similar to below
will generate wrong relocation kind:
  enum { FIELD_EXISTENCE = 2, };
  struct s1 { int a1; };
  int test() {
    struct s1 *v = 0;
    return __builtin_preserve_field_info(v[0], FIELD_EXISTENCE);
  }
The expected relocation kind should be FIELD_EXISTENCE, but
recorded reloc kind in the final object file is FIELD_BYTE_OFFSET,
which is incorrect.

This exposed a bug in generating access strings from intrinsics.
The current access string generation has two steps:
  step 1: find the base struct/union type,
  step 2: traverse members in the base type.

The current implementation relies on at lease one member access
in step 2 to get the correct relocation kind, which is true
in typical cases. But if there is no member accesses, the current
implementation falls to the default info kind FIELD_BYTE_OFFSET.
This is incorrect, we should still record the reloc kind
based on the user input. This patch fixed this issue by properly
recording the reloc kind in such cases.

Differential Revision: https://reviews.llvm.org/D82932
The file was addedllvm/test/CodeGen/BPF/CORE/intrinsic-array-2.ll
The file was modifiedllvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp
Commit 71c6a36018dd3e3a8f709d4a6f81a6d3ce56d780 by adam.balogh
[AMDGPU][NFC] Remove redundant condition

Condition `LiteralCount` is checked both in an outer and in an inner
`if` statement in `SIInstrInfo::verifyInstruction()`. This patch removes
the redundant inner check.

The issue was found using `clang-tidy` check under review
`misc-redundant-condition`. See https://reviews.llvm.org/D81272.

Differential Revision: https://reviews.llvm.org/D82555
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Commit ec5ba353fab79d2201f63485117682756da31d46 by adam.balogh
[Hexagon][NFC] Remove redundant condition

Condition `secondReg` is checked both in an outer and in an inner `if`
statement in static function `canCompareBeNewValueJump()` in file
`HexagonNewValueJump.cpp`. This patch removes the redundant inner check.

The issue was found using `clang-tidy` check under review
`misc-redundant-condition`. See https://reviews.llvm.org/D81272.

Differential Revision: https://reviews.llvm.org/D82556
The file was modifiedllvm/lib/Target/Hexagon/HexagonNewValueJump.cpp
Commit 1b2d2d70e1ec161878a78d880fb8972550b88185 by adam.balogh
[LLDB][NFC] Remove redundant condition

Condition `auto_advance_pc` is checked both in an outer and in an
inner `if` statement in `EmulateInstructionARM::EvaluateInstruction()`,
`EmulateInstructionARM64::EvaluateInstruction()` and
`EmulateInstructionPPC64::EvaluateInstruction()`. This patch removes the
redundant inner check.

The issue was found using `clang-tidy` check under review
`misc-redundant-condition`. See https://reviews.llvm.org/D81272.

Differential Revision: https://reviews.llvm.org/D82558
The file was modifiedlldb/source/Plugins/Instruction/ARM64/EmulateInstructionARM64.cpp
The file was modifiedlldb/source/Plugins/Instruction/PPC64/EmulateInstructionPPC64.cpp
The file was modifiedlldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp
Commit ff2d09148c91784c35b43c52f14b1501f38dd4c5 by adam.balogh
[LLDB][Clang Integration][NFC] Remove redundant condition

Condition `omit_empty_base_classes` is checked both in an outer and
in an inner `if` statement in `TypeSystemClang::GetNumBaseClasses()`.
This patch removes the redundant inner check.

The issue was found using `clang-tidy` check under review
`misc-redundant-condition`. See https://reviews.llvm.org/D81272.

Differential Revision: https://reviews.llvm.org/D82559
The file was modifiedlldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
Commit 40c50bdee443dd48424ac7d724ced8874c40ee33 by adam.balogh
[Sema][NFC] Remove Redundant Condition

Condition `TypeQuals` is checked both in an outer and in an inner `if`
statement in static function `ConvertDeclSpecToType()` in file
`SemaType.cpp`. This patch removes the redundant inner check.

The issue was found using `clang-tidy` check under review
`misc-redundant-condition`. See https://reviews.llvm.org/D81272.

Differential Revision: https://reviews.llvm.org/D82563
The file was modifiedclang/lib/Sema/SemaType.cpp
Commit 4da65c2920b68a1cf47054a7d655cc2a19a4aa28 by adam.balogh
[clang-tidy] New util `Aliasing` factored out from `bugprone-infinite-loop`

Function `hasPtrOrReferenceInfFunc()` of `bugprone-infinite-loop` is a
generic function which could be reused in another checks. This patch
moves this function into a newly created utility module.

Differential Revision: https://reviews.llvm.org/D81396
The file was addedclang-tools-extra/clang-tidy/utils/Aliasing.h
The file was modifiedclang-tools-extra/clang-tidy/bugprone/InfiniteLoopCheck.cpp
The file was modifiedclang-tools-extra/clang-tidy/utils/CMakeLists.txt
The file was addedclang-tools-extra/clang-tidy/utils/Aliasing.cpp
Commit ea563daae5232a03e08e43e68da813f76548f36a by adam.balogh
[Analyzer] Fix errors in iterator modeling

There is major a bug found in iterator modeling: upon adding a value
to or subtracting a value from an iterator the position of the original
iterator is also changed beside the result. This patch fixes this bug.

To catch such bugs in the future we also changed the tests to look for
regular expressions including an end-of-line symbol (`$`) so we can
prevent false matches where only the tested prefix matches.

Another minor bug is that when printing the state, all the iterator
positions are printed in a single line. This patch also fixes this.

Differential Revision: https://reviews.llvm.org/D82385
The file was modifiedclang/test/Analysis/iterator-modeling.cpp
The file was modifiedclang/lib/StaticAnalyzer/Checkers/IteratorModeling.cpp
Commit 9e63b190af76c798b06b1e3b75216abfdeb1bce3 by adam.balogh
[Analyzer] Handle pointer implemented as iterators in iterator checkers

Iterators are an abstraction of pointers and in some data structures
iterators may be implemented by pointers. This patch adds support for
iterators implemented as pointers in all the iterator checkers
(including iterator modeling).

Differential Revision: https://reviews.llvm.org/D82185
The file was modifiedclang/lib/StaticAnalyzer/Checkers/InvalidatedIteratorChecker.cpp
The file was modifiedclang/lib/StaticAnalyzer/Checkers/Iterator.cpp
The file was modifiedclang/lib/StaticAnalyzer/Checkers/IteratorModeling.cpp
The file was modifiedclang/test/Analysis/mismatched-iterator.cpp
The file was modifiedclang/lib/StaticAnalyzer/Checkers/IteratorRangeChecker.cpp
The file was modifiedclang/test/Analysis/iterator-modeling.cpp
The file was modifiedclang/test/Analysis/invalidated-iterator.cpp
The file was modifiedclang/lib/StaticAnalyzer/Checkers/MismatchedIteratorChecker.cpp
The file was modifiedclang/lib/StaticAnalyzer/Checkers/Iterator.h
The file was modifiedclang/test/Analysis/iterator-range.cpp
Commit 52e0582440c134fc8ac59e82fe05bb9baef96a66 by llvmgnsyncbot
[gn build] Port 4da65c2920b
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clang-tidy/utils/BUILD.gn
Commit f3b34466104877b024e168cac054bded6b9279a0 by 1.int32
[clang][CrossTU] Invalidate parent map after get cross TU definition.

Summary:
Parent map of ASTContext is built once. If this happens and later
the TU is modified by getCrossTUDefinition the parent map does not
contain the newly imported objects and has to be re-created.

Invalidation of the parent map is added to the CrossTranslationUnitContext.
It could be added to ASTImporter as well but for now this task remains the
responsibility of the user of ASTImporter. Reason for this is mostly that
ASTImporter calls itself recursively.

Reviewers: gamesh411, martong

Reviewed By: gamesh411

Subscribers: rnkovacs, dkrupp, Szelethus, gamesh411, martong, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D82568
The file was modifiedclang/unittests/CrossTU/CrossTranslationUnitTest.cpp
The file was modifiedclang/lib/CrossTU/CrossTranslationUnit.cpp
Commit 28de229bc63489b9346558f4f3a57b024b53962a by gchatelet
[Alignment][NFC] Migrate MachineFrameInfo::CreateStackObject to Align

This patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Differential Revision: https://reviews.llvm.org/D82894
The file was modifiedllvm/lib/Target/RISCV/RISCVFrameLowering.cpp
The file was modifiedllvm/lib/Target/XCore/XCoreMachineFunctionInfo.cpp
The file was modifiedllvm/lib/Target/Mips/MipsSEFrameLowering.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
The file was modifiedllvm/lib/Target/X86/X86FastISel.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
The file was modifiedllvm/include/llvm/CodeGen/MachineFrameInfo.h
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/lib/Target/ARC/ARCFrameLowering.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIFrameLowering.cpp
The file was modifiedllvm/lib/Target/Mips/MipsMachineFunction.cpp
The file was modifiedllvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was modifiedllvm/lib/Target/Sparc/SparcISelLowering.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCFastISel.cpp
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
Commit ffee8040534495fa739808e6c66a7fc73eca27bb by sguelton
Correctly track GCOVProfiling IR update

Differential Revision: https://reviews.llvm.org/D82742
The file was modifiedllvm/lib/Transforms/Instrumentation/GCOVProfiling.cpp
Commit 3ee580d0176f69a9f724469660f1d1805e0b6a06 by sam.parker
[ARM][LowOverheadLoops] Handle reductions

While validating live-out values, record instructions that look like
a reduction. This will comprise of a vector op (for now only vadd),
a vorr (vmov) which store the previous value of vadd and then a vpsel
in the exit block which is predicated upon a vctp. This vctp will
combine the last two iterations using the vmov and vadd into a vector
which can then be consumed by a vaddv.

Once we have determined that it's safe to perform tail-predication,
we need to change this sequence of instructions so that the
predication doesn't produce incorrect code. This involves changing
the register allocation of the vadd so it updates itself and the
predication on the final iteration will not update the falsely
predicated lanes. This mimics what the vmov, vctp and vpsel do and
so we then don't need any of those instructions.

Differential Revision: https://reviews.llvm.org/D75533
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.h
The file was modifiedllvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vector-arith-codegen.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions.ll
The file was modifiedllvm/lib/CodeGen/ReachingDefAnalysis.cpp
The file was modifiedllvm/include/llvm/CodeGen/ReachingDefAnalysis.h
Commit 91823163955859abbdcad5901d765aeae860939e by Saiyedul.Islam
[AMDGPU] Spill more than wavesize CSR SGPRs

In case of more than wavesize CSR SGPR spills, lanes of reserved VGPR were getting
overwritten due to wrap around.

Reserve a VGPR (when NumVGPRSpillLanes = 0, WaveSize, 2*WaveSize, ..) and when one
of the two conditions is true:
1. One reserved VGPR being tracked by VGPRReservedForSGPRSpill is not yet reserved.
2. All spill lanes of reserved VGPR(s) are full and another spill lane is required.

Reviewed By: arsenm, kerbowa

Differential Revision: https://reviews.llvm.org/D82463
The file was modifiedllvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
The file was addedllvm/test/CodeGen/AMDGPU/spill_more_than_wavesize_csr_sgprs.ll
Commit a8e582c8307ba1d33c05d272b5c1b755fa809b51 by hans
[ThinLTO] Always parse module level inline asm with At&t dialect (PR46503)

clang-cl passes -x86-asm-syntax=intel to the cc1 invocation so that
assembly listings produced by the /FA flag are printed in Intel dialect.
That flag however should not affect the *parsing* of inline assembly in
the program. (See r322652)

When compiling normally, AsmPrinter::emitInlineAsm is used for
assembling and defaults to At&t dialect. However, when compiling for
ThinLTO, the code which parses module level inline asm to find symbols
for the symbol table was failing to set the dialect. This patch fixes
that. (See the bug for more details.)

Differential revision: https://reviews.llvm.org/D82862
The file was modifiedllvm/lib/Object/ModuleSymbolTable.cpp
The file was addedclang/test/CodeGen/thinlto-inline-asm.c
Commit f12cd99c440a83d53a8717a9c8cdc4df41f39f3d by sam.mccall
[clangd] Config: compile Fragment -> CompiledFragment -> Config

Subscribers: mgorny, ilya-biryukov, MaskRay, jkorous, arphaman, kadircet, usaxena95, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D82612
The file was modifiedclang-tools-extra/clangd/unittests/ConfigYAMLTests.cpp
The file was modifiedclang-tools-extra/clangd/unittests/CMakeLists.txt
The file was modifiedclang-tools-extra/clangd/ConfigYAML.cpp
The file was addedclang-tools-extra/clangd/ConfigCompile.cpp
The file was modifiedclang-tools-extra/clangd/ConfigFragment.h
The file was addedclang-tools-extra/clangd/unittests/ConfigCompileTests.cpp
The file was addedclang-tools-extra/clangd/ConfigProvider.h
The file was modifiedclang-tools-extra/clangd/CMakeLists.txt
The file was addedclang-tools-extra/clangd/unittests/ConfigTesting.h
Commit 52f65323660051a5d039d475edfd4a3018682dcb by endre.fulop
[analyzer][CrossTU] Lower CTUImportThreshold default value

Summary:
The default value of 100 makes the analysis slow. Projects of considerable
size can take more time to finish than it is practical. The new default
setting of 8 is based on the analysis of LLVM itself. With the old default
value of 100 the analysis time was over a magnitude slower. Thresholding the
load of ASTUnits is to be extended in the future with a more fine-tuneable
solution that accomodates to the specifics of the project analyzed.

Reviewers: martong, balazske, Szelethus

Subscribers: whisperity, xazax.hun, baloghadamsoftware, szepet, rnkovacs, a.sidorin, mikhail.ramalho, Szelethus, donat.nagy, dkrupp, Charusso, steakhal, ASDenysPetrov, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D82561
The file was modifiedclang/test/Analysis/analyzer-config.c
The file was modifiedclang/include/clang/StaticAnalyzer/Core/AnalyzerOptions.def
Commit 9d347f6efa3018faf2fa159e25830817f4d2f41d by llvmgnsyncbot
[gn build] Port f12cd99c440
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clangd/unittests/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clangd/BUILD.gn
Commit a1aed80a35f3f775cdb1d68c4388723691abc0dd by paul.walker
[SVE] Relax merge requirement for IR based divides.

We currently lower SDIV to SDIV_MERGE_OP1. This forces the value
for inactive lanes in a way that can hamper register allocation,
however, the lowering has no requirement for inactive lanes.

Instead this patch replaces SDIV_MERGE_OP1 with SDIV_PRED thus
freeing the register allocator. Once done the only user of
SDIV_MERGE_OP1 is intrinsic lowering so I've removed the node
and perform ISel on the intrinsic directly. This also allows
us to implement MOVPRFX based zeroing in the same manner as SUB.

This patch also renames UDIV_MERGE_OP1 and [F]ADD_MERGE_OP1 for
the same reason but in the ADD cases the ISel code is already
as required.

Differential Revision: https://reviews.llvm.org/D82783
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
The file was modifiedllvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Commit 76b2d9cbebd227d42e2099a0eb89c800b945997a by Tony.Tye
[AMDGPU] Correct AMDGPUUsage.rst DW_AT_LLVM_lane_pc example

- Correct typo of DW_OP_xaddr to DW_OP_addrx in AMDGPUUsage.rst for
  DW_AT_LLVM_lane_pc example.

Change-Id: I1b0ee2b24362a0240388e4c2f044c1d4883509b9
The file was modifiedllvm/docs/AMDGPUUsage.rst
Commit f0ecfb789bb2d3de57876927e03a5c26da8419c8 by sam.parker
[NFC][ARM] Add test.
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/varying-outer-2d-reduction.ll
Commit 8270a903baf55122289499ba00a979e9c04dcd44 by pavel
[lldb] Scalar re-fix UB in float->int conversions

The refactor in 48ca15592f1 reintroduced UB when converting out-of-bounds
floating point numbers to integers -- the behavior for ULongLong() was
originally fixed in r341685, but did not survive my refactor because I
based my template code on one of the methods which did not have this
fix.

This time, I apply the fix to all float->int conversions, instead of
just the "double->unsigned long long" case. I also use a slightly
simpler version of the code, with fewer round-trips
(APFloat->APSInt->native_int vs
APFloat->native_float->APInt->native_int).

I also add some unit tests for the conversions.
The file was modifiedlldb/source/Utility/Scalar.cpp
The file was modifiedlldb/unittests/Utility/ScalarTest.cpp
Commit 7f37d8830635bf119a5f630dd3958c8f45780805 by gchatelet
[Alignment][NFC] Migrate MachineFrameInfo::CreateSpillStackObject to Align

iThis patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Differential Revision: https://reviews.llvm.org/D82934
The file was modifiedllvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
The file was modifiedllvm/include/llvm/CodeGen/MachineFrameInfo.h
Commit 85460c4ea273784dd45da558ad9a6f13a79b2d91 by david.stenberg
[DebugInfo] Do not emit entry values for composite locations

Summary:
This is a fix for PR45009.

When working on D67492 I made DwarfExpression emit a single
DW_OP_entry_value operation covering the whole composite location
description that is produced if a register does not have a valid DWARF
number, and is instead composed of multiple register pieces. Looking
closer at the standard, this appears to not be valid DWARF. A
DW_OP_entry_value operation's block can only be a DWARF expression or a
register location description, so it appears to not be valid for it to
hold a composite location description like that.

See DWARFv5 sec. 2.5.1.7:

"The DW_OP_entry_value operation pushes the value that the described
location held upon entering the current subprogram. It has two
operands: an unsigned LEB128 length, followed by a block containing a
DWARF expression or a register location description (see Section
2.6.1.1.3 on page 39)."

Here is a dwarf-discuss mail thread regarding this:

http://lists.dwarfstd.org/pipermail/dwarf-discuss-dwarfstd.org/2020-March/004610.html

There was not a strong consensus reached there, but people seem to lean
towards that operations specified under 2.6 (e.g. DW_OP_piece) may not
be part of a DWARF expression, and thus the DW_OP_entry_value operation
can't contain those.

Perhaps we instead want to emit a entry value operation per each
DW_OP_reg* operation, e.g.:

  - DW_OP_entry_value(DW_OP_regx sub_reg0),
    DW_OP_stack_value,
    DW_OP_piece 8,
  - DW_OP_entry_value(DW_OP_regx sub_reg1),
    DW_OP_stack_value,
    DW_OP_piece 8,
  [...]

The question then becomes how the call site should look; should a
composite location description be emitted there, and we then leave it up
to the debugger to match those two composite location descriptions?
Another alternative could be to emit a call site parameter entry for
each sub-register, but firstly I'm unsure if that is even valid DWARF,
and secondly it seems like that would complicate the collection of call
site values quite a bit. As far as I can tell GCC does not emit any
entry values / call sites in these cases, so we do not have something to
compare with, but the former seems like the more reasonable approach.

Currently when trying to emit a call site entry for a parameter composed
of multiple DWARF registers a (DwarfRegs.size() == 1) assert is
triggered in addMachineRegExpression(). Until the call site
representation is figured out, and until there is use for these entry
values in practice, this commit simply stops the invalid DWARF from
being emitted.

Reviewers: djtodoro, vsk, aprantl

Reviewed By: djtodoro, vsk

Subscribers: jyknight, hiraditya, fedor.sergeev, jrtc27, llvm-commits

Tags: #debug-info, #llvm

Differential Revision: https://reviews.llvm.org/D75270
The file was modifiedllvm/test/DebugInfo/Sparc/entry-value-complex-reg-expr.ll
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfExpression.h
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
Commit 917bdfaca6df575f617b0f3aa989183ab187e8ac by grimar
[llvm-readobj] - Simplify and refine hash table tests

Now we are able to have default values for macros in YAML descriptions.
I've applied it for hash table tests and also fixed few copy-paste issues
in their comments.

Differential revision: https://reviews.llvm.org/D82870
The file was modifiedllvm/test/tools/llvm-readobj/ELF/hash-histogram.test
The file was modifiedllvm/test/tools/llvm-readobj/ELF/gnuhash.test
The file was modifiedllvm/test/tools/llvm-readobj/ELF/hash-symbols.test
Commit 61f967dccabab67f9996a4fb1c6ec4fa4f23f005 by grimar
[llvm-readobj] - Don't crash when checking the number of dynamic symbols.

When we deriving the number of symbols from the DT_HASH table, we can crash when
calculate the number of symbols in the symbol table when SHT_DYNSYM
has sh_entsize == 0.

The patch fixes the issue.

Differential revision: https://reviews.llvm.org/D82877
The file was modifiedllvm/test/tools/llvm-readobj/ELF/dyn-symbols-size-from-hash-table.test
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp
Commit 7dcc3858e72666dc12240c8a4bd278775cd807ea by sam.mccall
[clangd] Fix name conflict again, unbreak GCC. NFC
The file was modifiedclang-tools-extra/clangd/unittests/ConfigTesting.h
Commit 4c6683eafc17b201fc5de17f96230be46d8ff521 by kerry.mclaughlin
[AArch64][SVE] Add reg+imm addressing mode for unpredicated loads

Reviewers: efriedma, sdesmalen, david-arm

Reviewed By: efriedma

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, danielkiss, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D82893
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was addedllvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-imm.ll
Commit 4b9ae1b7e5e052126e1be4c817ff53203d33d9d1 by petar.avramovic
AMDGPU/GlobalISel: Select init_exec intrinsic

Change imm with timm in pattern for SI_INIT_EXEC_LO and
remove regbank mappings for non register operands.

Differential Revision: https://reviews.llvm.org/D82885
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.init.exec.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
Commit 38470baa542bde038340b7d10a0ed2c25fac1bfa by Vitaly Buka
[StackSafety,NFC] Remove unneded constexpr

Differential Revision: https://reviews.llvm.org/D80908
The file was modifiedllvm/lib/IR/ModuleSummaryIndex.cpp
Commit 8180a399652a3896239b2b4e8730f8141a78a72e by Vitaly Buka
[StackSafety,NFC] Remove expensive assert

Differential Revision: https://reviews.llvm.org/D80908
The file was modifiedllvm/lib/Analysis/StackSafetyAnalysis.cpp
Commit 070acb1d1e51ffd289a46b8f93e993635d0053b7 by daniel.kiss
[Driver][ARM] parse version of arm/thumb architecture correctly

Summary:
If you execute the following commandline multiple times, the behavior was not always the same:
  clang++ --target=thumbv7em-none-windows-eabi-coff -march=armv7-m -mcpu=cortex-m7 -o temp.obj -c -x c++ empty.cpp

Most of the time the compilation succeeded, but sometimes clang reported this error:
  clang++: error: the target architecture 'thumbv7em' is not supported by the target 'thumbv7em-none-windows-eabi'

The cause of the inconsistent behavior was the uninitialized variable Version.

With these commandline arguments, the variable Version was not set by getAsInteger(),
because it cannot parse a number from the substring "7em" (of "thumbv7em").
To get a consistent behaviour, it's enough to initialize the variable Version to zero.
Zero is smaller than 7, so the comparison will be true.
Then the command always fails with the error message seen above.

By using consumeInteger() instead of getAsInteger() we get 7 from the substring "7em"
and the command does not fail.

Reviewers: compnerd, danielkiss

Reviewed By: danielkiss

Subscribers: danielkiss, kristof.beyls, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D75453
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was addedclang/test/Driver/windows-thumbv7em.cpp
Commit 56bb1d1755ae38b4e7a67f775978b18a601f215f by medismail.bennani
[lldb/api] Improve error reporting in SBBreakpoint::AddName (NFCI)

This patch improves the error reporting for SBBreakpoint::AddName by
adding a new method `SBBreakpoint::AddNameWithErrorHandling` that returns
a SBError instead of a boolean.

This way, if the breakpoint naming failed in the backend, the client
(i.e. Xcode), will be able to report the reason of that failure to the
user.

rdar://64765461

Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
The file was modifiedlldb/source/API/SBBreakpoint.cpp
The file was modifiedlldb/include/lldb/API/SBBreakpoint.h
The file was modifiedlldb/bindings/interface/SBBreakpoint.i
The file was modifiedlldb/test/API/functionalities/breakpoint/breakpoint_names/TestBreakpointNames.py
Commit a61f62a7b605a9077672b4f49021d84ed0cf12d9 by medismail.bennani
Revert "[lldb/api] Improve error reporting in SBBreakpoint::AddName (NFCI)"

This reverts commit 56bb1d1755ae38b4e7a67f775978b18a601f215f.
The file was modifiedlldb/test/API/functionalities/breakpoint/breakpoint_names/TestBreakpointNames.py
The file was modifiedlldb/include/lldb/API/SBBreakpoint.h
The file was modifiedlldb/source/API/SBBreakpoint.cpp
The file was modifiedlldb/bindings/interface/SBBreakpoint.i
Commit f70cad26121543c0a29b9a2c400b02c659210d71 by medismail.bennani
[lldb/api] Improve error reporting in SBBreakpoint::AddName (NFCI)

This patch improves the error reporting for SBBreakpoint::AddName by
adding a new method `SBBreakpoint::AddNameWithErrorHandling` that returns
a SBError instead of a boolean.

This way, if the breakpoint naming failed in the backend, the client
(i.e. Xcode), will be able to report the reason of that failure to the
user.

rdar://64765461

Differential Revision: https://reviews.llvm.org/D82879

Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
The file was modifiedlldb/test/API/functionalities/breakpoint/breakpoint_names/TestBreakpointNames.py
The file was modifiedlldb/include/lldb/API/SBBreakpoint.h
The file was modifiedlldb/source/API/SBBreakpoint.cpp
The file was modifiedlldb/bindings/interface/SBBreakpoint.i
Commit 22a3e4055f4382e8ebbf67705501e6969c6b398b by kbobyrev
[clangd] Set gRPC deadlines to all remote index requests

Summary: "TL;DR: Always set a deadline.", https://grpc.io/blog/deadlines/

Reviewers: sammccall

Reviewed By: sammccall

Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, kadircet, usaxena95, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D82844
The file was modifiedclang-tools-extra/clangd/index/remote/Client.cpp
Commit c79745ed48f3e22e9c5fdfa070bceecf7590896c by adam.balogh
[Analyzer] Quick fix for broken tests on Windows
The file was modifiedclang/test/Analysis/iterator-modeling.cpp
Commit c44266dc4816ec3df084232055ec02060eec0616 by selliott
[RISCV][NFC] Add Test for (select (or B1, B2), X, Y)

Summary:
As shown, LLVM is keen to avoid logic and introduce selects (in DAGCombiner, and
other places). This leads to control flow on RISC-V which we should attempt to
avoid.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D79267
The file was addedllvm/test/CodeGen/RISCV/select-or.ll
The file was addedllvm/test/CodeGen/RISCV/select-and.ll
Commit 7dc892661edde4eb90229dd5a14f45a1ceb08653 by selliott
[RISCV] Implement Hooks to avoid chaining SELECT

Summary:
This implements two hooks that attempt to avoid control flow for RISC-V. RISC-V
will lower SELECTs into control flow, which is not a great idea.

The hook `hasMultipleConditionRegisters()` turns off the following
DAGCombiner folds:
    select(C0|C1, x, y) <=> select(C0, x, select(C1, x, y))
    select(C0&C1, x, y) <=> select(C0, select(C1, x, y), y)

The second hook `setJumpIsExpensive` controls a flag that has a similar purpose
and is used in CodeGenPrepare and the SelectionDAGBuilder.

Both of these have the effect of ensuring more logic is done before fewer jumps.

Note: with the `B` extension, we may be able to lower select into a conditional
move instruction, so at some point these hooks will need to be guarded based on
enabled extensions.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D79268
The file was modifiedllvm/test/CodeGen/RISCV/zext-with-load-is-free.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-previous-failure.ll
The file was modifiedllvm/test/CodeGen/RISCV/select-and.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/test/CodeGen/RISCV/select-or.ll
Commit 0144f501a63e62771c7e2552334a36c36f3a3686 by llvm-dev
AttrBuilder::merge/remove - use const& for iterator values in for-range loops.

Noticed by clang-tidy performance-for-range-copy warning.
The file was modifiedllvm/lib/IR/Attributes.cpp
Commit 36aaffbf56913ebe1e3987d7d0ac76573be65cbc by llvm-dev
Fix Wdocumentation warnings due to outdated parameter list. NFC.
The file was modifiedclang/lib/CodeGen/CGDecl.cpp
Commit cfb5b144cf4686755d9e244bd425221ad88e2a63 by llvm-dev
Fix Wdocumentation warnings by only tagging a param id once per doxygen comment block. NFC.
The file was modifiedllvm/lib/Transforms/Utils/FlattenCFG.cpp
Commit 93707fe30927b19b533f04426a6614f952f49dd1 by llvm-dev
[X86][SSE] Add test showing incorrect sign-extension by targetShrinkDemandedConstant
The file was addedllvm/test/CodeGen/X86/shrink-const.ll
Commit 41ca82cbe815904173d094cb3a7789a705a73695 by gbreynoo
[llvm-size] Output REL, RELA and STRTAB sections when allocatable

gnu size has a number of special cases regarding REL, RELA and STRTAB
sections being considered in size output. To avoid unnecessary
complexity this commit makes llvm size outputs these sections in cases
they have the SHF_ALLOC flag.

Differential Revision: https://reviews.llvm.org/D82479
The file was modifiedllvm/tools/llvm-size/llvm-size.cpp
The file was addedllvm/test/tools/llvm-size/output-alloc.test
Commit b485586482af213cf04a1e97712283db1707435b by llvm-dev
[X86][SSE] Fix targetShrinkDemandedConstant constant vector sign extensions

D82257/rG3521ecf1f8a3 was incorrectly sign-extending a constant vector from the lsb, this is fine if all the constant elements are 'allsignbits' in the active bits, but if only some of the elements are, then we are corrupting the constant values for those elements.

This fix ensures we sign extend from the msb of the active/demanded bits instead.
The file was modifiedllvm/test/CodeGen/X86/shrink-const.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 2c7af6dffc0645dad561378550701e1e29b5d7e4 by llvm-dev
Pass stripNonLineTableDebugInfo remapDebugLoc lambda DebugLoc arg by const reference not value.

Noticed by clang-tidy performance-unnecessary-value-param warning.
The file was modifiedllvm/lib/IR/DebugInfo.cpp
Commit b294e00fb079600f337f479eb29fc27058228302 by kamau.bridgeman
[PowerPC] Fix for PC Relative call protocol

The situation where the caller uses a TOC and the callee does not
but is marked as clobbers the TOC (st_other=1) was not being compiled
correctly if both functions where in the same object file.

The call site where we had `callee` was missing a nop after the call.
This is because it was assumed that since the two functions where in
the same DSO they would be sharing a TOC. This is not the case if the
callee uses PC Relative because in that case it may clobber the TOC.
This patch makes sure that we add the cnop correctly so that the
linker has a place to restore the TOC.

Reviewers: sfertile, NeHuang, saghir

Differential Revision: https://reviews.llvm.org/D81126
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/ifunc.ll
The file was addedllvm/test/CodeGen/PowerPC/pcrel-local-caller-toc.ll
The file was addedllvm/test/CodeGen/PowerPC/func-alias.ll
Commit 65647ed1e5e8a74ef28f19279d329bb49741dcaa by llvm-dev
Pass DIEnumerator APInt args by const reference not value.

Noticed by clang-tidy performance-unnecessary-value-param warning.
The file was modifiedllvm/include/llvm/IR/DebugInfoMetadata.h
The file was modifiedllvm/lib/IR/DebugInfoMetadata.cpp
Commit 37dd8b6ce5f3ad6c5b9f6b5498606f8b7723e8ab by grimar
[llvm-readobj] - Simplify the symbols.test

We are able to use YAML macros to avoid having
4 independent YAML descriptions.

Differential revision: https://reviews.llvm.org/D82942
The file was modifiedllvm/test/tools/llvm-readobj/ELF/symbols.test
Commit 669494e9c06c78b51260598bba9d84ba7634a53e by n.james93
[clang-tidy] fix cppcoreguidelines-init-variables with catch variables

Ignore catch statement var decls.

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D82924
The file was modifiedclang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines-init-variables.cpp
The file was modifiedclang-tools-extra/clang-tidy/cppcoreguidelines/InitVariablesCheck.cpp
Commit e35a5876e4c7f67211dd600a3006bede2ccab25c by a.bataev
Revert "[StackSafety,NFC] Remove unneded constexpr"

This reverts commit 38470baa542bde038340b7d10a0ed2c25fac1bfa because it
breaks builds with lld and gold linkers.
The file was modifiedllvm/lib/IR/ModuleSummaryIndex.cpp
Commit a03dc8c9fa8e9c5cf44448fac1a9ad0fdad7df41 by pavel
[lldb] Add basic -flimit-debug-info support to expression evaluator

Summary:
This patch adds support for evaluation of expressions referring to types
which were compiled in -flimit-debug-info (a.k.a -fno-standalone-debug)
in clang. In this mode it's possible that the debug information needed
to fully describe a c++ type is not present in a single shared library
-- for example debug info for a base class or a member of a type can
only be found in another shared library.  This situation is not
currently handled well within lldb as we are limited to searching within
a single shared library (lldb_private::Module) when searching for the
definition of these types.

The way that this patch gets around this limitation is by doing the
search at a later stage -- during the construction of the expression ast
context. This works by having the parser (currently SymbolFileDWARF, but
a similar approach is probably needed for PDBs too) mark a type as
"forcefully completed". What this means is that the parser has marked
the type as "complete" in the module ast context (as this is necessary
to e.g. derive classes from it), but its definition is not really there.
This is done via a new field on the ClangASTMetadata struct.

Later, when we are importing such a type into the expression ast, we
check this flag. If the flag is set, we try to find a better definition
for the type in other shared libraries. We do this by initiating a
new lookup for the "forcefully completed" classes, which then imports the
type from a module with a full definition.

This patch only implements this handling for base classes, but other
cases (members, array element types, etc.). The changes for that should
be fairly simple and mostly revolve around marking these types as
"forcefully completed" at an approriate time -- the importing logic is
generic already.

Another aspect, which is also not handled by this patch is viewing these
types via the "frame variable" command. This does not use the AST
importer and so it will need to handle these types on its own -- that
will be the subject of another patch.

Differential Revision: https://reviews.llvm.org/D81561
The file was addedlldb/test/API/functionalities/limit-debug-info/Makefile
The file was addedlldb/test/API/functionalities/limit-debug-info/onetwo.h
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
The file was addedlldb/test/API/functionalities/limit-debug-info/foo.cpp
The file was modifiedlldb/source/Plugins/ExpressionParser/Clang/ClangASTImporter.cpp
The file was modifiedlldb/source/Plugins/ExpressionParser/Clang/ClangASTMetadata.h
The file was addedlldb/test/API/functionalities/limit-debug-info/two.cpp
The file was addedlldb/test/API/functionalities/limit-debug-info/TestLimitDebugInfo.py
The file was addedlldb/test/API/functionalities/limit-debug-info/one.cpp
The file was addedlldb/test/API/functionalities/limit-debug-info/main.cpp
Commit 7d9518c8000bcd742b364a390bc79560f736dc96 by ntv
[mlir][Linalg] Add an option to use Alloca instead of malloc/free pairs.

Summary: A relevant test is also added.

Subscribers: mehdi_amini, rriddle, jpienaar, shauheen, antiagainst, arpith-jacob, mgester, lucyrfox, aartbik, liufengdb, stephenneuendorffer, Joonsoo, grosul1, Kayjukh, jurahul, msifontes

Tags: #mlir

Differential Revision: https://reviews.llvm.org/D82959
The file was modifiedmlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Promotion.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/Passes.h
The file was modifiedmlir/include/mlir/Dialect/Linalg/Passes.td
The file was modifiedmlir/test/Dialect/Linalg/promote.mlir
Commit f3b5bf3eb7029238cead637be2e285b443b2e141 by Raphael Isemann
[lldb] Fix NSDate test after Scalar change

The formatter was requesting an unsigned integer from the ValueObject,
but CFAbsoluteTime is a signed double, so in the NSDate test the formatter
actually just printed the 'error value' date which is the Cocoa epoch. This
started failing after the recent Scalar changes.

This patch just changes the logic to use a signed value which fits to the data
we try to read and avoids this issue.
The file was modifiedlldb/source/Plugins/Language/ObjC/CF.cpp
Commit 97a7a9abb25d86fd831b403a1d13de6d62e7a8b5 by david.sherwood
[CodeGen] Fix up warnings in visitEXTRACT_SUBVECTOR

It's perfectly valid to do certain DAG combines where we extract
subvectors from a concat vector when we have scalable vector types.
However, we can do this in a way that avoids generating compiler
warnings by replacing calls to getVectorNumElements() with
getVectorMinNumElements(). Due to the way subvector extracts are
designed to work with scalable vector types this is ok.

This eliminates some warnings from existing tests in this file:

  llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll

Differential Revision: https://reviews.llvm.org/D82655
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit 2831a317b689c7f005a29f008a8e4c24485c0711 by erich.keane
Implement AVX ABI Warning/error

The x86-64 "avx" feature changes how >128 bit vector types are passed,
instead of being passed in separate 128 bit registers, they can be
passed in 256 bit registers.

"avx512f" does the same thing, except it switches from 256 bit registers
to 512 bit registers.

The result of both of these is an ABI incompatibility between functions
compiled with and without these features.

This patch implements a warning/error pair upon an attempt to call a
function that would run afoul of this. First, if a function is called
that would have its ABI changed, we issue a warning.

Second, if said call is made in a situation where the caller and callee
are known to have different calling conventions (such as the case of
'target'), we instead issue an error.

Differential Revision: https://reviews.llvm.org/D82562
The file was modifiedclang/lib/CodeGen/CGCall.cpp
The file was modifiedclang/lib/CodeGen/TargetInfo.h
The file was modifiedclang/test/CodeGen/target-builtin-noerror.c
The file was modifiedclang/test/CodeGen/target-builtin-error-3.c
The file was modifiedclang/lib/CodeGen/TargetInfo.cpp
The file was addedclang/test/CodeGen/target-avx-abi-diag.c
The file was modifiedclang/include/clang/Basic/DiagnosticFrontendKinds.td
Commit 63eddb679ad0bbb49cc9a3ff7f9f063c5ba16833 by rojamd
[cmake][Windows] Add libpath to CMAKE_MODULE_LINKER_FLAGS too

Followup to b8000c0ce845, the library path needs to go in
CMAKE_MODULE_LINKER_FLAGS too, for the sake of a few files
like LLVMHello.dll.

Reviewed By: hans

Differential Revision: https://reviews.llvm.org/D82888
The file was modifiedllvm/cmake/modules/HandleLLVMOptions.cmake
Commit 27bbc8ede127fb1ea8b6a853a5d2fe70f206408b by gchatelet
[Alignment][NFC] Migrate TargetTransformInfo::CreateVariableSizedObject to Align

This patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Differential Revision: https://reviews.llvm.org/D82939
The file was modifiedllvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
The file was modifiedllvm/include/llvm/CodeGen/MachineFrameInfo.h
Commit d3085c25012aceef3755abf9921a0368c64f40c6 by gchatelet
[Alignment][NFC] Transition and simplify calls to DL::getABITypeAlignment

This patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Differential Revision: https://reviews.llvm.org/D82956
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/CallLowering.cpp
The file was modifiedllvm/lib/Transforms/IPO/LowerTypeTests.cpp
The file was modifiedllvm/lib/Target/ARM/ARMFastISel.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.h
The file was modifiedllvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
The file was modifiedllvm/lib/IR/DataLayout.cpp
The file was modifiedllvm/lib/Target/ARM/ARMCallLowering.cpp
The file was modifiedllvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
The file was modifiedllvm/lib/CodeGen/LowerEmuTLS.cpp
The file was modifiedllvm/lib/Target/Target.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonISelLowering.cpp
The file was modifiedllvm/lib/Analysis/ValueTracking.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/lib/Transforms/IPO/GlobalOpt.cpp
Commit ef36f5143d83897cc6f59ff918769d29ad5a0612 by gchatelet
[Alignment] TargetLowering::hasPairedLoad must use Align for RequiredAlignment

As per documentation of `hasPairLoad`:
"`RequiredAlignment` gives the minimal alignment constraints that must be met to be able to select this paired load."
In this sense, `0` is strictly equivalent to `1`. We make this obvious by using `Align` instead of unsigned.
There is only one implementor of this interface.

Differential Revision: https://reviews.llvm.org/D82958
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/lib/Analysis/Lint.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetLowering.h
Commit 19c35526d98699db6917cf2a6f0dd3fe7da68926 by erich.keane
Limit x86 test to require target to fix buildbot (from 2831a317b)

The modification of the features apparently requires the backend to be
instantiated, so make sure this is required to fix the ARM build bots.
The file was modifiedclang/test/CodeGen/target-avx-abi-diag.c
Commit 05a20a9e9aba301a828bcbd72b0ed724755752d1 by luismarques
[RISCV] Temporarily move riscv-expand-pseudo pass to PreEmitPass2

The pass to split atomic and non-atomic RISC-V pseudo-instructions was itself
split into two passes in D79635 / commit rG2cb0644f90b7, with the splitting of
non-atomic instructions being moved to the PreSched2 phase. A comment was
added to D79635 detailing a case where this caused problems, so this commit
moves the non-atomic split pass back to the PreEmitPass2 phase. This allows
the bulk of the changes from D79635 to remain committed, while addressing the
the reported problem (the pass split is now almost NFC). Once the root problem
is fixed we can move the (non-atomic) instruction splitting pass back to
earlier in the pipeline.
The file was modifiedllvm/lib/Target/RISCV/RISCVTargetMachine.cpp
Commit c5263a4e84cc7fb7135a7e9e0cf000af264b72c5 by sam.mccall
[clangd] Fix race in FileIndex that sometimes temporarily lost updates.

Summary:
FileIndex was built out of threadsafe components, so update() didn't have data
races, but wasn't actually correct.

Reviewers: kadircet

Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, usaxena95, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D82891
The file was modifiedclang-tools-extra/clangd/index/FileIndex.cpp
The file was modifiedclang-tools-extra/clangd/index/FileIndex.h
The file was modifiedclang-tools-extra/clangd/index/Symbol.h
The file was modifiedclang-tools-extra/clangd/unittests/FileIndexTests.cpp
Commit 195205589208934b8c3b64dd84ccb355729b5b67 by marukawa
[VE] Support symbol with offset value

Summary: Support symbol with offset value as a VEMCExpr.

Reviewers: simoll, k-ishizaka

Reviewed By: simoll

Subscribers: hiraditya, llvm-commits

Tags: #llvm, #ve

Differential Revision: https://reviews.llvm.org/D82734
The file was modifiedllvm/lib/Target/VE/VEMCInstLower.cpp
The file was addedllvm/test/CodeGen/VE/load_off.ll
Commit 1276855f2b4485ec312b379c1b8eaf5510d9b157 by pavel
[lldb] Attempt to fix TestLimitDebugInfo on windows

The test fails due to link errors. I believe this change should fix
that.
The file was modifiedlldb/test/API/functionalities/limit-debug-info/Makefile
The file was modifiedlldb/test/API/functionalities/limit-debug-info/onetwo.h
Commit a61fa1a4b9d247e34ea5541422f7040a37baf6e7 by luismarques
Revert "[RISCV] Temporarily move riscv-expand-pseudo pass to PreEmitPass2"

This reverts commit 05a20a9e9aba301a828bcbd72b0ed724755752d1.
The file was modifiedllvm/lib/Target/RISCV/RISCVTargetMachine.cpp
Commit 9010cef2af0affdef774a721f6adb52a40041da5 by Raphael Isemann
[lldb] Replace StringConvert with llvm::to_integer when parsing integer values in CommandObjects

Summary:

This replaces the current use of LLDB's own `StringConvert` with LLVM's
`to_integer` which has a less error-prone API and doesn't use special 'error
values' to designate parsing problems.

Where needed I also added missing error handling code that prints a parsing
error instead of continuing with the error value returned from `StringConvert`
(which either gave a cryptic error message or just took the error value
performed an incorrect action with it. For example, `frame recognizer delete -1`
just deleted the frame recognizer at index 0).

Reviewers: #lldb, labath

Reviewed By: labath

Subscribers: labath, abidh, JDevlieghere

Differential Revision: https://reviews.llvm.org/D82297
The file was modifiedlldb/test/API/commands/frame/recognizer/TestFrameRecognizer.py
The file was addedlldb/test/API/commands/process/signal/main.cpp
The file was modifiedlldb/source/Commands/CommandObjectProcess.cpp
The file was addedlldb/test/API/commands/thread/select/Makefile
The file was modifiedlldb/source/Commands/CommandObjectPlatform.cpp
The file was addedlldb/test/API/commands/target/stop-hook/enable/TestTargetStopHookEnable.py
The file was addedlldb/test/API/commands/target/modules/search-paths/insert/TestTargetModulesSearchpathsInsert.py
The file was addedlldb/test/API/commands/target/select/TestTargetSelect.py
The file was modifiedlldb/source/Commands/CommandObjectFrame.cpp
The file was addedlldb/test/API/commands/target/modules/search-paths/insert/Makefile
The file was addedlldb/test/API/commands/thread/select/main.cpp
The file was addedlldb/test/API/commands/process/signal/TestProcessSignal.py
The file was addedlldb/test/API/commands/platform/file/close/TestPlatformFileClose.py
The file was addedlldb/test/API/commands/target/modules/search-paths/insert/main.cpp
The file was addedlldb/test/API/commands/target/stop-hook/delete/TestTargetStopHookDelete.py
The file was modifiedlldb/source/Commands/CommandObjectTarget.cpp
The file was modifiedlldb/source/Commands/CommandObjectThread.cpp
The file was addedlldb/test/API/commands/target/stop-hook/disable/TestTargetStopHookDisable.py
The file was addedlldb/test/API/commands/thread/select/TestThreadSelect.py
The file was addedlldb/test/API/commands/process/signal/Makefile
The file was addedlldb/test/API/commands/platform/file/read/TestPlatformFileRead.py
Commit b2aa546b0747418b0784b291b9104a4e3bf1e0c9 by luismarques
[RISCV] Temporarily move riscv-expand-pseudo pass to PreEmitPass2

The pass to split atomic and non-atomic RISC-V pseudo-instructions was itself
split into two passes in D79635 / commit rG2cb0644f90b7, with the splitting of
non-atomic instructions being moved to the PreSched2 phase. A comment was
added to D79635 detailing a case where this caused problems, so this commit
moves the non-atomic split pass back to the PreEmitPass2 phase. This allows
the bulk of the changes from D79635 to remain committed, while addressing the
the reported problem (the pass split is now almost NFC). Once the root problem
is fixed we can move the (non-atomic) instruction splitting pass back to
earlier in the pipeline.
The file was modifiedllvm/test/CodeGen/RISCV/codemodel-lowering.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVTargetMachine.cpp
Commit d36f2c6a6c4bb3c1cd213f3ed08a7a090fee54d2 by pzheng
[RISCV] Add mcountinhibit CSR

Summary:
The mcountinhibit CSR is defined in the ratified 1.11 version of the privileged
spec.

Reviewers: apazos, asb, lenary, luismarques

Reviewed By: asb

Subscribers: hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, sameer.abuasal, evandro, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D82913
The file was modifiedllvm/lib/Target/RISCV/RISCVSystemOperands.td
The file was modifiedllvm/test/MC/RISCV/machine-csr-names.s