FailedChanges

Changes from Git (git http://labmaster3.local/git/llvm-zorg.git)

Summary

  1. Adding myself as a recipient of Sphinx builder failure emails. (details)
  2. Removed extra square bracket. (details)
Commit 4f84ca41449691cd45ce49d5e34ac580940ff6ab by aballman
Adding myself as a recipient of Sphinx builder failure emails.
The file was modifiedbuildbot/osuosl/master/config/status.py
Commit 5fab453ffc9cb6f7f8922e96af204ced7591110f by gkistanova
Removed extra square bracket.
The file was modifiedbuildbot/osuosl/master/config/status.py

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [DSE] Support traversing MemoryPhis. (details)
  2. [Matrix] Generalize ColumnMatrixTy to MatrixTy (NFC). (details)
  3. [Syntax] Split syntax tests (details)
  4. [InstCombine] Don't replace musttail result based on known bits (details)
  5. [ARM] Extra MVE float loop tests. NFC (details)
  6. [InstCombine] Simplify calls with "returned" attribute (details)
  7. [NFC][RISCV] Test for 0.0 fp immediate (details)
  8. [RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w (details)
  9. [ARM] Change VDUP type to i32 for MVE (details)
  10. Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes" (details)
  11. [clang] Add support for consteval constructors (details)
  12. [lldb] Enable now passing part of TestDataFormatterStdString.py (details)
  13. [llvm-readobj][llvm-readelf][test] - Add a test to check how we dump relocation addends. (details)
  14. Improve step over performance (details)
  15. [Syntax] Test both the default and windows target platforms in unittests (details)
  16. [llvm-readobj] Allow syms from all sections to match stack size entries (details)
  17. [Tests] Regenerate some test checks; NFC (details)
  18. [ValueTracking] Add computeKnownBits DemandedElts support to shift instructions (PR36319) (details)
  19. Revert "[Syntax] Test both the default and windows target platforms in unittests" (details)
  20. [InstCombine] Move test to instcombine; NFC (details)
  21. [OPENMP50]Initial support for scan directive. (details)
  22. [ValueTracking] Add some initial isKnownNonZero DemandedElts support (PR36319) (details)
  23. Fix `-Wunused-variable` warning. NFC. (details)
  24. [DSE,MSSA] Precommit additional tests for D73763. (details)
  25. [ARM,CDE] Implement GPR CDE intrinsics (details)
  26. [ARM,CDE] Implement CDE S and D-register intrinsics (details)
  27. [ARM,CDE] Implement CDE unpredicated Q-register intrinsics (details)
  28. [ARM,CDE] Implement CDE vreinterpret intrinsics (details)
  29. [AMDGPU] Enable divergence driven ISel for ADD/SUB i64 (details)
  30. [scudo][standalone] Allow fallback to secondary if primary is full (details)
  31. AMDGPU: Add more tests for fshr (details)
  32. AMDGPU: Move towards deprecating alignbit intrinsic (details)
  33. [DAGCombiner] Fix non-determinism problem related to argument evaluation order in visitFDIV (details)
  34. [PowerPC][AIX][NFC] Add zero-sized by val params to cc test. (details)
  35. [analyzer] StdLibraryFunctionsChecker: Add argument constraints (details)
  36. [Syntax] Test both the default and windows target platforms in unittests (details)
  37. [ARM,MVE] Add ACLE intrinsics for the vminv/vmaxv family. (details)
  38. [ARM,MVE] Add ACLE intrinsics for the vaddv/vaddlv family. (details)
  39. [InstCombine][X86] simplifyX86immShift - convert variable in-range vector shift by scalar amounts to generic shifts (PR40391) (details)
  40. [[Clang CallGraph]] CallGraph should still record calls to decls. (details)
  41. Use FinishThunk to finish musttail thunks (details)
  42. [X86] Prevent (bitcast (broadcast_load)) combine from producing vXf16 broadcast instructions. (details)
  43. [PowerPC][AIX][NFC] Extend the test coverage of ByVal args. (details)
  44. [DAGCombiner] Do not fold truncate(build_vector(..)) if it creates an illegal type (details)
  45. [analyzer] StdLibraryFunctionsChecker: Add NotNull Arg Constraint (details)
  46. Attempt to fix failing build-bot with [-Werror,-Wcovered-switch-default] (details)
  47. [mlir/quant] fix a small typo in the quant utility (details)
  48. [lldb-vscode] Don't use SBLaunchInfo in request_attach (details)
  49. [InstCombine] Handle known shl nsw sign bit in SimplifyDemanded (details)
  50. Cleanup the plumbing for DILineInfoSpecifier. [NFC - Try 2] (details)
  51. Add missing module map entry (details)
  52. [mlir][AVX512] Start a primitive AVX512 dialect (details)
  53. PR45181: Fix another invalid DIExpression combination (details)
  54. [llc] Initialize TargetLoweringObjectFile for MIR input (details)
  55. [X86] Reland D71360 Clean up UseInitArray initialization for X86ELFTargetObjectFile (details)
  56. [OPENMP50]Initial support for inclusive clause. (details)
  57. [libc++] Add a new FILE_DEPENDENCIES parser (details)
  58. [libc] NFC - Move the round redirector from its own nested directory. (details)
  59. [ADT] CoalescingBitVector: Avoid initial heap allocation, NFC (details)
  60. [ADT] CoalescingBitVector: Add advanceToLowerBound iterator operation (details)
  61. [LiveDebugValues] Speed up collectIDsForRegs, NFC (details)
  62. unittest: Work around build failure on MSVC builders (details)
  63. [OPENMP50]Do not allow several scan directives in the same parent (details)
  64. [InstCombine] Remove known bits constant folding (details)
  65. [mlir][Linalg] NFC: Clean up for 0-D abstraction. (details)
  66. [mlir][LLVMIR] Fix fusion for rank-0 tensors (details)
  67. [llvm-ar] Use target triple to deduce archive kind for bitcode inputs (details)
Commit 3a8372ed02abe9ce6c82d12dbec3f5eed2d3a5f0 by flo
[DSE] Support traversing MemoryPhis.

For MemoryPhis, we have to avoid that the MemoryPhi may be executed
before before the access we are currently looking at.

To do this we do a post-order numbering of the basic blocks in the
function and bail out once we reach a MemoryPhi with a larger (or equal)
post-order block number than the current MemoryAccess.
This changes the order in which we visit stores for elimination.

This patch also adds support for exploring multiple paths. We keep a worklist (ToCheck) of memory accesses that might be eliminated by our starting MemoryDef or MemoryPhis for further exploration.  For MemoryPhis, we add the incoming values to the worklist, for MemoryDefs we add the defining access.

Reviewers: dmgreen, rnk, efriedma, bryant, asbirlea

Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D72148
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-memoryphis.ll
The file was modifiedllvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-loops.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-exceptions.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-simple.ll
Commit be86bc76f0c21c024ed15704f266eb3595088b02 by flo
[Matrix] Generalize ColumnMatrixTy to MatrixTy (NFC).

This patch sets the stage for supporting both row and column major
layouts for matrixes. It renames ColumnMatrixTy to MatrixTy, adds
booleans indicating the underlying layout to both MatrixTy and ShapeInfo
and generalizes the methods of MatrixTy to support both row and column
major layouts.

Reviewers: Gerolf, anemet, andrew.w.kaylor, LuoYuanke

Reviewed By: anemet

Differential Revision: https://reviews.llvm.org/D76324
The file was modifiedllvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
Commit e9630630ffa2a69bf3eabe154a3846deab694fa0 by gribozavr
[Syntax] Split syntax tests

Summary:
This patch split Basic test into multple individual tests to allow simpler
filtering and clearer signal into what's broken when it's broken.

Reviewers: gribozavr2

Reviewed By: gribozavr2

Subscribers: cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D76366
The file was modifiedclang/unittests/Tooling/Syntax/TreeTest.cpp
Commit 5c10967157d11a489de544b51349d12cfb3fe7de by nikita.ppv
[InstCombine] Don't replace musttail result based on known bits

This is the same change as D75824, but for two cases where
InstCombine performs the same optimization: Replacing an instruction
whose bits are fully known with a constant. This is not (generally)
legal for musttail calls.

Differential Revision: https://reviews.llvm.org/D76457
The file was addedllvm/test/Transforms/InstCombine/call-returned.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstructionCombining.cpp
Commit 9cf920e64d18e9c64706c8c8baf71a4919dcbb42 by david.green
[ARM] Extra MVE float loop tests. NFC
The file was addedllvm/test/CodeGen/Thumb2/mve-float16regloops.ll
The file was addedllvm/test/CodeGen/Thumb2/mve-float32regloops.ll
Commit 03727687766a72504712861bf038f0be962527d0 by nikita.ppv
[InstCombine] Simplify calls with "returned" attribute

If a call argument has the "returned" attribute, we can simplify
the call to the value of that argument. This was already partially
handled by InstSimplify/InstCombine for the case where the argument
is an integer constant, and the result is thus known via known bits.
The non-constant (or non-int) argument cases weren't handled though.

This previously landed as an InstSimplify transform, but was reverted
due to assertion failures when compiling the Linux kernel. The reason
is that simplifying a call to another call breaks assumptions in
call graph updating during inlining. As the code is not easy to fix,
and there is no particularly strong motivation for having this in
InstSimplify, the transform is only performed in InstCombine instead.

Differential Revision: https://reviews.llvm.org/D75815
The file was modifiedllvm/test/Transforms/InstCombine/expensive-combines.ll
The file was modifiedllvm/test/Transforms/InstCombine/strncpy_chk-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/fortify-folding.ll
The file was modifiedllvm/test/Transforms/InstCombine/strcpy_chk-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/unused-nonnull.ll
The file was modifiedllvm/test/Transforms/InstCombine/align-attr.ll
The file was modifiedllvm/test/Transforms/InstCombine/call-returned.ll
The file was modifiedllvm/test/Transforms/InstSimplify/call.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
Commit ebb04e9ca936409a756bb6817f0957591fe493c1 by roger.ferrer
[NFC][RISCV] Test for 0.0 fp immediate

To show a later change that impacts 0.0 fp constant generation.

Differential Revision: https://reviews.llvm.org/D75728
The file was addedllvm/test/CodeGen/RISCV/fp-imm.ll
Commit 3c24aee7ee8b00ff3825684f3e5436d8f71e4046 by roger.ferrer
[RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w

Floating point positive zero can be selected using fmv.w.x / fmv.d.x /
fcvt.d.w and the zero source register.

Differential Revision: https://reviews.llvm.org/D75729
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/test/CodeGen/RISCV/float-br-fcmp.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoF.td
The file was modifiedllvm/test/CodeGen/RISCV/double-arith.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.h
The file was modifiedllvm/test/CodeGen/RISCV/float-arith.ll
The file was modifiedllvm/test/CodeGen/RISCV/fp-imm.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoD.td
Commit b3499f572d37ce238c3f78668ef7e885d357745d by david.green
[ARM] Change VDUP type to i32 for MVE

The MVE VDUP instruction take a GPR and splats into every lane of a
vector register. Unlike NEON we do not have a VDUPLANE equivalent
instruction, doing the same splat from a fp register. Previously a VDUP
to a v4f32/v8f16 would be represented as a (v4f32 VDUP f32), which
would mean the instruction pattern needs to add a COPY_TO_REGCLASS to
the GPR.

Instead this now converts that earlier during an ISel DAG combine,
converting (VDUP x) to (VDUP (bitcast x)). This can allow instruction
selection to tell that the input needs to be an i32, which in one of the
testcases allows it to use ldr (or specifically ldm) over (vldr;vmov).

Whilst being simple enough for floats, as the types sizes are the same,
these is no BITCAST equivalent for getting a half into a i32. This uses
a VMOVrh ARMISD node, which doesn't know the same tricks yet.

Differential Revision: https://reviews.llvm.org/D76292
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vcmpfr.ll
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/mve-intrinsics/vaddq.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-intrinsics/dup.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-float16regloops.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vdup.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-intrinsics/ternary.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vldst4.ll
The file was modifiedllvm/lib/Target/ARM/ARMInstrMVE.td
The file was modifiedllvm/test/CodeGen/Thumb2/mve-intrinsics/vmulq.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-intrinsics/vsubq.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-pred-threshold.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-float32regloops.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-fmas.ll
Commit baa6f6a7828a46c37b96227282938717220f8b34 by akuegel
Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes"

This reverts commit e9f22fd4293a65bcdcf1b18b91c72f63e5e9e45b.

When building with -DLLVM_USE_SANITIZER="Thread", check-llvm has 70
failing tests with this revision, and 29 without this revision.
The file was modifiedllvm/lib/CodeGen/GlobalISel/RegisterBank.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVRegisterBankInfo.h
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
The file was modifiedllvm/lib/Target/RISCV/RISCVSubtarget.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/RegisterBank.h
The file was modifiedllvm/utils/TableGen/RegisterBankEmitter.cpp
Commit 180581cfcf5115388caa3b8ee20eac1fd35f2d11 by tyker
[clang] Add support for consteval constructors

Summary:
Changes:
- handle immediate invocations for constructors.
- add tests

after this patch i believe the implementation of consteval is nearly standard compliant, but IR-gen still needs to be taught not to emit consteval declarations.

Reviewers: rsmith

Reviewed By: rsmith

Subscribers: wchilders

Differential Revision: https://reviews.llvm.org/D74007
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/lib/Sema/SemaExpr.cpp
The file was modifiedclang/lib/Sema/SemaInit.cpp
The file was modifiedclang/lib/Sema/SemaDeclCXX.cpp
The file was modifiedclang/lib/Sema/TreeTransform.h
The file was modifiedclang/test/SemaCXX/cxx2a-consteval.cpp
Commit 467c4902a10999f792bea653147641ac8b89cca5 by Raphael Isemann
[lldb] Enable now passing part of TestDataFormatterStdString.py

This was fixed by 7b2442584e40f97693c38c0d79b83f770d557039 .
The file was modifiedlldb/test/API/functionalities/data-formatter/data-formatter-stl/libstdcpp/string/TestDataFormatterStdString.py
Commit 63778bc653a2193717b39874e9f69dcfe3f8771c by grimar
[llvm-readobj][llvm-readelf][test] - Add a test to check how we dump relocation addends.

Seems we do not test how we print relocation addends well.
And the behavior of dumpers does not seem to be ideal here
(and llvm-readelf does not match GNU as the test case shows).

This patch adds a test case to document the current behavior.

Differential revision: https://reviews.llvm.org/D75671
The file was addedllvm/test/tools/llvm-readobj/ELF/reloc-addends.test
Commit 089cfe113da1395427dd31f21067d5b618b89d7c by pavel
Improve step over performance

Summary:
This patch improves step over performance for the case when we are
stepping over a call with a next-branch-breakpoint (see
https://reviews.llvm.org/D58678), and we encounter a stop during the
call. Currently, this causes the thread plan to step-out //each frame//
until it reaches the step-over range. This is a regression introduced by
https://reviews.llvm.org/D58678 (which did improve other things!). Prior
to that change, the step-over plan would always step-out just once.

With this patch, if we find ourselves stopped in a deeper stack frame
and we already have a next branch breakpoint, we simply return from the
step-over plan's ShouldStop handler without pushing the step out plan.

In my experiments this improved the time of stepping over a call that
loads 12 dlls from 14s to 5s. This was in remote debugging scenario with
10ms RTT, the call in question was Vulkan initialization
(vkCreateInstance), which loads various driver dlls. Loading those dlls
must stop on the rendezvous breakpoint, causing the perf problem
described above.

Reviewers: clayborg, labath, jingham

Reviewed By: jingham

Subscribers: lldb-commits

Tags: #lldb

Differential Revision: https://reviews.llvm.org/D76216
The file was modifiedlldb/source/Target/ThreadPlanStepOverRange.cpp
Commit fd7300f717c18c861e77685efe6f16f12fb63ae7 by gribozavr
[Syntax] Test both the default and windows target platforms in unittests

Summary:
This increases the coverage for things that differ between Linux and Windows, such as `-fdelayed-template-parsing`. This would have prevented the rollback of https://reviews.llvm.org/D76346.

While at it, update -std=c++11 to c++17 for the test.

Reviewers: gribozavr2

Reviewed By: gribozavr2

Subscribers: cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D76433
The file was modifiedclang/unittests/Tooling/Syntax/TreeTest.cpp
Commit 86b093d1a18c1d4ccd3578e70e738a0f249ab19e by james.henderson
[llvm-readobj] Allow syms from all sections to match stack size entries

Prior to this change, for non-relocatable objects llvm-readobj would
assume that all symbols that corresponded to a stack size section's
entries were in the section specified by the section's sh_link field.
In the presence of an output section description combining
SHF_LINK_ORDER sections linking different output sections, this cannot
be respected, since linker script section patterns are "by name" by
nature. Consequently, the sh_link value would not be correct for all
section entries.

This patch changes llvm-readobj to ignore the section of symbols in a
non-relocatable object.

Fixes https://bugs.llvm.org/show_bug.cgi?id=45228.

Reviewed by: grimar, MaskRay

Differential Revision: https://reviews.llvm.org/D76425
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp
The file was modifiedllvm/test/tools/llvm-readobj/ELF/stack-sizes.test
Commit a09ff56b5b5edc3aef0e2f572f9ffd1c4deb8e08 by nikita.ppv
[Tests] Regenerate some test checks; NFC
The file was modifiedllvm/test/Transforms/GVN/PRE/volatile.ll
The file was modifiedllvm/test/Transforms/InstSimplify/assume.ll
The file was modifiedllvm/test/Analysis/ValueTracking/knownnonzero-shift.ll
Commit c1efdbcbe0dfef846a9774eea280a74b9ea19437 by llvm-dev
[ValueTracking] Add computeKnownBits DemandedElts support to shift instructions (PR36319)
The file was modifiedllvm/test/Transforms/InstSimplify/shift-knownbits.ll
The file was modifiedllvm/lib/Analysis/ValueTracking.cpp
Commit 9967352a0346021d389afb6e3283d0c58911a560 by gribozavr
Revert "[Syntax] Test both the default and windows target platforms in unittests"

This reverts commit fd7300f717c18c861e77685efe6f16f12fb63ae7. The fix
in this patch didn't help and the Windows buildbot broke:
http://45.33.8.238/win/10881/step_7.txt
The file was modifiedclang/unittests/Tooling/Syntax/TreeTest.cpp
Commit ce6c95aacae0cf5f8de8780de7f22de5f31a07dd by nikita.ppv
[InstCombine] Move test to instcombine; NFC

This test uses -instcombine, so move it into the appropriate
directory. Also fork it for expensive checks enabled/disabled.
The file was removedllvm/test/Analysis/ValueTracking/known-signbit-shift.ll
The file was addedllvm/test/Transforms/InstCombine/known-signbit-shift.ll
Commit fcba7c3534f98851531095f8457eb3142e237f0b by a.bataev
[OPENMP50]Initial support for scan directive.

Addedi basic parsing/sema/serialization support for scan directive.
The file was modifiedclang/include/clang/Serialization/ASTBitCodes.h
The file was modifiedclang/test/OpenMP/nesting_of_regions.cpp
The file was modifiedclang/lib/Serialization/ASTWriterStmt.cpp
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/lib/Basic/OpenMPKinds.cpp
The file was modifiedclang/tools/libclang/CXCursor.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/lib/AST/StmtProfile.cpp
The file was modifiedclang/lib/StaticAnalyzer/Core/ExprEngine.cpp
The file was modifiedclang/include/clang/AST/StmtOpenMP.h
The file was addedclang/test/OpenMP/scan_ast_print.cpp
The file was modifiedclang/include/clang-c/Index.h
The file was modifiedclang/lib/AST/StmtOpenMP.cpp
The file was modifiedclang/lib/AST/StmtPrinter.cpp
The file was modifiedclang/lib/Sema/TreeTransform.h
The file was modifiedclang/lib/Sema/SemaExceptionSpec.cpp
The file was modifiedclang/lib/CodeGen/CGOpenMPRuntime.cpp
The file was modifiedclang/lib/CodeGen/CGOpenMPRuntimeNVPTX.cpp
The file was modifiedclang/include/clang/Basic/StmtNodes.td
The file was modifiedclang/lib/Sema/SemaOpenMP.cpp
The file was modifiedclang/include/clang/AST/RecursiveASTVisitor.h
The file was modifiedclang/lib/CodeGen/CGStmt.cpp
The file was addedclang/test/OpenMP/scan_messages.cpp
The file was modifiedclang/lib/Parse/ParseOpenMP.cpp
The file was modifiedclang/lib/Serialization/ASTReaderStmt.cpp
The file was modifiedllvm/include/llvm/Frontend/OpenMP/OMPKinds.def
The file was modifiedclang/tools/libclang/CIndex.cpp
Commit 7f764fa18f640bf4748ef53c39d55e52132bf95d by llvm-dev
[ValueTracking] Add some initial isKnownNonZero DemandedElts support (PR36319)
The file was modifiedllvm/lib/Analysis/ValueTracking.cpp
The file was modifiedllvm/test/Transforms/InstSimplify/compare.ll
Commit a4edea29be2a77a8c8c237d75563a09a61791442 by michael.hliao
Fix `-Wunused-variable` warning. NFC.
The file was modifiedclang/lib/Sema/SemaExpr.cpp
Commit ece6cf0fa56687d4f9fd918a7dc367cd1277d0c4 by flo
[DSE,MSSA] Precommit additional tests for D73763.
The file was addedllvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-overlap.ll
The file was addedllvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-multipath.ll
The file was addedllvm/test/Transforms/DeadStoreElimination/MSSA/memset-unknown-sizes.ll
Commit 7a85e3585ec59b1bfe3b08072ff042af80d07f22 by mikhail.maltsev
[ARM,CDE] Implement GPR CDE intrinsics

Summary:
This change implements ACLE CDE intrinsics that translate to
instructions working with general-purpose registers.

The specification is available at
https://static.docs.arm.com/101028/0010/ACLE_2019Q4_release-0010.pdf

Each ACLE intrinsic gets a corresponding LLVM IR intrinsic (because
they have distinct function prototypes). Dual-register operands are
represented as pairs of i32 values. Because of this the instruction
selection for these intrinsics cannot be represented as TableGen
patterns and requires custom C++ code.

Reviewers: simon_tatham, MarkMurrayARM, dmgreen, ostannard

Reviewed By: MarkMurrayARM

Subscribers: kristof.beyls, hiraditya, danielkiss, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D76296
The file was modifiedclang/test/CodeGen/arm-cde-gpr.c
The file was modifiedllvm/lib/Target/ARM/ARMInstrCDE.td
The file was modifiedllvm/include/llvm/IR/IntrinsicsARM.td
The file was modifiedclang/test/Sema/arm-cde-immediates.c
The file was modifiedllvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
The file was addedllvm/test/CodeGen/Thumb2/cde-gpr.ll
The file was modifiedclang/include/clang/Basic/arm_cde.td
Commit d22e66171251cd3dd07507912189aa814a419678 by mikhail.maltsev
[ARM,CDE] Implement CDE S and D-register intrinsics

Summary:
This patch implements the following ACLE intrinsics:

  uint32_t __arm_vcx1_u32(int coproc, uint32_t imm);
  uint32_t __arm_vcx1a_u32(int coproc, uint32_t acc, uint32_t imm);
  uint32_t __arm_vcx2_u32(int coproc, uint32_t n, uint32_t imm);
  uint32_t __arm_vcx2a_u32(int coproc, uint32_t acc, uint32_t n, uint32_t imm);
  uint32_t __arm_vcx3_u32(int coproc, uint32_t n, uint32_t m, uint32_t imm);
  uint32_t __arm_vcx3a_u32(int coproc, uint32_t acc, uint32_t n, uint32_t m, uint32_t imm);

  uint64_t __arm_vcx1d_u64(int coproc, uint32_t imm);
  uint64_t __arm_vcx1da_u64(int coproc, uint64_t acc, uint32_t imm);
  uint64_t __arm_vcx2d_u64(int coproc, uint64_t m, uint32_t imm);
  uint64_t __arm_vcx2da_u64(int coproc, uint64_t acc, uint64_t m, uint32_t imm);
  uint64_t __arm_vcx3d_u64(int coproc, uint64_t n, uint64_t m, uint32_t imm);
  uint64_t __arm_vcx3da_u64(int coproc, uint64_t acc, uint64_t n, uint64_t m, uint32_t imm);

Since the semantics of CDE instructions is opaque to the compiler, the
ACLE intrinsics require dedicated LLVM IR intrinsics. The 64-bit and
32-bit variants share the same IR intrinsic.

Reviewers: simon_tatham, MarkMurrayARM, ostannard, dmgreen

Reviewed By: MarkMurrayARM

Subscribers: kristof.beyls, hiraditya, danielkiss, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D76298
The file was modifiedllvm/lib/Target/ARM/ARMInstrCDE.td
The file was modifiedclang/test/Sema/arm-cde-immediates.c
The file was modifiedclang/utils/TableGen/MveEmitter.cpp
The file was modifiedllvm/include/llvm/IR/IntrinsicsARM.td
The file was addedclang/test/CodeGen/arm-cde-vfp.c
The file was addedllvm/test/CodeGen/Thumb2/cde-vfp.ll
The file was modifiedclang/include/clang/Basic/arm_cde.td
Commit 969034b86037d3c1daf725aef13ba16424f92fe1 by mikhail.maltsev
[ARM,CDE] Implement CDE unpredicated Q-register intrinsics

Summary:
This patch implements the following intrinsics:

  uint8x16_t __arm_vcx1q_u8 (int coproc, uint32_t imm);
  T __arm_vcx1qa(int coproc, T acc, uint32_t imm);
  T __arm_vcx2q(int coproc, T n, uint32_t imm);
  uint8x16_t __arm_vcx2q_u8(int coproc, T n, uint32_t imm);
  T __arm_vcx2qa(int coproc, T acc, U n, uint32_t imm);
  T __arm_vcx3q(int coproc, T n, U m, uint32_t imm);
  uint8x16_t __arm_vcx3q_u8(int coproc, T n, U m, uint32_t imm);
  T __arm_vcx3qa(int coproc, T acc, U n, V m, uint32_t imm);

Most of them are polymorphic. Furthermore, some intrinsics are
polymorphic by 2 or 3 parameter types, such polymorphism is not
supported by the existing MVE/CDE tablegen backends, also we don't
really want to have a combinatorial explosion caused by 1000 different
combinations of 3 vector types. Because of this some intrinsics are
implemented as macros involving a cast of the polymorphic arguments to
uint8x16_t.

The IR intrinsics are even more restricted in terms of types: all MVE
vectors are cast to v16i8.

Reviewers: simon_tatham, MarkMurrayARM, dmgreen, ostannard

Reviewed By: MarkMurrayARM

Subscribers: kristof.beyls, hiraditya, danielkiss, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D76299
The file was modifiedclang/test/Sema/arm-cde-immediates.c
The file was modifiedllvm/lib/Target/ARM/ARMInstrCDE.td
The file was modifiedclang/include/clang/Basic/arm_cde.td
The file was addedclang/test/CodeGen/arm-cde-vec.c
The file was modifiedllvm/include/llvm/IR/IntrinsicsARM.td
The file was addedllvm/test/CodeGen/Thumb2/cde-vec.ll
The file was modifiedclang/utils/TableGen/MveEmitter.cpp
Commit 6ae3eff8baaca95752b1ec9732c605b3d4e8d630 by mikhail.maltsev
[ARM,CDE] Implement CDE vreinterpret intrinsics

Summary:
This patch implements the following CDE intrinsics:

  int8x16_t __arm_vreinterpretq_s8_u8 (uint8x16_t in);
  uint16x8_t __arm_vreinterpretq_u16_u8 (uint8x16_t in);
  int16x8_t __arm_vreinterpretq_s16_u8 (uint8x16_t in);
  uint32x4_t __arm_vreinterpretq_u32_u8 (uint8x16_t in);
  int32x4_t __arm_vreinterpretq_s32_u8 (uint8x16_t in);
  uint64x2_t __arm_vreinterpretq_u64_u8 (uint8x16_t in);
  int64x2_t __arm_vreinterpretq_s64_u8 (uint8x16_t in);
  float16x8_t __arm_vreinterpretq_f16_u8 (uint8x16_t in);
  float32x4_t __arm_vreinterpretq_f32_u8 (uint8x16_t in);

These intrinsics are header-only because they reuse the existing
MVE vreinterpret clang built-ins.

This set is slightly different from the published specification
(see https://static.docs.arm.com/101028/0010/ACLE_2019Q4_release-0010.pdf):
it includes

  int8x16_t __arm_vreinterpretq_s8_u8 (uint8x16_t in);

which was unintentionally ommitted from the spec, and
does not include

  float64x2_t __arm_vreinterpretq_f64_u8 (uint8x16_t in);

The float64x2_t type requires additional implementation
effort, and we are not including it yet.

Reviewers: simon_tatham, MarkMurrayARM, dmgreen, ostannard

Reviewed By: MarkMurrayARM

Subscribers: kristof.beyls, danielkiss, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D76300
The file was modifiedclang/include/clang/Basic/arm_cde.td
The file was addedclang/test/CodeGen/arm-cde-reinterpret.c
Commit 6e34e71869ab57ee33cb361426789ee85e1cde87 by alex-t
 [AMDGPU] Enable divergence driven ISel for ADD/SUB i64

Summary:
Currently we custom select add/sub with carry out to scalar form relying on later replacing them to vector form if necessary.
This change enables custom selection code to take the divergence of adde/addc SDNodes into account and select the appropriate form in one step.

Reviewers: arsenm, vpykhtin, rampitec

Reviewed By: arsenm, vpykhtin

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa

Differential Revision: https://reviews.llvm.org/D76371
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/urem64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/udiv64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/srem64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/sdiv64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/bypass-div.ll
Commit f8352502a355fb080300e2cc9de5629614a6c00f by kostyak
[scudo][standalone] Allow fallback to secondary if primary is full

Summary:
We introduced a way to fallback to the immediately larger size class for
the Primary in the event a region was full, but in the event of the largest
size class, we would just fail.

This change allows to fallback to the Secondary when the last region of
the Primary is full. We also expand the trick to all platforms as opposed
to being Android only, and update the test to cover the new case.

Reviewers: hctim, cferris, eugenis, morehouse, pcc

Subscribers: #sanitizers, llvm-commits

Tags: #sanitizers

Differential Revision: https://reviews.llvm.org/D76430
The file was modifiedcompiler-rt/lib/scudo/standalone/tests/combined_test.cpp
The file was modifiedcompiler-rt/lib/scudo/standalone/combined.h
Commit 53d6b156bbb9763b6f64f1a27b10f6a2ce1dfa88 by arsenm2
AMDGPU: Add more tests for fshr
The file was modifiedllvm/test/CodeGen/AMDGPU/fshr.ll
Commit a950e3beefd55c354b658f2ef79a9406289bcc08 by arsenm2
AMDGPU: Move towards deprecating alignbit intrinsic

This is equivalent to llvm.fshr, so legalize the intrinsic to the
generic node.
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/VOP3Instructions.td
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
Commit d168b7778035af6cc795b2367ca7f379ce1a629e by bjorn.a.pettersson
[DAGCombiner] Fix non-determinism problem related to argument evaluation order in visitFDIV

Summary:
For some reason the order in which we call getNegatedExpression
for the involved operands, after a call to isCheaperToUseNegatedFPOps,
seem to matter. This patch includes a new test case in
test/CodeGen/X86/fdiv.ll that crashes if we reverse the order of
those calls. Before this patch that could happen depending on
which compiler that were used when buildind llvm. With my GCC
version (7.4.0) I got the crash, because it seems like it is
using a different order for the argument evaluation compared
to clang.

All other users of isCheaperToUseNegatedFPOps already used this
pattern with unfolded/ordered calls to getNegatedExpression, so
this patch is aligning visitFDIV with the other use cases.

This patch simply deals with the non-determinism for FDIV. While
the underlying problem with getNegatedExpression is discussed
further in D76439.

Reviewers: spatel, RKSimon

Reviewed By: spatel

Subscribers: hiraditya, mgrang, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D76319
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/test/CodeGen/X86/fdiv.ll
Commit fc902cb6e2b29e50e6cd0e36fbb955d7b6cde43e by sd.fertile
[PowerPC][AIX][NFC] Add zero-sized by val params to cc test.

The zero sized structs force creation of a stack object of size 1, align
8 in the locals area, but otherwise have no effect on the calling convention
code. i.e. They consume no registers or stack space in the paramater save area.

The 32-bit codegen has 8 bytes of padding to fit the new stack object so
stack size stays the same. 64-bit codegen has no padding in the stack
frames allocated so 8 bytes is added, and becuase of 16-byte aligned
stack, the stack size increases from 112 bytes to 128.
The file was modifiedllvm/test/CodeGen/PowerPC/aix-cc-byval.ll
Commit 94061df6e5f24c2f25ad7c55af13dd17cccc5856 by gabor.marton
[analyzer] StdLibraryFunctionsChecker: Add argument constraints

Differential Revision:
https://reviews.llvm.org/D73898
The file was modifiedclang/include/clang/StaticAnalyzer/Checkers/Checkers.td
The file was modifiedclang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp
The file was addedclang/test/Analysis/std-c-library-functions-arg-constraints.c
The file was modifiedclang/test/Analysis/analyzer-enabled-checkers.c
The file was modifiedclang/test/Analysis/std-c-library-functions.c
Commit eddede9d5184a431c7f859ef1869f1a4de8d08d4 by gribozavr
[Syntax] Test both the default and windows target platforms in unittests

Summary:
This increases the coverage for things that differ between Linux and Windows, such as -fdelayed-template-parsing. This would have prevented the rollback of https://reviews.llvm.org/D76346.

While at it, update -std=c++11 to c++17 for the test.

Reviewers: gribozavr2

Reviewed By: gribozavr2

Subscribers: cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D76497
The file was modifiedclang/unittests/Tooling/Syntax/TreeTest.cpp
Commit 45a9945b9ea95bd065d3c4e08d9089a309b24a23 by simon.tatham
[ARM,MVE] Add ACLE intrinsics for the vminv/vmaxv family.

Summary:
I've implemented these as target-specific IR intrinsics, because
they're not //quite// enough like @llvm.experimental.vector.reduce.min
(which doesn't take the extra scalar parameter). Also this keeps the
predicated and unpredicated versions looking similar, and the
floating-point minnm/maxnm versions fold into the same schema.

We had a couple of min/max reductions already implemented, from the
initial pathfinding exercise in D67158. Those were done by having
separate IR intrinsic names for the signed and unsigned integer
versions; as part of this commit, I've changed them to use a flag
parameter indicating signedness, which is how we ended up deciding
that the rest of the MVE intrinsics family ought to work. So now
hopefully the ewhole lot is consistent.

In the new llc test, the output code from the `v8f16` test functions
looks quite unpleasant, but most of it is PCS lowering (you can't pass
a `half` directly in or out of a function). In other circumstances,
where you do something else with your `half` in the same function, it
doesn't look nearly as nasty.

Reviewers: dmgreen, MarkMurrayARM, miyuki, ostannard

Reviewed By: MarkMurrayARM

Subscribers: kristof.beyls, hiraditya, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D76490
The file was modifiedclang/include/clang/Basic/arm_mve.td
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vminvq.c
The file was modifiedllvm/test/CodeGen/Thumb2/mve-intrinsics/vminvq.ll
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/include/llvm/IR/IntrinsicsARM.td
The file was modifiedllvm/lib/Target/ARM/ARMInstrMVE.td
Commit 1adfa4c99169733dedb67b4f7ab03d2fbb196162 by simon.tatham
[ARM,MVE] Add ACLE intrinsics for the vaddv/vaddlv family.

Summary:
I've implemented them as target-specific IR intrinsics rather than
using `@llvm.experimental.vector.reduce.add`, on the grounds that the
'experimental' intrinsic doesn't currently have much code generation
benefit, and my replacements encapsulate the sign- or zero-extension
so that you don't expose the illegal MVE vector type (`<4 x i64>`) in
IR.

The machine instructions come in two versions: with and without an
input accumulator. My new IR intrinsics, like the 'experimental' one,
don't take an accumulator parameter: we represent that by just adding
on the input value using an ordinary i32 or i64 add. So if you write
the `vaddvaq` C-language intrinsic with an input accumulator of zero,
it can be optimised to VADDV, and conversely, if you write something
like `x += vaddvq(y)` then that can be combined into VADDVA.

Most of this is achieved in isel lowering, by converting these IR
intrinsics into the existing `ARMISD::VADDV` family of custom SDNode
types. For the difficult case (64-bit accumulators), isel lowering
already implements the optimization of folding an addition into a
VADDLV to make a VADDLVA; so once we've made a VADDLV, our job is
already done, except that I had to introduce a parallel set of ARMISD
nodes for the //predicated// forms of VADDLV.

For the simpler VADDV, we handle the predicated form by just leaving
the IR intrinsic alone and matching it in an ordinary dag pattern.

Reviewers: dmgreen, MarkMurrayARM, miyuki, ostannard

Reviewed By: dmgreen

Subscribers: kristof.beyls, hiraditya, danielkiss, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D76491
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.h
The file was addedclang/test/CodeGen/arm-mve-intrinsics/vaddv.c
The file was modifiedllvm/include/llvm/IR/IntrinsicsARM.td
The file was modifiedclang/include/clang/Basic/arm_mve.td
The file was modifiedllvm/lib/Target/ARM/ARMInstrMVE.td
The file was addedllvm/test/CodeGen/Thumb2/mve-intrinsics/vaddv.ll
Commit 34659de5fdd18468f062f301e64d7c883c9a5f14 by llvm-dev
[InstCombine][X86] simplifyX86immShift - convert variable in-range vector shift by scalar amounts to generic shifts (PR40391)

The sll/srl/sra scalar vector shifts can be replaced with generic shifts if the shift amount is known to be in range.

This also required public DemandedElts variants of llvm::computeKnownBits to be exposed (PR36319).
The file was modifiedllvm/include/llvm/Analysis/ValueTracking.h
The file was modifiedllvm/test/Transforms/InstCombine/X86/x86-vector-shifts.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
The file was modifiedllvm/lib/Analysis/ValueTracking.cpp
Commit ffcc076a2b23363025de2f67243086963f235b20 by erich.keane
[[Clang CallGraph]] CallGraph should still record calls to decls.

Discovered by a downstream user, we found that the CallGraph ignores
callees unless they are defined.  This seems foolish, and prevents
combining the report with other reports to create unified reports.
Additionally, declarations contain information that is likely useful to
consumers of the CallGraph.

This patch implements this by splitting the includeInGraph function into
two versions, the current one plus one that is for callees only.  The
only difference currently is that includeInGraph checks for a body, then
calls includeCalleeInGraph.

Differential Revision: https://reviews.llvm.org/D76435
The file was modifiedclang/include/clang/Analysis/CallGraph.h
The file was modifiedclang/test/Analysis/debug-CallGraph.cpp
The file was modifiedclang/lib/Analysis/CallGraph.cpp
Commit ce5173c0e174870934d1b3a026f631d996136191 by rnk
Use FinishThunk to finish musttail thunks

FinishThunk, and the invariant of setting and then unsetting
CurCodeDecl, was added in 7f416cc42638 (2015). The invariant didn't
exist when I added this musttail codepath in ab2090d10765 (2014).
Recently in 28328c3771, I started using this codepath on non-Windows
platforms, and users reported problems during release testing (PR44987).

The issue was already present for users of EH on i686-windows-msvc, so I
added a test for that case as well.

Reviewed By: hans

Differential Revision: https://reviews.llvm.org/D76444
The file was modifiedclang/lib/CodeGen/CGVTables.cpp
The file was addedclang/test/CodeGenCXX/thunks-ehspec.cpp
The file was addedclang/test/CodeGenCXX/ms-thunks-ehspec.cpp
Commit 32fbea15485dbb04ad7222ffb017a9356c159d81 by craig.topper
[X86] Prevent (bitcast (broadcast_load)) combine from producing vXf16 broadcast instructions.

The combine tries to put the broadcast in either the integer or
fp domain to match the bitcast domain. But we can only do this
if the broadcast size is 32 or larger.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 56122fcd641ae71de662575b0272994ef3a942b1 by sd.fertile
[PowerPC][AIX][NFC] Extend the test coverage of ByVal args.

Adds/changes some types in the ByVal cc test so that they aren't all
structs of arrays of bytes, and adds testing for passing multiple
ByVal arguments.
The file was modifiedllvm/test/CodeGen/PowerPC/aix-cc-byval.ll
Commit edcfb47ff6d5562e22207f364c65f84302aa346b by pirama
[DAGCombiner] Do not fold truncate(build_vector(..)) if it creates an illegal type

Summary:
It can be the case that a vector type is legal but the corresponding
scalar type is not legal for an architecture (i8 vs. v16i8 on AArch64).
Check if the scalar type created when folding
  truncate(build_vector(x,y)) -> build_vector(truncate(x),truncate(y))

is legal if we are running after the type legalizer.

This fixes https://github.com/android/ndk/issues/1207.

Reviewers: RKSimon, srhines

Subscribers: kristof.beyls, hiraditya, danielkiss, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D76312
The file was addedllvm/test/CodeGen/AArch64/dag-combine-trunc-build-vec.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit ededa65d559dac04ae50d3a33610875bb8f1a85e by gabor.marton
[analyzer] StdLibraryFunctionsChecker: Add NotNull Arg Constraint

Reviewers: NoQ, Szelethus, balazske, gamesh411, baloghadamsoftware, steakhal

Subscribers: whisperity, xazax.hun, szepet, rnkovacs, a.sidorin, mikhail.ramalho, donat.nagy, dkrupp, Charusso, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D75063
The file was modifiedclang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp
The file was modifiedclang/test/Analysis/std-c-library-functions-arg-constraints.c
The file was modifiedclang/test/Analysis/std-c-library-functions.c
Commit f59bb40e361c061adaa19e988f1f5769d3b8fac7 by gabor.marton
Attempt to fix failing build-bot with [-Werror,-Wcovered-switch-default]
The file was modifiedclang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp
Commit 942afe0cb2ac0f3fe4a5ffc52400e1819b4fd570 by liufeng.ee
[mlir/quant] fix a small typo in the quant utility

This is an edge case where the input type is a primitive type.

Differential Revision: https://reviews.llvm.org/D76442
The file was modifiedmlir/lib/Dialect/Quant/Utils/UniformSupport.cpp
Commit 0b18b568e91a3ebe3ab33d13328a1614fb94cf07 by Tatyana Krasnukha
[lldb-vscode] Don't use SBLaunchInfo in request_attach

If LLDB attaches to an already running target, then structure SBAttachInfo is
used instead of SBLaunchInfo. lldb-vscode function request_attach sets some
values to g_vsc.launch_info, however this field is then not passed anywhere, so
this action has no effect. This commit removes invocation of
SBLaunchInfo::SetDetachOnError, which has no equivalent in SBAttachInfo.

File package.json doesn't describe detachOnError property for "attach" request
type, therefore it is not needed to update it.

Differential Revision: https://reviews.llvm.org/D76351
The file was modifiedlldb/tools/lldb-vscode/lldb-vscode.cpp
Commit 3205d1a860367f7ab77d331f03086eeed194e44c by nikita.ppv
[InstCombine] Handle known shl nsw sign bit in SimplifyDemanded

Ideally SimplifyDemanded should compute the same known bits as
computeKnownBits(). This patch addresses one discrepancy, where
ValueTracking is more powerful: If we have a shl nsw shift, we
know that the sign bit of the input and output must be the same.
If this results in a conflict, the result is poison.

This is implemented in
https://github.com/llvm-mirror/llvm/blob/2c4ca6832fa6b306ee6a7010bfb80a3f2596f824/lib/Analysis/ValueTracking.cpp#L1175-L1179
and
https://github.com/llvm-mirror/llvm/blob/2c4ca6832fa6b306ee6a7010bfb80a3f2596f824/lib/Analysis/ValueTracking.cpp#L904-L908.

This implements the same basic logic in SimplifyDemanded. It's
slightly stronger, because I return undef instead of zero for the
poison case (which is not an option inside ValueTracking).

As mentioned in https://reviews.llvm.org/D75801#inline-698484,
we could detect poison in more cases, this just establishes parity
with the existing logic.

Differential Revision: https://reviews.llvm.org/D76489
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
The file was modifiedllvm/test/Transforms/InstCombine/known-signbit-shift.ll
Commit 5de4ba1770f4815dd36d449a9b64b0aec783159d by saugustine
Cleanup the plumbing for DILineInfoSpecifier. [NFC - Try 2]
The file was modifiedllvm/include/llvm/DebugInfo/Symbolize/SymbolizableModule.h
The file was modifiedllvm/include/llvm/DebugInfo/Symbolize/DIPrinter.h
The file was modifiedllvm/lib/DebugInfo/Symbolize/SymbolizableObjectFile.h
The file was modifiedllvm/include/llvm/DebugInfo/Symbolize/Symbolize.h
The file was modifiedllvm/lib/DebugInfo/Symbolize/DIPrinter.cpp
The file was modifiedllvm/tools/llvm-symbolizer/llvm-symbolizer.cpp
The file was modifiedllvm/include/llvm/DebugInfo/DIContext.h
The file was modifiedllvm/lib/DebugInfo/Symbolize/Symbolize.cpp
The file was modifiedllvm/unittests/DebugInfo/DWARF/DWARFDebugLineTest.cpp
The file was modifiedllvm/lib/DebugInfo/Symbolize/SymbolizableObjectFile.cpp
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
The file was modifiedllvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp
Commit 18e8f27ad87e4a7dfd25629a6c880ce63a450e26 by Adrian Prantl
Add missing module map entry
The file was modifiedllvm/include/llvm/module.modulemap
Commit 462db62053fba10d3961448c1a5bd653ada8a87d by ntv
[mlir][AVX512] Start a primitive AVX512 dialect

The Vector Dialect [document](https://mlir.llvm.org/docs/Dialects/Vector/) discusses the vector abstractions that MLIR supports and the various tradeoffs involved.

One of the layer that is missing in OSS atm is the Hardware Vector Ops (HWV) level.

This revision proposes an AVX512-specific to add a new Dialect/Targets/AVX512 Dialect that would directly target AVX512-specific intrinsics.

Atm, we rely too much on LLVM’s peephole optimizer to do a good job from small insertelement/extractelement/shufflevector. In the future, when possible, generic abstractions such as VP intrinsics should be preferred.

The revision will allow trading off HW-specific vs generic abstractions in MLIR.

Differential Revision: https://reviews.llvm.org/D75987
The file was addedmlir/include/mlir/Dialect/LLVMIR/LLVMAVX512.td
The file was addedmlir/lib/Conversion/AVX512ToLLVM/CMakeLists.txt
The file was addedmlir/lib/Conversion/AVX512ToLLVM/ConvertAVX512ToLLVM.cpp
The file was modifiedmlir/tools/mlir-translate/CMakeLists.txt
The file was addedmlir/lib/Dialect/AVX512/IR/AVX512Dialect.cpp
The file was addedmlir/include/mlir/Dialect/AVX512/CMakeLists.txt
The file was addedmlir/include/mlir/Dialect/AVX512/AVX512.td
The file was addedmlir/lib/Target/LLVMIR/LLVMAVX512Intr.cpp
The file was addedmlir/test/Dialect/AVX512/roundtrip.mlir
The file was modifiedmlir/lib/Dialect/CMakeLists.txt
The file was modifiedmlir/include/mlir/Dialect/LLVMIR/CMakeLists.txt
The file was addedmlir/lib/Dialect/LLVMIR/IR/LLVMAVX512Dialect.cpp
The file was addedmlir/lib/Dialect/AVX512/CMakeLists.txt
The file was addedmlir/include/mlir/Dialect/AVX512/AVX512Dialect.h
The file was modifiedmlir/lib/Conversion/CMakeLists.txt
The file was addedmlir/include/mlir/Dialect/LLVMIR/LLVMAVX512Dialect.h
The file was modifiedmlir/include/mlir/InitAllDialects.h
The file was modifiedmlir/include/mlir/InitAllPasses.h
The file was addedmlir/test/Conversion/AVX512ToLLVM/convert-to-llvm.mlir
The file was addedmlir/include/mlir/Conversion/AVX512ToLLVM/ConvertAVX512ToLLVM.h
The file was modifiedmlir/include/mlir/IR/OpImplementation.h
The file was modifiedmlir/lib/Dialect/LLVMIR/CMakeLists.txt
The file was modifiedmlir/lib/Target/CMakeLists.txt
The file was addedmlir/test/Target/avx512.mlir
The file was modifiedmlir/include/mlir/Dialect/CMakeLists.txt
Commit 636665331bbd4c369a9f33c4d35fb9a863c94646 by Vedant Kumar
PR45181: Fix another invalid DIExpression combination

The original test case from PR45181 triggers a DIExpression combination
that wasn't fixed in D76164.
The file was addedllvm/test/DebugInfo/X86/pr45181.ll
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
Commit fe5937cb33b7753ff95edbe7cbd3be549961b733 by maskray
[llc] Initialize TargetLoweringObjectFile for MIR input

MIRParser uses MC and transitively calls MCObjectFileInfo::getObjectFileType().
TargetLoweringObjectFile::Initialize should be called beforehand to
initialize MCObjectFileInfo::Env.

This manifested as a -fsanitize=undefined
test/CodeGen/MIR/X86/instr-symbols-and-mcsymbol-operands.mir failure
when D71360/aa5ee8f244441a8ea103a7e0ed8b6f3e74454516 was committed.
The file was modifiedllvm/tools/llc/llc.cpp
Commit 7899fe9da8d8df6f19ddcbbb877ea124d711c54b by maskray
[X86] Reland D71360 Clean up UseInitArray initialization for X86ELFTargetObjectFile

UseInitArray is now the CC1 default but TargetLoweringObjectFileELF::UseInitArray still defaults to false.
The following two unknown OS target triples continue using .ctors/.dtors because InitializeELF is not called.

clang -target i386 -c a.c
clang -target x86_64 -c a.c

This cleanup fixes this as a bonus.

Differential Revision: https://reviews.llvm.org/D71360
The file was modifiedllvm/lib/Target/RISCV/RISCVTargetObjectFile.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetObjectFile.cpp
The file was modifiedllvm/lib/Target/Sparc/SparcTargetObjectFile.cpp
The file was modifiedllvm/lib/Target/X86/X86TargetObjectFile.h
The file was modifiedllvm/test/CodeGen/X86/constructor.ll
The file was modifiedllvm/lib/Target/X86/X86TargetObjectFile.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
The file was modifiedllvm/lib/Target/X86/X86TargetMachine.cpp
The file was modifiedllvm/test/CodeGen/X86/init-priority.ll
The file was modifiedllvm/lib/Target/Mips/MipsTargetObjectFile.cpp
The file was modifiedllvm/lib/Target/Lanai/LanaiTargetObjectFile.cpp
The file was modifiedllvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCTargetObjectFile.cpp
Commit 06dea73307e75f0227ba24cab2adf2e4dad62b88 by a.bataev
[OPENMP50]Initial support for inclusive clause.

Added parsing/sema/serialization support for inclusive clause in scan
directive.
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/lib/Basic/OpenMPKinds.cpp
The file was modifiedclang/lib/Sema/TreeTransform.h
The file was modifiedclang/include/clang/AST/OpenMPClause.h
The file was modifiedclang/lib/Parse/ParseOpenMP.cpp
The file was modifiedclang/test/OpenMP/scan_ast_print.cpp
The file was modifiedclang/test/OpenMP/scan_messages.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/include/clang/AST/RecursiveASTVisitor.h
The file was modifiedclang/lib/AST/OpenMPClause.cpp
The file was modifiedclang/include/clang/Basic/OpenMPKinds.def
The file was modifiedclang/test/OpenMP/nesting_of_regions.cpp
The file was modifiedclang/tools/libclang/CIndex.cpp
The file was modifiedclang/lib/CodeGen/CGStmtOpenMP.cpp
The file was modifiedclang/lib/Serialization/ASTReader.cpp
The file was modifiedclang/lib/Serialization/ASTWriter.cpp
The file was modifiedclang/lib/AST/StmtProfile.cpp
The file was modifiedclang/lib/Sema/SemaOpenMP.cpp
Commit 7efbd851adf3124f7e756c37348ddd3ff7427ad7 by Louis Dionne
[libc++] Add a new FILE_DEPENDENCIES parser

Instead of considering all the .dat files to be dependencies of a test,
only consider those that are listed in FILE_DEPENDENCIES.
The file was modifiedlibcxx/test/libcxx/input.output/file.streams/fstreams/ifstream.cons/wchar_pointer.pass.cpp
The file was modifiedlibcxx/test/std/input.output/file.streams/fstreams/ifstream.cons/pointer.pass.cpp
The file was modifiedlibcxx/test/std/input.output/file.streams/fstreams/ifstream.members/open_path.pass.cpp
The file was modifiedlibcxx/utils/libcxx/test/format.py
The file was modifiedlibcxx/test/std/input.output/file.streams/fstreams/ifstream.members/close.pass.cpp
The file was modifiedlibcxx/test/std/input.output/file.streams/fstreams/ifstream.assign/nonmember_swap.pass.cpp
The file was modifiedlibcxx/test/std/input.output/file.streams/fstreams/ifstream.cons/move.pass.cpp
The file was modifiedlibcxx/test/std/input.output/file.streams/fstreams/ifstream.members/open_pointer.pass.cpp
The file was modifiedlibcxx/test/libcxx/input.output/file.streams/fstreams/ifstream.members/open_wchar_pointer.pass.cpp
The file was modifiedlibcxx/test/std/localization/locales/locale.convenience/conversions/conversions.buffer/pbackfail.pass.cpp
The file was modifiedlibcxx/test/std/input.output/file.streams/fstreams/filebuf.virtuals/underflow.pass.cpp
The file was modifiedlibcxx/test/std/input.output/file.streams/fstreams/ifstream.assign/member_swap.pass.cpp
The file was modifiedlibcxx/test/std/input.output/file.streams/fstreams/ifstream.assign/move_assign.pass.cpp
The file was modifiedlibcxx/test/std/input.output/file.streams/fstreams/filebuf.virtuals/seekoff.pass.cpp
The file was modifiedlibcxx/test/std/input.output/file.streams/fstreams/ifstream.members/open_string.pass.cpp
The file was modifiedlibcxx/test/std/input.output/file.streams/fstreams/ifstream.cons/path.pass.cpp
The file was modifiedlibcxx/test/std/input.output/file.streams/fstreams/ifstream.members/rdbuf.pass.cpp
The file was modifiedlibcxx/test/std/localization/locales/locale.convenience/conversions/conversions.buffer/underflow.pass.cpp
The file was modifiedlibcxx/test/std/input.output/file.streams/fstreams/ifstream.cons/string.pass.cpp
Commit 25294708f5ee8c0063c9ff20b862aa71cf0eeaad by sivachandra
[libc] NFC - Move the round redirector from its own nested directory.

We have moved away from directories for entrypoints but this function
was not moved out.

Submitting as obvious.
The file was modifiedlibc/src/math/CMakeLists.txt
The file was addedlibc/src/math/round.h
The file was addedlibc/src/math/round.cpp
The file was removedlibc/src/math/round/round.h
The file was removedlibc/src/math/round/CMakeLists.txt
The file was removedlibc/src/math/round/round.cpp
The file was addedlibc/src/math/round_redirector.cpp
The file was removedlibc/src/math/round/round_redirector.cpp
Commit 4716ebb823e4a3953d7ea803db1949ff699b96c8 by Vedant Kumar
[ADT] CoalescingBitVector: Avoid initial heap allocation, NFC

Avoid making a heap allocation when constructing a CoalescingBitVector.

This reduces time spent in LiveDebugValues when compiling sqlite3 by
700ms (0.5% of the total User Time).

rdar://60046261

Differential Revision: https://reviews.llvm.org/D76465
The file was modifiedllvm/lib/CodeGen/LiveDebugValues.cpp
The file was modifiedllvm/include/llvm/ADT/CoalescingBitVector.h
The file was modifiedllvm/unittests/ADT/CoalescingBitVectorTest.cpp
Commit a3fd1a1c744f4fa0bdefc77f5ec00141fb1f6d2a by Vedant Kumar
[ADT] CoalescingBitVector: Add advanceToLowerBound iterator operation

advanceToLowerBound moves an iterator to the first bit set at, or after,
the given index. This can be faster than doing IntervalMap::find.

rdar://60046261

Differential Revision: https://reviews.llvm.org/D76466
The file was modifiedllvm/include/llvm/ADT/CoalescingBitVector.h
The file was modifiedllvm/unittests/ADT/CoalescingBitVectorTest.cpp
Commit a24594335513f1ecf07a785a6633f9d3956c0ad2 by Vedant Kumar
[LiveDebugValues] Speed up collectIDsForRegs, NFC

Use the advanceToLowerBound operation available on CoalescingBitVector
iterators to speed up collection of variables which reside within some
set of registers.

The speedup comes from avoiding repeated top-down traversals in
IntervalMap::find. The linear scan forward from one register interval to
the next is unlikely to be as expensive as a full IntervalMap search
starting from the root.

This reduces time spent in LiveDebugValues when compiling sqlite3 by
200ms (about 0.1% - 0.2% of the total User Time).

Depends on D76466.

rdar://60046261

Differential Revision: https://reviews.llvm.org/D76467
The file was modifiedllvm/lib/CodeGen/LiveDebugValues.cpp
Commit 7ec24448801c30bb0b2127f2c7b7ac10c1a009fc by Vedant Kumar
unittest: Work around build failure on MSVC builders

MSVC insists on using the deleted move constructor instead of the copy
constructor:

http://lab.llvm.org:8011/builders/lld-x86_64-win7/builds/41203

C:\ps4-buildslave2\lld-x86_64-win7\llvm-project\llvm\unittests\ADT\CoalescingBitVectorTest.cpp(193):
error C2280: 'llvm::CoalescingBitVector<unsigned
int,16>::CoalescingBitVector(llvm::CoalescingBitVector<unsigned int,16>
&&)': attempting to reference a deleted function
The file was modifiedllvm/unittests/ADT/CoalescingBitVectorTest.cpp
Commit 9b95929a26e133bc3cae9f29f91e8e351d233840 by a.bataev
[OPENMP50]Do not allow several scan directives in the same parent
region.

According to OpenMP 5.0, exactly one scan directive must appear in the loop body of an enclosing worksharing-loop, worksharing-loop SIMD, or simd construct on which a reduction clause with the inscan modifier is present.
The file was modifiedclang/lib/Sema/SemaOpenMP.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/test/OpenMP/scan_messages.cpp
Commit 2b52e4e629e6793f832caef5e47f9d84607740f3 by nikita.ppv
[InstCombine] Remove known bits constant folding

If ExpensiveCombines is enabled (which is the case with -O3 on the
legacy PM and always on the new PM), InstCombine tries to compute
the known bits of all instructions in the hope that all bits end up
being known, which is fairly expensive.

How effective is it? If we add some statistics on how often the
constant folding succeeds and how many KnownBits calculations are
performed and run test-suite we get:

    "instcombine.NumConstPropKnownBits": 642,
    "instcombine.NumConstPropKnownBitsComputed": 18744965,

In other words, we get one fold for every 30000 KnownBits calculations.
However, the truth is actually much worse: Currently, known bits are
computed before performing other folds, so there is a high chance
that cases that get folded by known bits would also have been
handled by other folds.

What happens if we compute known bits after all other folds
(hacky implementation: https://gist.github.com/nikic/751f25b3b9d9e0860db5dde934f70f46)?

    "instcombine.NumConstPropKnownBits": 0,
    "instcombine.NumConstPropKnownBitsComputed": 18105547,

So it turns out despite doing 18 million known bits calculations,
the known bits fold does not do anything useful on test-suite.
I was originally planning to move this into AggressiveInstCombine
so it only runs once in the pipeline, but seeing this, I think
we're better off removing it entirely.

As this is the only use of the "expensive combines" mechanism,
it may be removed afterwards, but I'll leave that to a separate patch.

Differential Revision: https://reviews.llvm.org/D75801
The file was modifiedllvm/test/Transforms/InstCombine/phi-shifts.ll
The file was modifiedllvm/test/Transforms/InstCombine/known-signbit-shift.ll
The file was modifiedllvm/test/Transforms/InstCombine/out-of-bounds-indexes.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstructionCombining.cpp
The file was modifiedllvm/test/Transforms/InstCombine/assume.ll
Commit be4e9db5799a4d1c2350859b4582bbf25e39fff9 by hanchung
[mlir][Linalg] NFC: Clean up for 0-D abstraction.

Summary:
After D75831 has been landed, both the generic op and indexed_generic op can
handle 0-D edge case. In the previous patch, only generic op has been updated.
This patch updates the lowering to loops for indexed_generic op. Since they are
almost the sanme, the patch also refactors the common part.

Differential Revision: https://reviews.llvm.org/D76413
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/LinalgToLoops.cpp
Commit 08a9147349ea1dd80365951dee2375ede6ac49c2 by ataei
[mlir][LLVMIR] Fix fusion for rank-0 tensors

Summary: This diff fixes fusion craching for ops with rank-0 tensors

Reviewers: mravishankar, nicolasvasilache, rriddle!

Subscribers: mehdi_amini, rriddle, jpienaar, burmako, shauheen, antiagainst, arpith-jacob, mgester, lucyrfox, liufengdb, Joonsoo, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D76479
The file was modifiedmlir/lib/IR/AffineMap.cpp
The file was modifiedmlir/test/Dialect/Linalg/fusion-tensor.mlir
Commit fe5599eac6a57ad5a354e3b6fec9e97332304bac by pirama
[llvm-ar] Use target triple to deduce archive kind for bitcode inputs

Summary:
When using full LTO on cross-compile settings, instead of generating the
default archive kind of the host platform, we could deduce the archive
kind based on the target triple.

This specifically addresses https://github.com/android/ndk/issues/1209
by making it possible to drop llvm-ar in place of GNU ar without extra
flags.

Reviewers: compnerd, pcc, srhines, danalbert

Subscribers: hiraditya, MaskRay, steven_wu, dexonsmith, rupprecht, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D76461
The file was addedllvm/test/tools/llvm-ar/lto-kind-from-triple.test
The file was modifiedllvm/tools/llvm-ar/llvm-ar.cpp