SuccessChanges

Summary

  1. Fix printer for llvm.addressof symbol name that need escaping (details)
  2. [Hexagon] Add support for Hexagon/HVX v67 ISA (details)
  3. AMDGPU: Partially merge indirect register write handling (details)
  4. AMDGPU: Prepare to use scalar register indexing (details)
  5. AMDGPU: Cleanup and generate 64-bit div tests (details)
Commit fdb9cc7dc560f6e56df55dd4be1c88b83636184d by aminim
Fix printer for llvm.addressof symbol name that need escaping
Differential Revision: https://reviews.llvm.org/D73065
The file was modifiedmlir/test/Dialect/LLVMIR/global.mlir
The file was modifiedmlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
Commit c12a5917d2f2ace092118e638913b1c45888363e by kparzysz
[Hexagon] Add support for Hexagon/HVX v67 ISA
The file was modifiedllvm/lib/Target/Hexagon/HexagonDepInstrInfo.td
The file was addedllvm/lib/Target/Hexagon/HexagonDepMask.h
The file was modifiedllvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonDepTimingClasses.h
The file was modifiedllvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
The file was modifiedllvm/lib/Target/Hexagon/HexagonPatterns.td
The file was modifiedllvm/lib/Target/Hexagon/HexagonDepArch.h
The file was modifiedllvm/lib/ObjectYAML/ELFYAML.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonDepIICHVX.td
The file was modifiedllvm/lib/Target/Hexagon/HexagonDepITypes.h
The file was modifiedllvm/test/CodeGen/Hexagon/swp-sigma.ll
The file was modifiedllvm/lib/Target/Hexagon/HexagonSchedule.td
The file was modifiedllvm/lib/Target/Hexagon/HexagonISelLowering.cpp
The file was modifiedllvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
The file was addedllvm/test/MC/Hexagon/v67_all.s
The file was modifiedllvm/lib/Target/Hexagon/Hexagon.td
The file was modifiedclang/include/clang/Basic/BuiltinsHexagon.def
The file was addedllvm/test/MC/Hexagon/extensions/v67_hvx.s
The file was modifiedclang/test/Driver/hexagon-toolchain-elf.c
The file was modifiedllvm/lib/Target/Hexagon/HexagonDepOperands.td
The file was modifiedllvm/lib/Target/Hexagon/HexagonDepInstrFormats.td
The file was modifiedllvm/lib/Target/Hexagon/HexagonInstrFormats.td
The file was modifiedllvm/lib/Target/Hexagon/HexagonDepMappings.td
The file was modifiedclang/include/clang/Driver/Options.td
The file was removedllvm/lib/Target/Hexagon/HexagonInstrFormatsV5.td
The file was addedllvm/test/CodeGen/Hexagon/fmul-v67.ll
The file was modifiedllvm/lib/Target/Hexagon/HexagonDepITypes.td
The file was addedllvm/test/CodeGen/Hexagon/fminmax-v67.ll
The file was addedllvm/test/MC/Hexagon/v67.s
The file was modifiedllvm/lib/Target/Hexagon/HexagonDepArch.td
The file was modifiedclang/lib/Basic/Targets/Hexagon.h
The file was addedllvm/lib/Target/Hexagon/HexagonScheduleV67.td
The file was addedllvm/test/CodeGen/Hexagon/intrinsics-v67.ll
The file was modifiedllvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonPseudo.td
The file was modifiedllvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td
The file was modifiedllvm/lib/Target/Hexagon/HexagonSubtarget.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonSubtarget.h
The file was addedllvm/lib/Target/Hexagon/HexagonArch.h
The file was modifiedllvm/lib/Target/Hexagon/HexagonDepDecoders.inc
The file was modifiedclang/include/clang/Basic/BuiltinsHexagonDep.def
The file was modifiedclang/lib/Basic/Targets/Hexagon.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
The file was modifiedllvm/include/llvm/BinaryFormat/ELF.h
The file was modifiedllvm/include/llvm/IR/IntrinsicsHexagonDep.td
The file was modifiedclang/test/Preprocessor/hexagon-predefines.c
The file was addedclang/test/CodeGen/builtins-hexagon-v67-audio.c
The file was addedllvm/test/CodeGen/Hexagon/df-min-max.ll
The file was addedclang/test/CodeGen/builtins-hexagon-v67.c
The file was modifiedllvm/lib/Target/Hexagon/HexagonDepIICScalar.td
Commit 8615eeb455618fabe962f6951ccd8fe95b26bb15 by arsenm2
AMDGPU: Partially merge indirect register write handling
a785209bc2fb switched to using a pseudos instead of manually tying
operands on the regular instruction. The VGPR indexing mode path should
have the same problems that change attempted to avoid, so these should
use the same strategy.
Use a single pseudo for the VGPR indexing mode and movreld paths, and
expand it based on the subtarget later. These have essentially the same
constraints, reading the index from m0.
Switch from using an offset to the subregister index directly, instead
of computing an offset and re-adding it back. Also add missing pseudos
for existing register class sizes.
The file was modifiedllvm/lib/Target/AMDGPU/VOP1Instructions.td
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Commit 9b13b4a0e3a192a3b0d938bfaa71ce6dc0740ece by arsenm2
AMDGPU: Prepare to use scalar register indexing
Define pseudos mirroring the the VGPR indexing ones, and adjust the
operands in the s_movrel* instructions to avoid the result def.
The file was modifiedllvm/lib/Target/AMDGPU/VOP1Instructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/inserted-wait-states.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/SOPInstructions.td
Commit 317fdcd09ae9df1eaf1da40443d59b8b2bf68b8b by arsenm2
AMDGPU: Cleanup and generate 64-bit div tests
Split out r600 tests, and try to be more consistent with coverage. Cover
a few more cases for 24-bit optimization and constants.
The file was addedllvm/test/CodeGen/AMDGPU/sdiv64.ll
The file was addedllvm/test/CodeGen/AMDGPU/urem64.ll
The file was addedllvm/test/CodeGen/AMDGPU/sdivrem64.r600.ll
The file was addedllvm/test/CodeGen/AMDGPU/udiv64.ll
The file was removedllvm/test/CodeGen/AMDGPU/sdivrem64.ll
The file was removedllvm/test/CodeGen/AMDGPU/udivrem64.ll
The file was addedllvm/test/CodeGen/AMDGPU/udivrem64.r600.ll
The file was addedllvm/test/CodeGen/AMDGPU/srem64.ll