Commit
e6b0ce70bdd888f4c1863941db8928040bbc2eff
by martin[LLD] [COFF] Silence a GCC warning about an unused variable. NFC.
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 | lld/COFF/Driver.cpp |
Commit
98da49d979198366d4710ac65a3786b9a8f3b4c1
by llvm-dev[SelectionDAG] Compute Known + Sign Bits - merge INSERT_SUBVECTOR known/unknown index paths Match the approach in SimplifyDemandedBits where we calculate the demanded elts and then have a common path for the ComputeKnownBits/ComputeNumSignBits call, additionally we only ever need original demanded elts of the base vector even if the index is unknown.
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 | llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp |
Commit
03cae086f41c48a971329dc5a1f4a76c1c6af036
by llvm-dev[SelectionDAG] ComputeKnownBits - merge EXTRACT_VECTOR_ELT known/unknown index paths Match the approach in SimplifyDemandedBits/ComputeNumSignBits where we calculate the demanded elts and then have a common path for the ComputeKnownBits call.
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 | llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp |
Commit
f1ad192915f64e3eeedfb01aa1073e81bff4e1a1
by thomasp[FileCheck] Strengthen error checks in unit tests Summary: This commit adds error checking beyond UndefVarError and fix a number of Error/Expected related idioms: - use (EXPECT|ASSERT)_THAT_(ERROR|EXPECTED) instead of errorToBool or boolean operator - ASSERT when a further check require the check to be successful to give a correct result Reviewers: jhenderson, jdenny, probinson, grimar, arichardson, rnk Reviewed By: jhenderson Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72914
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 | llvm/unittests/Support/FileCheckTest.cpp |
Commit
e8fc8507dacbab119a1ca14535d7c75f0514a078
by Milos.Stojanovic[llvm-exegesis] Don't use unsupported aliasing instructions Since some instruction types aren't allowed as the main instruction also don't allow them for aliasing instructions. Differential Revision: https://reviews.llvm.org/D73220
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 | llvm/tools/llvm-exegesis/lib/SerialSnippetGenerator.cpp |
Commit
772e4931932270a82f38c83d4344c800b2f54eff
by simon.tatham[ARM,MVE] Revise immediate VBIC/VORR to look more like NEON. Summary: In NEON, the immediate forms of VBIC and VORR are each represented as a single MC instruction, which takes its immediate operand already encoded in a NEON-friendly format: 8 data bits, plus some control bits indicating how to expand them into a full vector. In MVE, we represented immediate VBIC and VORR as four separate MC instructions each, for an 8-bit immediate shifted left by 0, 8, 16 or 24 bits. For each one, the value of the immediate operand is in the 'natural' form, i.e. the numerical value that would actually be BICed or ORRed into each vector lane (and also the same value shown in assembly). For example, MVE_VBICIZ16v4i32 takes an operand such as 0xab0000, which NEON would represent as 0xab | (control bits << 8). The MVE approach is superficially nice (it makes assembly input and output easy, and it's also nice if you're manually constructing immediate VBICs). But it turns out that it's better for isel if we make the NEON and MVE instructions work the same, because the ARMISD::VBICIMM and VORRIMM node types already encode their immediate into the NEON format, so it's easier if we can just use it. Also, this commit reduces the total amount of code rather than increasing it, which is surely an indication that it really is simpler to do it this way! Reviewers: dmgreen, ostannard, miyuki, MarkMurrayARM Reviewed By: dmgreen Subscribers: kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D73205
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 | llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp |
 | llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp |
 | llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp |
 | llvm/unittests/Target/ARM/MachineInstrTest.cpp |
 | llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h |
 | llvm/lib/Target/ARM/ARMInstrMVE.td |
 | llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp |
Commit
4321c6af28e9cc26d385fc388b8f0a74b32741c1
by simon.tatham[ARM,MVE] Support immediate vbicq,vorrq,vmvnq intrinsics. Summary: Immediate vmvnq is code-generated as a simple vector constant in IR, and left to the backend to recognize that it can be created with an MVE VMVN instruction. The predicated version is represented as a select between the input and the same constant, and I've added a Tablegen isel rule to turn that into a predicated VMVN. (That should be better than the previous VMVN + VPSEL: it's the same number of instructions but now it can fold into an adjacent VPT block.) The unpredicated forms of VBIC and VORR are done by enabling the same isel lowering as for NEON, recognizing appropriate immediates and rewriting them as ARMISD::VBICIMM / ARMISD::VORRIMM SDNodes, which I then instruction-select into the right MVE instructions (now that I've also reworked those instructions to use the same MC operand encoding). In order to do that, I had to promote the Tablegen SDNode instance `NEONvorrImm` to a general `ARMvorrImm` available in MVE as well, and similarly for `NEONvbicImm`. The predicated forms of VBIC and VORR are represented as a vector select between the original input vector and the output of the unpredicated operation. The main convenience of this is that it still lets me use the existing isel lowering for VBICIMM/VORRIMM, and not have to write another copy of the operand encoding translation code. This intrinsic family is the first to use the `imm_simd` system I put into the MveEmitter tablegen backend. So, naturally, it showed up a bug or two (emitting bogus range checks and the like). Fixed those, and added a full set of tests for the permissible immediates in the existing Sema test. Also adjusted the isel pattern for `vmovlb.u8`, which stopped matching because lowering started turning its input into a VBICIMM. Now it recognizes the VBICIMM instead. Reviewers: dmgreen, MarkMurrayARM, miyuki, ostannard Reviewed By: dmgreen Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D72934
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 | llvm/lib/Target/ARM/ARMISelLowering.cpp |
 | clang/include/clang/Basic/arm_mve.td |
 | clang/test/Sema/arm-mve-immediates.c |
 | clang/include/clang/Basic/arm_mve_defs.td |
 | clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c |
 | llvm/lib/Target/ARM/ARMInstrInfo.td |
 | clang/utils/TableGen/MveEmitter.cpp |
 | llvm/lib/Target/ARM/ARMInstrNEON.td |
 | clang/include/clang/Sema/Sema.h |
 | llvm/lib/Target/ARM/ARMInstrMVE.td |
 | llvm/test/CodeGen/Thumb2/mve-intrinsics/bitwise-imm.ll |
 | clang/lib/Sema/SemaChecking.cpp |
Commit
aa0f37e14a877bf5bb7c28506b94a8a0ea6d4791
by kerry.mclaughlin[AArch64][SVE] Add first-faulting load intrinsic Summary: Implements the llvm.aarch64.sve.ldff1 intrinsic and DAG combine rules for first-faulting loads with sign & zero extends Reviewers: sdesmalen, efriedma, andwar, dancgr, rengolin Reviewed By: sdesmalen Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cameron.mcinally, cfe-commits, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D73025
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 | llvm/test/CodeGen/AArch64/sve-intrinsics-loads-ff.ll |
 | llvm/lib/Target/AArch64/AArch64InstrInfo.td |
 | llvm/lib/Target/AArch64/AArch64ISelLowering.h |
 | llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td |
 | llvm/lib/Target/AArch64/SVEInstrFormats.td |
 | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp |
 | llvm/include/llvm/IR/IntrinsicsAArch64.td |
Commit
1e0174a93cfd364bffd12abc8f0148509d0d0f75
by krasimirTreat C# `using` as a control statement Contributed by jbcoe! Summary: Unless SpaceBeforeParensOptions is set to SBPO_Never, a space will be put between `using` and `(` in C# code. Reviewers: klimek, MyDeveloperDay, krasimir Reviewed By: krasimir Subscribers: MyDeveloperDay, cfe-commits Tags: #clang-format, #clang Differential Revision: https://reviews.llvm.org/D72144
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 | clang/lib/Format/TokenAnnotator.cpp |
 | clang/unittests/Format/FormatTestCSharp.cpp |
Commit
279fa8e0064e3d0bd1646b8efdb94045585dd924
by gchatelet[Alignement][NFC] Deprecate untyped CreateAlignedLoad Summary: This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: arsenm, jvesely, nhaehnle, hiraditya, kerbowa, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D73260
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 | llvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp |
 | llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp |
 | llvm/lib/Target/X86/X86ISelLowering.cpp |
 | llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp |
 | llvm/lib/Target/X86/X86InterleavedAccess.cpp |
 | llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp |
 | llvm/lib/Target/ARM/ARMParallelDSP.cpp |
 | llvm/lib/CodeGen/AtomicExpandPass.cpp |
 | llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp |
 | llvm/lib/Transforms/Scalar/SROA.cpp |
 | llvm/lib/Transforms/Vectorize/LoopVectorize.cpp |
 | llvm/include/llvm/IR/Instructions.h |
 | llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp |
 | llvm/lib/IR/AutoUpgrade.cpp |
 | llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp |
 | llvm/lib/Transforms/Scalar/Scalarizer.cpp |
 | llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp |
 | llvm/include/llvm/IR/IRBuilder.h |
 | llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp |
 | llvm/lib/CodeGen/ScalarizeMaskedMemIntrin.cpp |
 | llvm/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp |
Commit
2f6987ba61cc31c16c64f511e5cbc76b52dc67b3
by fedor.sergeev[LoopRotate] add ability to repeat loop rotation until non-deoptimizing exit is found In case of loops with multiple exit where all-but-one exit are deoptimizing it might happen that the first rotation will end up with latch having a deoptimizing exit. This makes the loop unsuitable for trip-count analysis (say, getLoopEstimatedTripCount) as well as for loop transformations that know how to handle multple deoptimizing exits. It pretty much means that canonical form in multple-deoptimizing-exits case should be with non-deoptimizing exit at latch. Teach loop-rotation to reach this canonical form by repeating rotation. -loop-rotate-multi option introduced to control this behavior, currently disabled by default. Reviewers: skatkov, asbirlea, reames, fhahn Reviewed By: skatkov Tags: #llvm Differential Revision: https://reviews.llvm.org/D73058
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 | llvm/unittests/Transforms/Utils/CMakeLists.txt |
 | llvm/test/Transforms/LoopRotate/multiple-deopt-exits.ll |
 | llvm/lib/Transforms/Utils/LoopRotationUtils.cpp |
 | llvm/unittests/Transforms/Utils/LoopRotationUtilsTest.cpp |
Commit
48d4ba8fb2954d58d24f1ffe9f38045c537cf7b3
by llvm-dev[SelectionDAG] Compute Known + Sign Bits - merge INSERT_VECTOR_ELT known/unknown index paths Match the approach in SimplifyDemandedBits where we calculate the demanded elts and then have a common path for the ComputeKnownBits/ComputeNumSignBits call.
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 | llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp |
Commit
0d1468db58535900270a3d3d10ed61d7d45dc4b9
by sam.parker[NFC][RDA] Make the interface const Make all the public query methods const.
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 | llvm/include/llvm/CodeGen/ReachingDefAnalysis.h |
 | llvm/lib/CodeGen/ReachingDefAnalysis.cpp |
Commit
d6a97b049f754f899112dc7b43a746269f7d3026
by llvmgnsyncbot[gn build] Port 2f6987ba61c
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 | llvm/utils/gn/secondary/llvm/unittests/Transforms/Utils/BUILD.gn |
Commit
b482e1bfe29d135dc974bb21b87f95e95dfd605a
by jay.foad[CodeGen] Make use of MachineInstrBuilder::getReg Reviewers: arsenm Subscribers: wdng, hiraditya, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D73262
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 | llvm/unittests/CodeGen/GlobalISel/ConstantFoldingTest.cpp |
 | llvm/lib/Target/AArch64/AArch64CallLowering.cpp |
 | llvm/lib/Target/X86/X86CallLowering.cpp |
 | llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp |
 | llvm/lib/CodeGen/MachineSSAUpdater.cpp |
 | llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp |
 | llvm/lib/Target/ARM/ARMInstructionSelector.cpp |
 | llvm/unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp |
 | llvm/unittests/CodeGen/GlobalISel/PatternMatchTest.cpp |
 | llvm/lib/CodeGen/GlobalISel/CallLowering.cpp |
 | llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp |
 | llvm/unittests/CodeGen/GlobalISel/CSETest.cpp |
 | llvm/lib/Target/X86/X86InstrInfo.cpp |
Commit
c8695ba9cdebfc25af3312a84d91ae6f0f98487b
by zinenkoRevert "[mlir] Add baseAttr to TypedArrayAttrBase." This reverts commit eec36909c18b8788773abc95d199e6acde6eb42c. This modeling is incorrect. baseAttr is intended for attribute decorators that are not backed by C++ attribute classes. It essentially says DerivedAttr isa BaseAttr, which is wrong for ArrayAttr classes. If one needs to store the element type, it should be stored as a separate filed in the tablegen class.
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 | mlir/include/mlir/IR/OpBase.td |
Commit
ce23515f5ab01161c98449d833b3ae013b553aa8
by luke.drummond[tablegen] Emit string literals instead of char arrays This changes the generated (Instr|Asm|Reg|Regclass)Name tables from this form: extern const char HexagonInstrNameData[] = { /* 0 */ 'G', '_', 'F', 'L', 'O', 'G', '1', '0', 0, /* 9 */ 'E', 'N', 'D', 'L', 'O', 'O', 'P', '0', 0, /* 18 */ 'V', '6', '_', 'v', 'd', 'd', '0', 0, /* 26 */ 'P', 'S', '_', 'v', 'd', 'd', '0', 0, [...] }; ...to this: extern const char HexagonInstrNameData[] = { /* 0 */ "G_FLOG10\0" /* 9 */ "ENDLOOP0\0" /* 18 */ "V6_vdd0\0" /* 26 */ "PS_vdd0\0" [...] }; This should make debugging and exploration a lot easier for mortals, while providing a significant compile-time reduction for common compilers. To avoid issues with low implementation limits, this is disabled by default for visual studio or when cross-compiling. To force output one way or the other, pass `--long-string-literals=<bool>` to `tablegen` Reviewers: mstorsjo, rnk Subscribers: llvm-commit Differential Revision: https://reviews.llvm.org/D73044
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 | llvm/cmake/modules/TableGen.cmake |
 | llvm/utils/TableGen/AsmWriterEmitter.cpp |
 | llvm/utils/TableGen/RegisterInfoEmitter.cpp |
 | llvm/utils/TableGen/InstrInfoEmitter.cpp |
 | llvm/utils/TableGen/SequenceToOffsetTable.h |
 | llvm/utils/TableGen/TableGen.cpp |
Commit
98ea4b30c2c4e122defce039e29f7023aa2663e7
by simon.tatham[ARM,MVE] Make the MVE intrinsics work in C++! Summary: Apparently nobody has tried this in months of development. It turns out that `FunctionDecl::getBuiltinID` will never consider a function to be a builtin if it is in C++ and not extern "C". So none of the function declarations in <arm_mve.h> are recognized as builtins when clang is compiling in C++ mode: it just emits calls to them as ordinary functions, which then turn out not to exist at link time. The trivial fix is to wrap most of arm_mve.h in an extern "C". Added a test in clang/test/CodeGen/arm-mve-intrinsics which checks basic functioning of the MVE header file in C++ mode. I've filled it with copies of existing test functions from other files in that directory, including a few moderately tricky cases of overloading (in particular one that relies on the strict-polymorphism attribute added in D72518). (I considered making //every// test in that directory compile in both C and C++ mode and check the code generation was identical. But I think that would increase testing time by more than the value it adds, and also update_cc_test_checks gets confused when the output function name varies between RUN lines.) Reviewers: LukeGeeson, MarkMurrayARM, miyuki, dmgreen Reviewed By: MarkMurrayARM Subscribers: kristof.beyls, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D73268
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 | clang/utils/TableGen/MveEmitter.cpp |
 | clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp |
Commit
9187073f3e051903b4c1f86e5fce0e1c819a1c34
by simon.moll[VE][NFC] re-write RR* isel class using null_frag Summary: Re-write RR* using null_frag to avoid duplication in upcoming patches. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D73259
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 | llvm/lib/Target/VE/VEInstrInfo.td |
Commit
24364cd12bbfa2e58fa74bfb49d4ea85c64c0951
by kadircet[clang][CodeComplete] Make completion work after initializer lists Summary: CodeCompletion was not being triggered after successfully parsed initializer lists, e.g. ```cpp void foo(int, bool); void bar() { foo({1}^, false); } ``` CodeCompletion would suggest the function foo as an overload candidate up until the point marked with `^` but after that point we do not trigger signature help since parsing succeeds. This patch handles that case by failing in parsing expression lists whenever we see a codecompletion token, in addition to getting an invalid subexpression. Reviewers: sammccall Subscribers: cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D73177
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 | clang/lib/Parse/ParseExpr.cpp |
 | clang/test/CodeCompletion/call.cpp |
Commit
41784bed01543315a1d03141e6ddc023fd914c0b
by kazuRevert "Resubmit: [JumpThreading] Thread jumps through two basic blocks" This reverts commit 53b68e676faf208b4a8f817e9bd4ddd522cc6006. Our internal tests are showing breakage with this patch.
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 | llvm/include/llvm/Transforms/Scalar/JumpThreading.h |
 | llvm/test/Transforms/JumpThreading/thread-two-bbs1.ll |
 | llvm/test/Transforms/JumpThreading/thread-two-bbs3.ll |
 | llvm/test/Transforms/JumpThreading/thread-two-bbs2.ll |
 | llvm/lib/Transforms/Scalar/JumpThreading.cpp |
Commit
784204fd7edd56ebfe6f7aafc68f56a0692613be
by simon.moll[VE] add, sub, left/right shift isel patterns Summary: Add, sub, left/right shift isel patterns and tests for i32/i64 and fp32/fp64. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D73207
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 | llvm/lib/Target/VE/VEInstrInfo.td |
 | llvm/test/CodeGen/VE/subtraction.ll |
 | llvm/test/CodeGen/VE/left_shift.ll |
 | llvm/test/CodeGen/VE/addition.ll |
 | llvm/test/CodeGen/VE/right_shift.ll |
Commit
a8c5a461a8e81684d28ca06eb2f65bf43a88e03b
by a.v.lapshin[Dsymutil][Debuginfo][NFC] #4 Refactor dsymutil to separate DWARF optimizing part. Summary: The primary goal of this refactoring is to separate DWARF optimizing part. So that it could be reused by linker or by any other client. There was a thread on llvm-dev discussing the necessity of such a refactoring: http://lists.llvm.org/pipermail/llvm-dev/2019-September/135068.html. This is a final part from series of patches for dsymutil. Previous patches : D71068, D71839, D72476. This patch: 1. Creates lib/DWARFLinker interface : void addObjectFile(DwarfLinkerObjFile &ObjFile); bool link(); void setOptions; 1. Moves all linking logic from tools/dsymutil/DwarfLinkerForBinary into lib/DWARFLinker. 2. Renames RelocationManager into AddressesManager. 3. Remarks creation logic moved from separate parallel execution into object file loading routine. Testing: it passes "check-all" lit testing. MD5 checksum for clang .dSYM bundle matches for the dsymutil with/without that patch. Reviewers: JDevlieghere, friss, dblaikie, aprantl, jdoerfert Reviewed By: JDevlieghere Subscribers: merge_guards_bot, hiraditya, jfb, llvm-commits, probinson, thegameg Tags: #llvm, #debug-info Differential Revision: https://reviews.llvm.org/D72915
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 | llvm/tools/dsymutil/DwarfLinkerForBinary.h |
 | llvm/tools/dsymutil/LinkUtils.h |
 | llvm/include/llvm/CodeGen/DIE.h |
 | llvm/include/llvm/DWARFLinker/DWARFLinker.h |
 | llvm/tools/dsymutil/DwarfLinkerForBinary.cpp |
 | llvm/lib/DWARFLinker/DWARFLinker.cpp |
 | llvm/tools/dsymutil/DwarfStreamer.cpp |
Commit
e464b31c1565204e3be114d043bcbf4de61fe2e9
by jaskiewiczsRevert "[tablegen] Emit string literals instead of char arrays" This reverts commit ce23515f5ab01161c98449d833b3ae013b553aa8. That commit broke some builds on Windows: http://lab.llvm.org:8011/builders/clang-x64-windows-msvc/builds/13870
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 | llvm/utils/TableGen/InstrInfoEmitter.cpp |
 | llvm/utils/TableGen/SequenceToOffsetTable.h |
 | llvm/cmake/modules/TableGen.cmake |
 | llvm/utils/TableGen/RegisterInfoEmitter.cpp |
 | llvm/utils/TableGen/TableGen.cpp |
 | llvm/utils/TableGen/AsmWriterEmitter.cpp |
Commit
cc4b716a379fab76dca734716730767d7de8d557
by kparzysz[Hexagon] Remove unused operand definitions: s10_0Imm and s10_6Imm
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 | llvm/lib/Target/Hexagon/HexagonDepDecoders.inc |
 | llvm/lib/Target/Hexagon/HexagonDepOperands.td |
Commit
398175e5c718ab2a92eded571f669f3b6e036e75
by michael.hliaoFix GCC warning/error '-fpermission'. NFC.
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 | llvm/lib/DWARFLinker/DWARFLinker.cpp |
 | llvm/include/llvm/DWARFLinker/DWARFLinker.h |
Commit
49f7bc9e1e50eb8f6e065f97585b3bf0bcc23d5c
by michael.hliao[hip] Remove `-Werror=format-nonliteral` Summary: - It won't distinguish host and device code and trigger compilation failure on irrelevant code. Reviewers: sameerds, yaxunl Subscribers: cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D73224
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 | clang/test/Driver/hip-printf.hip |
 | clang/lib/Driver/ToolChains/HIP.cpp |
Commit
f3c508fe91606c7383c812838b07ed5433a00dcf
by a.bataev[OPENMP]Fix use of local allocators in allocate clauses. If local allocator was declared and used in the allocate clause, it was not captured in inner region. It leads to a compiler crash, need to capture the allocator declarator.
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 | clang/lib/Sema/SemaOpenMP.cpp |
 | clang/test/OpenMP/parallel_master_codegen.cpp |
 | clang/test/OpenMP/teams_distribute_ast_print.cpp |
Commit
ad24cf2a942068e5bcdda3fbe58c084715266cf3
by kkwli0[OpenMP] change omp_atk_* and omp_atv_* enumerators to lowercase [NFC] The OpenMP spec defines the OMP_ATK_* and OMP_ATV_* to be lowercase. Differential Revision: https://reviews.llvm.org/D73248
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 | openmp/runtime/src/kmp.h |
 | openmp/runtime/test/api/omp_alloc_null_fb.c |
 | openmp/runtime/test/api/omp_alloc_def_fb.c |
 | openmp/runtime/test/api/omp_alloc_hbw.c |
 | openmp/runtime/src/include/omp.h.var |
 | openmp/runtime/src/kmp_alloc.cpp |
Commit
c1cac20827684949d381ae418f1868a76eaeda67
by llvm-dev[X86][AVX] Add AVX1/AVX2 ashr vector tests
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 | llvm/test/CodeGen/X86/sar_fold64.ll |
Commit
fc5bbbf328bc2ef582cf1cf9ba5ac2ddfc12ea31
by llvm-dev[SelectionDAG] ComputeNumSignBits - add ISD::SUB demanded elts support
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 | llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp |
 | llvm/test/CodeGen/X86/sar_fold64.ll |
Commit
0c943c611774b6785bc9a245bf432ae75357358c
by sam.parker[NFC][ARM] Add test
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 | llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir |
Commit
dfec702290e4cbd2fb965096788225ef3aac0986
by arsenm2AMDGPU: Check for other uses when looking through casted select Fixes mesa regression on ext_transform_feedback-max-varyings
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 | llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp |
 | llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll |
Commit
59f95222d4c5e997342b0514984823a99a16d44b
by gchatelet[Alignment][NFC] Use Align with CreateAlignedStore Summary: This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet, bollu Subscribers: arsenm, jvesely, nhaehnle, hiraditya, kerbowa, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D73274
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 | clang/lib/CodeGen/CGObjCGNU.cpp |
 | llvm/lib/Transforms/IPO/LowerTypeTests.cpp |
 | polly/lib/CodeGen/RuntimeDebugBuilder.cpp |
 | llvm/lib/CodeGen/ScalarizeMaskedMemIntrin.cpp |
 | llvm/lib/Target/X86/X86InterleavedAccess.cpp |
 | llvm/lib/Transforms/Scalar/SROA.cpp |
 | llvm/lib/Transforms/Vectorize/LoopVectorize.cpp |
 | clang/lib/CodeGen/CGBuilder.h |
 | llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp |
 | llvm/lib/Transforms/Scalar/Scalarizer.cpp |
 | llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp |
 | llvm/include/llvm/IR/DataLayout.h |
 | llvm/lib/Target/AMDGPU/AMDGPURewriteOutArguments.cpp |
 | llvm/include/llvm/IR/GlobalObject.h |
 | llvm/include/llvm/IR/IRBuilder.h |
 | llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp |
 | polly/lib/CodeGen/LoopGeneratorsKMP.cpp |
 | llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp |
 | llvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp |
 | clang/lib/CodeGen/TargetInfo.cpp |
 | llvm/lib/CodeGen/CodeGenPrepare.cpp |
 | llvm/lib/IR/DataLayout.cpp |
 | polly/lib/CodeGen/BlockGenerators.cpp |
 | clang/lib/CodeGen/CGGPUBuiltin.cpp |
 | llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp |
 | llvm/lib/IR/AutoUpgrade.cpp |
 | clang/lib/CodeGen/CGBuiltin.cpp |
 | clang/lib/CodeGen/CGBlocks.cpp |
Commit
d1de6dc17cdd37f84e92da5a456099eab0cc1467
by llvm-dev[X86][SSE] Add ComputeNumSignBits tests for (ADD (AND X, 1), -1) vectors
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 | llvm/test/CodeGen/X86/sar_fold64.ll |
Commit
0fec8acdd82a69fc5419b4a9db3c92a86634729d
by llvm-dev[SelectionDAG] ComputeNumSignBits - add ISD::ADD vector support Add missing handling for (ADD (AND X, 1), -1) uniform vectors
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 | llvm/test/CodeGen/X86/sar_fold64.ll |
 | llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp |
Commit
e256a775ebfcda5fd5f4d05fe40f6bb029e88f29
by hansclang-cl: Parse /QIntel-jcc-erratum It appears to be a new flag, see https://github.com/MicrosoftDocs/cpp-docs/commit/c7ac1c2635a631c61d3bed9f12b31dee6d6716fe
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 | clang/test/Driver/cl-options.c |
 | clang/include/clang/Driver/CLCompatOptions.td |
Commit
4faf71a14338420afc09eec261d5295439ae956a
by arsenm2GlobalISel: Use Register
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 | llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h |
Commit
618fa77ae4dd8244e468fce0bf144fa329f41e5b
by arsenm2AMDGPU/GlobalISel: Select V_ADD3_U32/V_XOR3_B32 The other 3-op patterns should also be theoretically handled, but currently there's a bug in the inferred pattern complexity. I'm not sure what the error handling strategy should be for potential constant bus violations. I think the correct strategy is to never produce mixed SGPR and VGPR operands in a typical VOP instruction, which will trivially avoid them. However, it's possible to still have hand written MIR (or erroneously transformed code) with these operands. When these fold, the restriction will be violated. We currently don't have any verifiers for reg bank legality. For now, just ignore the restriction. It might be worth triggering a DAG fallback on verifier error.
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 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-add3.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-or3.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.private.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.xfail.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.shared.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir |
 | llvm/lib/Target/AMDGPU/VOP3Instructions.td |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll |
Commit
05532575e88a45774dcf470d4639a01a4e501f66
by sam.parker[RDA] Skip debug values Skip debug instructions when iterating through a block to find uses. Differential Revision: https://reviews.llvm.org/D73273
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 | llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix-debug.mir |
 | llvm/lib/CodeGen/ReachingDefAnalysis.cpp |