Changes

[LLD] [COFF] Silence a GCC warning about an unused variable. NFC.

[SelectionDAG] Compute Known + Sign Bits - merge INSERT_SUBVECTOR
known/unknown index paths
Match the approach in SimplifyDemandedBits where we calculate the
demanded elts and then have a common path for the
ComputeKnownBits/ComputeNumSignBits call, additionally we only ever need
original demanded elts of the base vector even if the index is unknown.

[SelectionDAG] ComputeKnownBits - merge EXTRACT_VECTOR_ELT known/unknown
index paths
Match the approach in SimplifyDemandedBits/ComputeNumSignBits where we
calculate the demanded elts and then have a common path for the
ComputeKnownBits call.

[FileCheck] Strengthen error checks in unit tests
Summary: This commit adds error checking beyond UndefVarError and fix a
number of Error/Expected related idioms:
- use (EXPECT|ASSERT)_THAT_(ERROR|EXPECTED) instead of errorToBool or
 boolean operator
- ASSERT when a further check require the check to be successful to give
 a correct result
Reviewers: jhenderson, jdenny, probinson, grimar, arichardson, rnk
Reviewed By: jhenderson
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72914

[llvm-exegesis] Don't use unsupported aliasing instructions
Since some instruction types aren't allowed as the main instruction also 
don't allow them for aliasing instructions.
Differential Revision: https://reviews.llvm.org/D73220

[ARM,MVE] Revise immediate VBIC/VORR to look more like NEON.
Summary: In NEON, the immediate forms of VBIC and VORR are each
represented as a single MC instruction, which takes its immediate
operand already encoded in a NEON-friendly format: 8 data bits, plus
some control bits indicating how to expand them into a full vector.
In MVE, we represented immediate VBIC and VORR as four separate MC 
instructions each, for an 8-bit immediate shifted left by 0, 8, 16 or 24
bits. For each one, the value of the immediate operand is in the
'natural' form, i.e. the numerical value that would actually be BICed or
ORRed into each vector lane (and also the same value shown in assembly).
For example, MVE_VBICIZ16v4i32 takes an operand such as 0xab0000, which
NEON would represent as 0xab | (control bits << 8).
The MVE approach is superficially nice (it makes assembly input and 
output easy, and it's also nice if you're manually constructing 
immediate VBICs). But it turns out that it's better for isel if we make
the NEON and MVE instructions work the same, because the ARMISD::VBICIMM
and VORRIMM node types already encode their immediate into the NEON
format, so it's easier if we can just use it.
Also, this commit reduces the total amount of code rather than 
increasing it, which is surely an indication that it really is simpler 
to do it this way!
Reviewers: dmgreen, ostannard, miyuki, MarkMurrayARM
Reviewed By: dmgreen
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73205

[ARM,MVE] Support immediate vbicq,vorrq,vmvnq intrinsics.
Summary: Immediate vmvnq is code-generated as a simple vector constant
in IR, and left to the backend to recognize that it can be created with
an MVE VMVN instruction. The predicated version is represented as a 
select between the input and the same constant, and I've added a 
Tablegen isel rule to turn that into a predicated VMVN. (That should be
better than the previous VMVN + VPSEL: it's the same number of 
instructions but now it can fold into an adjacent VPT block.)
The unpredicated forms of VBIC and VORR are done by enabling the same 
isel lowering as for NEON, recognizing appropriate immediates and 
rewriting them as ARMISD::VBICIMM / ARMISD::VORRIMM SDNodes, which I 
then instruction-select into the right MVE instructions (now that I've 
also reworked those instructions to use the same MC operand encoding). 
In order to do that, I had to promote the Tablegen SDNode instance
`NEONvorrImm` to a general `ARMvorrImm` available in MVE as well, and 
similarly for `NEONvbicImm`.
The predicated forms of VBIC and VORR are represented as a vector select
between the original input vector and the output of the unpredicated
operation. The main convenience of this is that it still lets me use the
existing isel lowering for VBICIMM/VORRIMM, and not have to write
another copy of the operand encoding translation code.
This intrinsic family is the first to use the `imm_simd` system I put 
into the MveEmitter tablegen backend. So, naturally, it showed up a bug
or two (emitting bogus range checks and the like). Fixed those, and
added a full set of tests for the permissible immediates in the existing
Sema test.
Also adjusted the isel pattern for `vmovlb.u8`, which stopped matching 
because lowering started turning its input into a VBICIMM. Now it 
recognizes the VBICIMM instead.
Reviewers: dmgreen, MarkMurrayARM, miyuki, ostannard
Reviewed By: dmgreen
Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D72934

[AArch64][SVE] Add first-faulting load intrinsic
Summary: Implements the llvm.aarch64.sve.ldff1 intrinsic and DAG combine
rules for first-faulting loads with sign & zero extends
Reviewers: sdesmalen, efriedma, andwar, dancgr, rengolin
Reviewed By: sdesmalen
Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl,
cameron.mcinally, cfe-commits, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73025

Treat C# `using` as a control statement
Contributed by jbcoe!
Summary: Unless SpaceBeforeParensOptions is set to SBPO_Never, a space
will be put between `using` and `(` in C# code.
Reviewers: klimek, MyDeveloperDay, krasimir
Reviewed By: krasimir
Subscribers: MyDeveloperDay, cfe-commits
Tags: #clang-format, #clang
Differential Revision: https://reviews.llvm.org/D72144

[Alignement][NFC] Deprecate untyped CreateAlignedLoad
Summary: This is patch is part of a series to introduce an Alignment
type. See this thread for context:
http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this
patch for the introduction of the type: https://reviews.llvm.org/D64790
Reviewers: courbet
Subscribers: arsenm, jvesely, nhaehnle, hiraditya, kerbowa, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73260

[LoopRotate] add ability to repeat loop rotation until non-deoptimizing
exit is found
In case of loops with multiple exit where all-but-one exit are
deoptimizing it might happen that the first rotation will end up with
latch having a deoptimizing exit. This makes the loop unsuitable for
trip-count analysis (say, getLoopEstimatedTripCount) as well as for loop
transformations that know how to handle multple deoptimizing exits.
It pretty much means that canonical form in multple-deoptimizing-exits
case should be with non-deoptimizing exit at latch. Teach loop-rotation
to reach this canonical form by repeating rotation.
-loop-rotate-multi option introduced to control this behavior, currently
disabled by default.
Reviewers: skatkov, asbirlea, reames, fhahn Reviewed By: skatkov
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73058

[SelectionDAG] Compute Known + Sign Bits - merge INSERT_VECTOR_ELT
known/unknown index paths
Match the approach in SimplifyDemandedBits where we calculate the
demanded elts and then have a common path for the
ComputeKnownBits/ComputeNumSignBits call.

[NFC][RDA] Make the interface const
Make all the public query methods const.

[gn build] Port 2f6987ba61c

[CodeGen] Make use of MachineInstrBuilder::getReg
Reviewers: arsenm
Subscribers: wdng, hiraditya, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73262

Revert "[mlir] Add baseAttr to TypedArrayAttrBase."
This reverts commit eec36909c18b8788773abc95d199e6acde6eb42c.
This modeling is incorrect. baseAttr is intended for attribute 
decorators that are not backed by C++ attribute classes. It essentially 
says DerivedAttr isa BaseAttr, which is wrong for ArrayAttr classes. If
one needs to store the element type, it should be stored as a separate
filed in the tablegen class.

[tablegen] Emit string literals instead of char arrays
This changes the generated (Instr|Asm|Reg|Regclass)Name tables from this 
form:
   extern const char HexagonInstrNameData[] = {
     /* 0 */ 'G', '_', 'F', 'L', 'O', 'G', '1', '0', 0,
     /* 9 */ 'E', 'N', 'D', 'L', 'O', 'O', 'P', '0', 0,
     /* 18 */ 'V', '6', '_', 'v', 'd', 'd', '0', 0,
     /* 26 */ 'P', 'S', '_', 'v', 'd', 'd', '0', 0,
     [...]
   };
...to this:
    extern const char HexagonInstrNameData[] = {
     /* 0 */ "G_FLOG10\0"
     /* 9 */ "ENDLOOP0\0"
     /* 18 */ "V6_vdd0\0"
     /* 26 */ "PS_vdd0\0"
     [...]
   };
This should make debugging and exploration a lot easier for mortals, 
while providing a significant compile-time reduction for common
compilers.
To avoid issues with low implementation limits, this is disabled by 
default for visual studio or when cross-compiling.
To force output one way or the other, pass
`--long-string-literals=<bool>` to `tablegen`
Reviewers: mstorsjo, rnk
Subscribers: llvm-commit
Differential Revision: https://reviews.llvm.org/D73044

[ARM,MVE] Make the MVE intrinsics work in C++!
Summary: Apparently nobody has tried this in months of development. It
turns out that `FunctionDecl::getBuiltinID` will never consider a
function to be a builtin if it is in C++ and not extern "C". So none of
the function declarations in <arm_mve.h> are recognized as builtins when 
clang is compiling in C++ mode: it just emits calls to them as ordinary
functions, which then turn out not to exist at link time.
The trivial fix is to wrap most of arm_mve.h in an extern "C".
Added a test in clang/test/CodeGen/arm-mve-intrinsics which checks basic
functioning of the MVE header file in C++ mode. I've filled it with
copies of existing test functions from other files in that directory,
including a few moderately tricky cases of overloading (in particular
one that relies on the strict-polymorphism attribute added in D72518).
(I considered making //every// test in that directory compile in both C
and C++ mode and check the code generation was identical. But I think
that would increase testing time by more than the value it adds, and
also update_cc_test_checks gets confused when the output function name
varies between RUN lines.)
Reviewers: LukeGeeson, MarkMurrayARM, miyuki, dmgreen
Reviewed By: MarkMurrayARM
Subscribers: kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D73268

[VE][NFC] re-write RR* isel class using null_frag
Summary: Re-write RR* using null_frag to avoid duplication in upcoming
patches.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D73259

[clang][CodeComplete] Make completion work after initializer lists
Summary: CodeCompletion was not being triggered after successfully
parsed initializer lists, e.g.
```cpp void foo(int, bool); void bar() {
 foo({1}^, false);
}
```
CodeCompletion would suggest the function foo as an overload candidate
up until the point marked with `^` but after that point we do not
trigger signature help since parsing succeeds.
This patch handles that case by failing in parsing expression lists
whenever we see a codecompletion token, in addition to getting an
invalid subexpression.
Reviewers: sammccall
Subscribers: cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D73177

Revert "Resubmit: [JumpThreading] Thread jumps through two basic blocks"
This reverts commit 53b68e676faf208b4a8f817e9bd4ddd522cc6006.
Our internal tests are showing breakage with this patch.

[VE] add, sub, left/right shift isel patterns
Summary: Add, sub, left/right shift isel patterns and tests for i32/i64
and fp32/fp64.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D73207

[Dsymutil][Debuginfo][NFC] #4 Refactor dsymutil to separate DWARF
optimizing part.
Summary: The primary goal of this refactoring is to separate DWARF
optimizing part. So that it could be reused by linker or by any other
client. There was a thread on llvm-dev discussing the necessity of such
a refactoring:
http://lists.llvm.org/pipermail/llvm-dev/2019-September/135068.html.
This is a final part from series of patches for dsymutil. Previous
patches : D71068, D71839, D72476. This patch:
1. Creates lib/DWARFLinker interface :
   void addObjectFile(DwarfLinkerObjFile &ObjFile);
  bool link();
  void setOptions;
1. Moves all linking logic from tools/dsymutil/DwarfLinkerForBinary
  into lib/DWARFLinker. 2. Renames RelocationManager into
AddressesManager. 3. Remarks creation logic moved from separate parallel
execution
  into object file loading routine.
Testing: it passes "check-all" lit testing. MD5 checksum for clang .dSYM
bundle matches for the dsymutil with/without that patch.
Reviewers: JDevlieghere, friss, dblaikie, aprantl, jdoerfert
Reviewed By: JDevlieghere
Subscribers: merge_guards_bot, hiraditya, jfb, llvm-commits, probinson,
thegameg
Tags: #llvm, #debug-info
Differential Revision: https://reviews.llvm.org/D72915

Revert "[tablegen] Emit string literals instead of char arrays"
This reverts commit ce23515f5ab01161c98449d833b3ae013b553aa8.
That commit broke some builds on Windows: 
http://lab.llvm.org:8011/builders/clang-x64-windows-msvc/builds/13870

[Hexagon] Remove unused operand definitions: s10_0Imm and s10_6Imm

Fix GCC warning/error '-fpermission'. NFC.

[hip] Remove `-Werror=format-nonliteral`
Summary:
- It won't distinguish host and device code and trigger compilation
 failure on irrelevant code.
Reviewers: sameerds, yaxunl
Subscribers: cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D73224

[OPENMP]Fix use of local allocators in allocate clauses.
If local allocator was declared and used in the allocate clause, it was 
not captured in inner region. It leads to a compiler crash, need to 
capture the allocator declarator.

[OpenMP] change omp_atk_* and omp_atv_* enumerators to lowercase [NFC]
The OpenMP spec defines the OMP_ATK_* and OMP_ATV_* to be lowercase.
Differential Revision: https://reviews.llvm.org/D73248

[X86][AVX] Add AVX1/AVX2 ashr vector tests

[SelectionDAG] ComputeNumSignBits - add ISD::SUB demanded elts support

[NFC][ARM] Add test

AMDGPU: Check for other uses when looking through casted select
Fixes mesa regression on ext_transform_feedback-max-varyings

[Alignment][NFC] Use Align with CreateAlignedStore
Summary: This is patch is part of a series to introduce an Alignment
type. See this thread for context:
http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this
patch for the introduction of the type: https://reviews.llvm.org/D64790
Reviewers: courbet, bollu
Subscribers: arsenm, jvesely, nhaehnle, hiraditya, kerbowa, cfe-commits,
llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D73274

[X86][SSE] Add ComputeNumSignBits tests for (ADD (AND X, 1), -1) vectors

[SelectionDAG] ComputeNumSignBits - add ISD::ADD vector support
Add missing handling for (ADD (AND X, 1), -1) uniform vectors

clang-cl: Parse /QIntel-jcc-erratum
It appears to be a new flag, see 
https://github.com/MicrosoftDocs/cpp-docs/commit/c7ac1c2635a631c61d3bed9f12b31dee6d6716fe

GlobalISel: Use Register

AMDGPU/GlobalISel: Select V_ADD3_U32/V_XOR3_B32
The other 3-op patterns should also be theoretically handled, but 
currently there's a bug in the inferred pattern complexity.
I'm not sure what the error handling strategy should be for potential 
constant bus violations. I think the correct strategy is to never 
produce mixed SGPR and VGPR operands in a typical VOP instruction, which
will trivially avoid them. However, it's possible to still have hand
written MIR (or erroneously transformed code) with these operands. When
these fold, the restriction will be violated. We currently don't have
any verifiers for reg bank legality. For now, just ignore the
restriction.
It might be worth triggering a DAG fallback on verifier error.

[RDA] Skip debug values
Skip debug instructions when iterating through a block to find uses.
Differential Revision: https://reviews.llvm.org/D73273