FailedChanges

Summary

  1. [lldb][NFC] Give some parameters in CommandInterpreter more descriptive (details)
  2. [AArch64] Update test checks on merge-store-dependency.ll. NFC (details)
  3. Recommit "[HardwareLoops] Optimisation remarks" (details)
  4. [mips] Fix `__mips_isa_rev` macros value for Octeon CPU (details)
  5. [mips] Set __OCTEON__ macros (details)
  6. DWARFDebugLoclists: Make it possible to read relocated addresses (details)
  7. [RISCV] Add InstrInfo areMemAccessesTriviallyDisjoint hook (details)
  8. [InstCombine] dropRedundantMaskingOfLeftShiftInput(): truncation (details)
  9. [LoopUnroll] peel-loop-conditions.ll: add some 'is even/odd' peeling (details)
  10. MemoryRegion: Print "don't know" permission values as such (details)
  11. lldb/minidump: Add support for the alternate ARM64 constant (details)
  12. [OpenCL] Add builtin function attribute handling (details)
  13. [OpenCL] Group builtin functions by prototype (details)
  14. Revert and patch "[Python] Remove readline module" (details)
  15. lldb/breakpad: add suppport for the "x86_64h" architecture (details)
  16. [Scheduling][ARM] Consistently enable PostRA Machine scheduling (details)
  17. [ARM] Always enable UseAA in the arm backend (details)
  18. Fix PR40644: miscompile indexed FP constant store (details)
  19. [Clang FE]  Recognize -mnop-mcount CL option (SystemZ only). (details)
Commit db5074dc10222a8202adcd7c1da1acd2828fbecb by Raphael Isemann
[lldb][NFC] Give some parameters in CommandInterpreter more descriptive
names
The file was modifiedlldb/source/Interpreter/CommandInterpreter.cpp
The file was modifiedlldb/include/lldb/Interpreter/CommandInterpreter.h
Commit edfb8eea575582f5a4f485368d84b7c5e9853780 by david.green
[AArch64] Update test checks on merge-store-dependency.ll. NFC
The file was modifiedllvm/test/CodeGen/AArch64/merge-store-dependency.ll
Commit 92164cf25d513d44fdb5d727a33d02ad4c87384e by sjoerd.meijer
Recommit "[HardwareLoops] Optimisation remarks"
With a few things fixed:
- initialisaiton of the optimisation remark pass (this was causing the
buildbot
failures on PPC),
- a test case.
Differential Revision: https://reviews.llvm.org/D69660
The file was modifiedllvm/test/CodeGen/ARM/O3-pipeline.ll
The file was modifiedllvm/lib/CodeGen/HardwareLoops.cpp
The file was modifiedllvm/test/Transforms/HardwareLoops/ARM/structure.ll
Commit e578d0fd295a67bce1e1fc922237f459deb49c7e by simon
[mips] Fix `__mips_isa_rev` macros value for Octeon CPU
The file was modifiedclang/test/Preprocessor/init.c
The file was modifiedclang/lib/Basic/Targets/Mips.cpp
Commit 0d14656b9d8ca38b8ea321c7047eaeec43c5b2ef by simon
[mips] Set __OCTEON__ macros
The file was modifiedclang/test/Preprocessor/init.c
The file was modifiedclang/lib/Basic/Targets/Mips.cpp
Commit b4c5b8f3f51206bac2282a8b483e76ad59a5aed5 by pavel
DWARFDebugLoclists: Make it possible to read relocated addresses
Summary: Handling relocations was not needed when the loclists section
was a DWO-only thing. But since DWARF5, it is possible to use it in
regular objects too, and the standard permits embedding addresses into
the section directly. These addresses need to be relocated in unlinked
files.
Reviewers: JDevlieghere, dblaikie, probinson
Subscribers: aprantl, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68271
The file was modifiedllvm/lib/DebugInfo/DWARF/DWARFDie.cpp
The file was modifiedllvm/lib/DebugInfo/DWARF/DWARFContext.cpp
The file was addedllvm/test/tools/llvm-dwarfdump/X86/debug_loclists.s
The file was modifiedllvm/include/llvm/DebugInfo/DWARF/DWARFDebugLoc.h
The file was modifiedllvm/lib/DebugInfo/DWARF/DWARFDebugLoc.cpp
Commit 0d47c7aba364962d14e4e25249d75da7bdf29b78 by luismarques
[RISCV] Add InstrInfo areMemAccessesTriviallyDisjoint hook
Summary: Introduces the `InstrInfo::areMemAccessesTriviallyDisjoint`
hook. The test could check for instruction reorderings, but to avoid
being brittle it just checks instruction dependencies.
Reviewers: asb, lenary Reviewed By: lenary Tags: #llvm Differential
Revision: https://reviews.llvm.org/D67046
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.h
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.cpp
The file was addedllvm/test/CodeGen/RISCV/disjoint.ll
Commit ccf1a5f4bbe680f20e26c29774d62bec6cb226da by lebedev.ri
[InstCombine] dropRedundantMaskingOfLeftShiftInput(): truncation
(PR42563)
Summary: That fold keeps growing and growing :( I think this may be one
of the last pieces for it.
Since D67677/D67725, the fold knowns the general form of the pattern -
where some masking is needed: https://rise4fun.com/Alive/F5R
https://rise4fun.com/Alive/gslRa
But there is one more huge piece missing - if you are extracting some
bits, it is not impossible that the origin is wider than the extraction,
i.e. there may be a truncation. And we don't deal with that yet.
But we can, and the generalization remains fully identical:
https://rise4fun.com/Alive/Uar https://rise4fun.com/Alive/5SW
After a preparatory cleanup i think the diff looks rather clean.
One missing piece is that in some patterns (especially pat. b),
`-1` only needs to be `-1` in final type, but that is for later..
https://bugs.llvm.org/show_bug.cgi?id=42563
Reviewers: spatel, nikic
Reviewed By: spatel
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69125
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
The file was modifiedllvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-after-truncation-variant-a.ll
The file was modifiedllvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-after-truncation-variant-e.ll
The file was modifiedllvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-a.ll
The file was modifiedllvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-b.ll
The file was modifiedllvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-after-truncation-variant-d.ll
The file was modifiedllvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-e.ll
The file was modifiedllvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-after-truncation-variant-f.ll
The file was modifiedllvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-after-truncation-variant-c.ll
The file was modifiedllvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-c.ll
The file was modifiedllvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-after-truncation-variant-b.ll
The file was modifiedllvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-d.ll
Commit 12c4a71ca9dc19dc364cd6ad4cfc2a3787141c24 by lebedev.ri
[LoopUnroll] peel-loop-conditions.ll: add some 'is even/odd' peeling
tests
The file was modifiedllvm/test/Transforms/LoopUnroll/peel-loop-conditions.ll
Commit 28cf9698abd39221001ace885a7d1c1f488b967c by pavel
MemoryRegion: Print "don't know" permission values as such
Summary: The permissions in a memory region have ternary states (yes,
no, don't know), but the memory region command only prints in binary,
treating
"don't know" as "yes", which is particularly confusing as for instance
the unwinder will treat an unknown value as "no".
This patch makes is so that we distinguish all three states when
printing the values, using "?" to indicate the lack of information. It
is implemented via a special argument to the format provider for the
OptionalBool enumeration.
Reviewers: clayborg, jingham
Subscribers: lldb-commits
Differential Revision: https://reviews.llvm.org/D69106
The file was modifiedlldb/test/Shell/Minidump/memory-region-from-module.yaml
The file was modifiedlldb/source/Target/MemoryRegionInfo.cpp
The file was modifiedlldb/include/lldb/Target/MemoryRegionInfo.h
The file was modifiedlldb/source/Commands/CommandObjectMemory.cpp
Commit 4ecff91ed1df05edbdb55cb2ccdf58466f1333b0 by pavel
lldb/minidump: Add support for the alternate ARM64 constant
The file was modifiedlldb/packages/Python/lldbsuite/test/functionalities/postmortem/minidump-new/regions-linux-map.yaml
The file was modifiedlldb/source/Plugins/Process/minidump/MinidumpParser.cpp
Commit 9a8d477a0e00c15d6d33a52486fa931483b7f2ea by sven.vanhaastregt
[OpenCL] Add builtin function attribute handling
Add handling for the "pure", "const" and "convergent" function
attributes for OpenCL builtin functions.
Patch by Pierre Gondois and Sven van Haastregt.
Differential Revision: https://reviews.llvm.org/D64319
The file was modifiedclang/utils/TableGen/ClangOpenCLBuiltinEmitter.cpp
The file was addedclang/test/CodeGenOpenCL/fdeclare-opencl-builtins.cl
The file was modifiedclang/lib/Sema/SemaLookup.cpp
The file was modifiedclang/lib/Sema/OpenCLBuiltins.td
Commit 0e56b0f94bfc683c5a95e96784cfc9229a730bc8 by sven.vanhaastregt
[OpenCL] Group builtin functions by prototype
The TableGen-generated file containing the function definitions can be
reorganized to save some memory in the Clang binary.  Functions having
the same prototype(s) will point to a shared list of prototype(s).
Patch by Pierre Gondois and Sven van Haastregt.
Differential Revision: https://reviews.llvm.org/D63557
The file was modifiedclang/utils/TableGen/ClangOpenCLBuiltinEmitter.cpp
Commit 9357b5d08497326a1895cab6c1d712bf12a34519 by sguelton
Revert and patch "[Python] Remove readline module"
Fix https://bugs.llvm.org/show_bug.cgi?id=43830 while avoiding polluting
the global Python namespace.
This both reverts r357277 to rebundle a version of Python's readline
module based on libedit.
However, this patch also provides two improvements over the previous
implementation:
1. use PyMem_RawMalloc instead of PyMem_Malloc, as expected by
PyOS_Readline
  (prevents to segfault upon exit of interactive session) 2. patch the
readline module upon embedded interpreter loading, instead of
  patching it globally, which should prevent any side effect on other
  modules/packages 3. only activate the patched module if libedit is
actually linked in lldb
Differential Revision: https://reviews.llvm.org/D69793
The file was modifiedlldb/source/Plugins/ScriptInterpreter/Python/CMakeLists.txt
The file was addedlldb/source/Plugins/ScriptInterpreter/Python/PythonReadline.cpp
The file was modifiedlldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
The file was addedlldb/source/Plugins/ScriptInterpreter/Python/PythonReadline.h
Commit f71e35dc1f3ea9b368b1d4626ee9bf7993839084 by pavel
lldb/breakpad: add suppport for the "x86_64h" architecture
The file was modifiedlldb/test/Shell/SymbolFile/Breakpad/Inputs/line-table-edgecases.syms
The file was modifiedlldb/source/Plugins/ObjectFile/Breakpad/BreakpadRecords.cpp
Commit 7d9af03ff7a0d4fb6ae3ec224a0d8d7398bdbd84 by david.green
[Scheduling][ARM] Consistently enable PostRA Machine scheduling
In the ARM backend, for historical reasons we have only some targets
using Machine Scheduling. The rest use the old list scheduler as they
are using itinaries and the list scheduler seems to produce better code
(and not crash running out of register on v6m codes). So whether to use
the MIScheduler or not is checked at runtime from the subtarget
features.
This is fine, except for post-ra scheduling. Whether to use the old
post-ra list scheduler or the post-ra machine schedule is decided as the
pass manager is set up, in arms case from a newly constructed subtarget.
Under some situations, like LTO, this won't include the correct cpu so
can pick the wrong option. This can have a surprising effect on
performance.
To fix that, this patch overrides targetSchedulesPostRAScheduling and
addPreSched2 in the ARM backend, adding _both_ post-ra schedulers and
picking at runtime which to execute. To pick between the two I've had to
add a enablePostRAMachineScheduler() method that normally returns
enableMachineScheduler() && enablePostRAScheduler(), which can be
overridden to enable just one of PostRAMachineScheduler vs
PostRAScheduler.
Thanks to David Penry for the identifying this problem.
Differential Revision: https://reviews.llvm.org/D69775
The file was modifiedllvm/test/CodeGen/ARM/cortex-a57-misched-vstm-wrback.ll
The file was modifiedllvm/lib/Target/ARM/ARMTargetMachine.cpp
The file was modifiedllvm/lib/CodeGen/MachineScheduler.cpp
The file was modifiedllvm/test/CodeGen/ARM/cortex-a57-misched-stm.ll
The file was modifiedllvm/lib/Target/ARM/ARMSubtarget.h
The file was modifiedllvm/test/CodeGen/ARM/cortex-a57-misched-ldm.ll
The file was modifiedllvm/test/CodeGen/ARM/cortex-a57-misched-vldm.ll
The file was modifiedllvm/include/llvm/CodeGen/TargetSubtargetInfo.h
The file was modifiedllvm/test/CodeGen/ARM/cortex-a57-misched-vstm.ll
The file was modifiedllvm/lib/Target/ARM/ARMSubtarget.cpp
The file was modifiedllvm/test/CodeGen/ARM/O3-pipeline.ll
The file was modifiedllvm/test/CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll
The file was modifiedllvm/test/CodeGen/ARM/cortex-a57-misched-vldm-wrback.ll
The file was modifiedllvm/lib/Target/ARM/ARMTargetMachine.h
The file was modifiedllvm/test/CodeGen/ARM/cortex-a57-misched-stm-wrback.ll
The file was modifiedllvm/lib/CodeGen/TargetSubtargetInfo.cpp
The file was addedllvm/test/CodeGen/ARM/postrasched.ll
Commit cf581d7977c5c80e9f6cb6e304d7eb3d0792f360 by david.green
[ARM] Always enable UseAA in the arm backend
This feature controls whether AA is used into the backend, and was
previously turned on for certain subtargets to help create less
constrained scheduling graphs. This patch turns it on for all
subtargets, so that they can all make use of the extra information to
produce better code.
Differential Revision: https://reviews.llvm.org/D69796
The file was modifiedllvm/test/CodeGen/ARM/useaa.ll
The file was modifiedllvm/lib/Target/ARM/ARMSubtarget.h
The file was modifiedllvm/test/CodeGen/ARM/va_arg.ll
The file was modifiedllvm/test/CodeGen/ARM/memcpy-ldm-stm.ll
The file was modifiedllvm/test/CodeGen/ARM/thumb1_return_sequence.ll
The file was modifiedllvm/lib/Target/ARM/ARM.td
Commit 646896a442249380f74ff404e6dd26687f3dc6d9 by thomasp
Fix PR40644: miscompile indexed FP constant store
Summary: Functions replaceStoreOfFPConstant() and OptimizeFloatStore()
both replace store of float by a store of an integer unconditionally.
However this generates wrong code when the store that is replaced is an
indexed or truncating store. This commit solves this issue by adding an
early return in these functions when the store being considered is not a
normal store.
Bug was only observed on out of tree targets, hence the lack of testcase
in this commit.
Reviewers: efriedma
Subscribers: hiraditya, arphaman, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68420
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit 93767143147b7d765c6ce8123a4226d449228649 by paulsson
[Clang FE]  Recognize -mnop-mcount CL option (SystemZ only).
Recognize -mnop-mcount from the command line and add a function
attribute
"mnop-mcount"="true" when passed.
When this option is used, a nop is added instead of a call to fentry.
This is used when building the Linux Kernel.
If this option is passed for any other target than SystemZ, an error is
generated.
Review: Ulrich Weigand https://reviews.llvm.org/D67763
The file was modifiedclang/include/clang/Basic/DiagnosticCommonKinds.td
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was addedclang/test/CodeGen/mnop-mcount.c
The file was modifiedclang/include/clang/Basic/CodeGenOptions.def
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/lib/CodeGen/CodeGenFunction.cpp
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp