SuccessChanges

Summary

  1. [VPlan] Keep start value of VPWidenPHIRecipe as VPValue. (details)
  2. [RISCV] Do not grow the stack a second time when we need to realign the stack (details)
  3. [OpenMP] Added the support for cache line size 256 for A64FX (details)
  4. [SelectionDAG] Extend immAll(Ones|Zeros)V to handle ISD::SPLAT_VECTOR (details)
Commit 65f578fc0e6fb10bb84f3dea906f8fb1230c1ab3 by flo
[VPlan] Keep start value of VPWidenPHIRecipe as VPValue.

Similar to D92129, update VPWidenPHIRecipe  to manage the start value as
VPValue. This allows adjusting the start value as a VPlan transform,
which will be used in a follow-up patch to support reductions during
epilogue vectorization.

Reviewed By: gilr

Differential Revision: https://reviews.llvm.org/D93975
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.h
Commit 524d8fa9a5a5428628a21a91016a52a54a9fe838 by roger.ferrer
[RISCV] Do not grow the stack a second time when we need to realign the stack

This is a first change needed to fix a crash in which the emergency
spill splot ends being out of reach. This happens when we run the
register scavenger after we have eliminated the frame indexes. The fix
for the actual crash will come in a later change.

This change removes an extra stack size increase we do in
RISCVFrameLowering::determineFrameLayout.

We don't have to change the size of the stack here as
PEI::calculateFrameObjectOffsets is already doing this with the right
size accounting the extra alignment.

Differential Revision: https://reviews.llvm.org/D89237
The file was modifiedllvm/lib/Target/RISCV/RISCVFrameLowering.cpp
The file was modifiedllvm/test/CodeGen/RISCV/stack-realignment-with-variable-sized-objects.ll
The file was modifiedllvm/test/CodeGen/RISCV/stack-realignment.ll
Commit 676c7cb0c0d4b66affde3ff7fc566c7a5aaa7246 by tianshilei1992
[OpenMP] Added the support for cache line size 256 for A64FX

Fugaku supercomputer is built with the Fujitsu A64FX microprocessor, whose cache line is 256. In current libomp, we only have cache line size 128 for PPC64 and otherwise 64. This patch added the support of cache line 256 for A64FX. It's worth noting that although A64FX is a variant of AArch64, this property is not shared. As a result, in light of UCX source code (https://github.com/openucx/ucx/blob/392443ab92626412605dee1572056f79c897c6c3/src/ucs/arch/aarch64/cpu.c#L17), we can only determine by checking whether the CPU is FUJITSU A64FX.

Reviewed By: jdoerfert, Hahnfeld

Differential Revision: https://reviews.llvm.org/D93169
The file was modifiedopenmp/runtime/cmake/LibompGetArchitecture.cmake
The file was modifiedopenmp/runtime/cmake/config-ix.cmake
The file was modifiedopenmp/runtime/CMakeLists.txt
The file was modifiedopenmp/runtime/src/kmp_config.h.cmake
The file was modifiedopenmp/runtime/cmake/LibompUtils.cmake
Commit de373ef779880e923636d90cdb277e4db84c7479 by fraser
[SelectionDAG] Extend immAll(Ones|Zeros)V to handle ISD::SPLAT_VECTOR

The TableGen immAllOnesV and immAllZerosV helpers implicitly wrapped the
ISD::isBuildVectorAll(Ones|Zeros) helper functions. This was inhibiting
their use for targets such as RISC-V which use ISD::SPLAT_VECTOR. In
particular, RISC-V had to define its own 'vnot' fragment.

In order to extend the scope of these nodes to include support for
ISD::SPLAT_VECTOR, two new ISD predicate functions have been introduced:
ISD::isConstantSplatVectorAll(Ones|Zeros). These effectively supersede
the older "isBuildVector" predicates, which are now simple wrappers for
the new functions. They pass a defaulted boolean toggle which preserves
the old behaviour. It is hoped that in time all call-sites can be ported
to the "isConstantSplatVector" functions.

While the use of ISD::isBuildVectorAll(Ones|Zeros) has not changed, the
behaviour of the TableGen immAll(Ones|Zeros)V **has**. To test the new
functionality, the custom RISC-V TableGen fragment has been removed and
replaced with the built-in 'vnot'. To test their use as pattern-roots, two
splat patterns have been updated accordingly.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D94223
The file was modifiedllvm/utils/TableGen/DAGISelMatcher.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
The file was modifiedllvm/include/llvm/CodeGen/SelectionDAGNodes.h
The file was modifiedllvm/utils/TableGen/DAGISelMatcherGen.cpp
The file was modifiedllvm/include/llvm/Target/TargetSelectionDAG.td
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp