FailedChanges

Summary

  1. IR: remove "else" after "return". NFCI. (details)
  2. [ARM,MVE] Fix valid immediate range for vsliq_n. (details)
  3. [ARM,MVE] Add missing IntrNoMem flag on IR intrinsics. (details)
  4. AMDGPU: Add register class to DS_SWIZZLE_B32 pattern (details)
  5. TableGen/GlobalISel: Fix slightly wrong generated comment (details)
  6. AMDGPU/GlobalISel: Fix add of neg inline constant pattern (details)
  7. AMDGPU/GlobalISel: Add equiv xform for bitcast_fpimm_to_i32 (details)
  8. AMDGPU/GlobalISel: Add selectVOP3Mods_nnan (details)
  9. AMDGPU/GlobalISel: Add IMMPopCount xform (details)
  10. AMDGPU/GlobalISel: Fix import of zext of s16 op patterns (details)
  11. AMDGPU: Use new PatFrag system for d16 load nodes (details)
  12. AMDGPU: Use new PatFrag system for d16 stores (details)
  13. AMDGPU: Eliminate more legacy codepred address space PatFrags (details)
  14. AMDGPU/GlobalISel: Fix import of integer med3 (details)
Commit 667e1f71b83c48b635b13b64bbff28b95e68265c by Tim Northover
IR: remove "else" after "return". NFCI.
The file was modifiedllvm/lib/IR/Core.cpp
Commit d857e114b5e04f5143485a5aea7ad9b283768692 by simon.tatham
[ARM,MVE] Fix valid immediate range for vsliq_n.
In common with most MVE immediate shift instructions, the left shift
takes an immediate in the range [0,n-1], while the right shift takes one
in the range [1,n]. I had absent-mindedly made them both the latter.
While I'm here, I've added a set of regression tests checking both ends
of the immediate range for a representative sample of the immediate
shifts.
The file was modifiedclang/include/clang/Basic/arm_mve.td
The file was modifiedclang/test/Sema/arm-mve-immediates.c
Commit 9704ba652a0062c53ec66b068766df5c0cd5c620 by simon.tatham
[ARM,MVE] Add missing IntrNoMem flag on IR intrinsics.
A lot of the IR-level intrinsics we've been defining for MVE recently
accidentally had `props = []` instead of `props = [IntrNoMem]`, so that
optimization would have been overcautious about reordering them.
All the affected cases were due to instantiating the multiclasses
`MVEPredicated` and `MVEMXPredicated` without filling in the `props`
parameter, because I //thought// I remembered having set the defaults in
those multiclasses to `[IntrNoMem]`. In fact I hadn't done that. Now I
have.
(The IR intrinsics that //do// read and write memory are all explicitly
marked as `[IntrReadMem]` or `[IntrWriteMem]` already, so they will
override these defaults.)
The file was modifiedllvm/include/llvm/IR/IntrinsicsARM.td
Commit db7c92077963195df0807e976cc916b5c6e29a05 by arsenm2
AMDGPU: Add register class to DS_SWIZZLE_B32 pattern
Reduces diff for a future patch.
The file was modifiedllvm/lib/Target/AMDGPU/DSInstructions.td
Commit 0274ed9dc75a0efb2b6130122226ee45f7e57dde by arsenm2
TableGen/GlobalISel: Fix slightly wrong generated comment
The file was modifiedllvm/test/TableGen/GlobalISelEmitter.td
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp
Commit 3952748ffdf017f83faddcb1240cb36cb4bb9c5b by arsenm2
AMDGPU/GlobalISel: Fix add of neg inline constant pattern
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUGISel.td
Commit d964086c62422771c1d6dbe66ee8ea06e8f834b2 by arsenm2
AMDGPU/GlobalISel: Add equiv xform for bitcast_fpimm_to_i32
Only partially fixes one pattern import.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUGISel.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
Commit 79450a4ea26a0e9731eaf2629f6dd8c1ffd8f407 by arsenm2
AMDGPU/GlobalISel: Add selectVOP3Mods_nnan
This doesn't enable any new imports yet, but moves the fmed patterns
from failing on this to hitting the "complex suboperand referenced more
than once" limitation in tablegen.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUGISel.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
Commit e71af775684a83f0d1d05ab5225d36830d5aa87e by arsenm2
AMDGPU/GlobalISel: Add IMMPopCount xform
Partially fixes BFE pattern import.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUGISel.td
Commit 7d677421607cbfdd8d1e96275c613d3db8a0e51f by arsenm2
AMDGPU/GlobalISel: Fix import of zext of s16 op patterns
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir
The file was modifiedllvm/lib/Target/AMDGPU/VOP2Instructions.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir
Commit c1d4963b447c9330c2ad50bb73bb93f9a42c9641 by arsenm2
AMDGPU: Use new PatFrag system for d16 load nodes
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.td
Commit 3766f4baccac5cc17680ad4cefd1d5a0d3ba2870 by arsenm2
AMDGPU: Use new PatFrag system for d16 stores
The file was modifiedllvm/lib/Target/AMDGPU/DSInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructions.td
Commit c66b2e1c87ecde72eb37d3452ec9c1b8766ede30 by arsenm2
AMDGPU: Eliminate more legacy codepred address space PatFrags
These should now be limited to R600 code.
The file was modifiedllvm/lib/Target/AMDGPU/FLATInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/BUFInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/R600Instructions.td
Commit 9ffd0ed838191247e0da7df5e28e54a5129e76a7 by arsenm2
AMDGPU/GlobalISel: Fix import of integer med3
This isn't too useful now, since nothing is currently trying to form
min/max from cmp+select.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructions.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.s16.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.s16.mir