Changes

Bump Android NDK version to r21.

Revert "Bump Android NDK version to r21."
This reverts commit 9822b13842a6f476f023ef282d329c276d165a7c.

Add test for spaceship operator to __config
Summary: The libcxx test suite auto-detects spaceship operator, but
__config does not. This means that the libcxx test suite has been broken
for over a month when using top-of-tree clang. This also really ought to
be fixed before 10.0.
See: bc633a42dd409dbeb456263e3388b8caa4680aa0
Reviewers: chandlerc, mclow.lists, EricWF, ldionne, CaseyCarter
Reviewed By: EricWF
Subscribers: broadwaylamb, hans, dexonsmith, tstellar, llvm-commits,
libcxx-commits
Tags: #libc, #llvm
Differential Revision: https://reviews.llvm.org/D72980

[DA] Don't propagate from unreachable blocks
Summary: Fixes crash that could occur when a divergent terminator has an
unreachable parent.
Reviewers: rampitec, nhaehnle, arsenm
Subscribers: jvesely, wdng, hiraditya, jfb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73323

Support Swift calling convention for WebAssembly targets
This adds basic support for the Swift calling convention with
WebAssembly targets.
Reviewed By: dschuff
Differential Revision: https://reviews.llvm.org/D71823

Resubmit: [DA][TTI][AMDGPU] Add option to select GPUDA with TTI
Summary: Enable the new diveregence analysis by default for AMDGPU.
Resubmit with test updates since GPUDA was causing failures on Windows.
Reviewers: rampitec, nhaehnle, arsenm, thakis
Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye,
hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73315

Allow combining of extract_subvector to extract element
Differential Revision: https://reviews.llvm.org/D73132

[AMDGPU] Allow narrowing muti-dword loads
Currently BE allows only a little load narrowing because of the fear it
will produce sub-dword ext loads. However, we can always allow narrowing
if we are shrinking one multi-dword load to another multi-dword load.
In particular we were unable to reduce s_load_dwordx8 into 
s_load_dwordx4 if identity shuffle was used to extract low 4 dwords.
Differential Revision: https://reviews.llvm.org/D73133

[PGO] Attach appropriate funclet operand bundles to value profiling
instrumentation calls
Patch by Chris Chrulski
When generating value profiling instrumentation, ensure the call gets
the correct funclet token, otherwise WinEHPrepare will turn the call
(and all subsequent instructions) into unreachable.
Differential Revision: https://reviews.llvm.org/D73221

[AMDGPU] Bundle loads before post-RA scheduler
We are relying on atrificial DAG edges inserted by the 
MemOpClusterMutation to keep loads and stores together in the post-RA
scheduler. This does not work all the time since it allows to schedule a
completely independent instruction in the middle of the cluster.
Removed the DAG mutation and added pass to bundle already clustered
instructions. These bundles are unpacked before the memory legalizer
because it does not work with bundles but also because it allows to
insert waitcounts in the middle of a store cluster.
Removing artificial edges also allows a more relaxed scheduling.
Differential Revision: https://reviews.llvm.org/D72737

Make address-space-lambda.cl pass on 32-bit Windows
Member functions will have the thiscall attribute on them.

[gn build] Port 555d8f4ef5e

Include <cstdlib> for std::abort() in clangd
This fixes a "not a member of 'std'" error with e.g. Fedora 32.
Closes: #105

[GlobalsAA] Add back a check to intrinsic_addresstaken.ll to see if the
AVX and AVX512 bots still fail for it.
These bots failed for this several months ago and as a result, this 
check was removed. If they still fail I'm going to try to see if I can
figure out why.

AMDGPU/GlobalISel: Add selection tests for G_ATOMICRMW_ADD

AMDGPU: Don't check constant address space for atomic stores
We define a separate list for storable address spaces. This saves entry
in the matcher table address space list.

TableGen: Work around assert on Mips register definitions
This would hit the "Biggest class wasn't first" assert in 
getMatchingSubClassWithSubRegs in a future patch for EXTRACT_SUBREG 
handling.
Mips defines 4 identical register classes (MSA128B, MSA128H, MSA128BW, 
MSA128D). These have the same set of registers, and only differ by the 
isel type. I believe this is an ill formed way of defining registers, 
that probably is just to work around the inconvenience of mixing 
different types in a single register class in DAG patterns.
Since these all have the same size, they would all sort to the 
beginning, but you would not necessarily get the same super register at
the front as the assert enforces. Breaking the ambiguity by also sorting
by name doesn't work, since each of these register classes all want to
be first. Force sorting of the original register class if the size is
the same.

TableGen/GlobalISel: Handle non-leaf EXTRACT_SUBREG
This previously only handled EXTRACT_SUBREGs from leafs, such as 
operands directly in the original output. Handle extracting from a 
result instruction.

Correct NumLoads in clustering
Scheduler sends NumLoads argument into shouldClusterMemOps() one less
the actual cluster length. So for 2 instructions it will pass just 1.
Correct this number.
This is NFC for in tree targets.
Differential Revision: https://reviews.llvm.org/D73292

Rename test-suite test case to prevent NOEXE failures
In the test-suite, we have two files:
 SingleSource/UnitTests/Vector/Altivec/ld.reference_output
 SingleSource/UnitTests/Vector/Altivec/ld.c
That need to have their name changed to:
 SingleSource/UnitTests/Vector/Altivec/vec_ld.reference_output
 SingleSource/UnitTests/Vector/Altivec/vec_ld.c
Because they cause other test cases in the directory to not produce 
executable once the ld test is built. The reason for the failure is that 
the ./ld is used as the linker when building other tests.