SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. Revert "[macho][NFC] Extract all CPU_(SUB_)TYPE logic to libObject" (details)
  2. [PowerPC][NFC] Cleanup some of the Darwin mentions in the README.txt. (details)
  3. [x86] allow peeking through an extract_subvector to find a splatted operand (details)
  4. [libc] Add Initial Support for Signals (details)
  5. Fix some typos in the MLIR documentation. (details)
  6. [ORC][examples] Fix ThinLtoJIT example after changes in 85fb997659b. (details)
  7. [ORC] Add a convenience method for setting the ExecutionSession to LLJITBuilder. (details)
  8. [X86] Fix NSW/NUW typo in avg test (PR44973) (details)
  9. [clang-format] Merge name and colon into a single token for C# named arguments (details)
  10. libclang: Make shared object symbol exporting by default (details)
  11. [AIX] Pack BasicBlockBits (details)
  12. [clang][doxygen] Fix false -Wdocumentation warning for tag typedefs (details)
  13. [GISel][KnownBits] Give up on PHI analysis as soon as we don't know anything (details)
  14. [cxx_status] Update -std= instructions for C++20. (details)
  15. [llvm][build] Fix shared lib builds. [NFC] (details)
  16. Revert "[NFCI][DebugInfo]: Corrected a Typo." (details)
  17. [ConstantFold] add/move tests for FP with undef operand; NFC (details)
  18. Revert "[AArch64][SVE] Add intrinsics for SVE2 bitwise ternary operations" (details)
  19. Revert "libclang: Add static build support for Windows" and (details)
  20. [X86] Replace a bad use of MVT::getVectorVT with EVT::getVectorVT (details)
  21. Revert 714265dabb606bfef2f85694234f152edbfa91ac "[X86] Replace a bad use of MVT::getVectorVT with EVT::getVectorVT" (details)
  22. Recommit "[X86] Replace a bad use of MVT::getVectorVT with EVT::getVectorVT"" (details)
  23. [AIX] Improve 32/64-bit build configuration (details)
  24. [ASTImporter] Add linkage check to ASTNodeImporter::hasSameVisibilityContext and rename to hasSameVisibilityContextAndLinkage (details)
  25. [Driver] Escape the program path for -frecord-command-line (details)
  26. [SVE] Add support for lowering GEPs involving scalable vectors. (details)
  27. [SCCP] Do not mark unknown loads as overdefined. (details)
  28. [mlir] [VectorOps] Multi-dim reductions for lowering vector.contract (details)
  29. [mlir] Use LLJIT::getMainJITDylib instead of hardcoding '<main>' (details)
  30. [lldb/Plugin] Don't mark ProcessNetBSD as a plugin (details)
  31. Revert "[Driver] Escape the program path for -frecord-command-line" (details)
  32. [mlir][Parser] Update DenseElementsAttr to print in hex when the number of elements is over a certain threshold. (details)
  33. [lldb/Test] Remove stale README in test/API (details)
  34. [libc++] Explain XFAILs with std::uncaught_exceptions test (details)
  35. [X86] Custom legalize v1i1 add/sub/mul to xor/xor/and with avx512. (details)
  36. [X86] Fix a couple copy mistakes in v4i1 or/and/xor isel patterns. (details)
  37. [X86] Custom legalize v1i1 UADDSAT/USUBSAT/SADDSAT/UADDSAT to match v2i1/v4i1/v8i1 etc. (details)
  38. [X86] Expand vselect of v1i1 under avx512. (details)
  39. [X86] Add CMOV_VK1 pseudo so we don't crash on v1i1 ISD::SELECT (details)
  40. [libc++][regex] Validate backreferences in the constructor. (details)
  41. [libunwind][CMake] Treat S files as C to work around CMake bug. (details)
  42. Filter callbr insts from critical edge splitting (details)
  43. [Dominators] Use Instruction::comesBefore for block-local queries, NFC (details)
  44. [XCore] Add instruction pattern for bitrev (details)
  45. [OpenMP][NFC] Remove leftover debug messages (details)
  46. [mlir] Use getOperation()->setAttr when generating attribute set (details)
  47. Split _LIBCPP_STRING_EXTERN_TEMPLATE_LIST up into a V1 and UNSTABLE version. (details)
  48. [X86] Add CMOV_VR64 pseudo instruction for MMX. Remove mmx handling from combineSelect. (details)
  49. libclc: Use acos implementation from amd_builtins (details)
  50. [X86] Remove unnecessary isNullConstant in LowerSelect. NFC (details)
  51. [WebAssembly] Remove unneeded getWasmKindForNamedSection function (details)
  52. [X86] Autogenerate complete checks. NFC (details)
  53. [X86] Make combineCMov not create unsupported FCMOVs when f32/f64 are using X87. (details)
  54. [X86] Don't bother avoiding illegal FCMOVs if we don't have the cmov subtarget feature. (details)
  55. [clangd] Fix the incomplete template specialization in findTarget. (details)
  56. [lldb][NFC] Split up ClangASTSource::FindExternalVisibleDecls (details)
  57. [clangd] Allow renaming class templates in cross-file rename. (details)
  58. Make unittests include path relative (details)
  59. [NFC][mlir] Adding more operators to EDSC TemplatedIndexedValue (details)
  60. test/CodeGen/AMDGPU: Add a test case that shows a miscompilation (details)
  61. [NFC] Corrected a minor typo in a comment (details)
  62. Detect and disable openmp tests that require multiple hardware processor to run (details)
  63. [ConstantFold] fold fsub -0.0, undef to undef rather than NaN (details)
  64. [DependenceAnalysis] Memory dependence analysis internal caching mechanism is broken in presence of TBAA (PR42733). (details)
  65. [Hexagon] Introduce noop intrinsic to cast between vector predicate types (details)
  66. [mlir] Add a signedness semantics bit to IntegerType (details)
  67. [TargetLowering] SimplifyDemandedBits - use getValidShiftAmountConstant helper. (details)
  68. [X86] Regenerate hi reg tests (details)
  69. [Error/unittests] Add a FailedWithMessage gtest matcher (details)
  70. [PowerPC][NFC] Remove Darwin specific logic in frame finalization. (details)
  71. [AST][NFC] Update outdated comments in ASTStructuralEquivalence.cpp (details)
  72. [PowerPC][NFC] Add a test for vrsave usage iinline asm. (details)
  73. [lldb/DWARF] Add support for type units in dwp files (details)
  74. Remove unused functions in llvm-ml (details)
  75. [mlir] Silence error: call to constructor of 'llvm::APInt' is ambiguous (details)
  76. AMDGPU/GlobalISel: Fix constant bus violation with source modifiers (details)
  77. AMDGPU/GlobalISel: Select llvm.amdgcn.fmul.legacy (details)
  78. AMDGPU/GlobalISel: Legalize G_FPOW (details)
  79. AMDGPU/GlobalISel: Manually select G_BUILD_VECTOR_TRUNC (details)
  80. [ARM] Correct Formatting. NFC (details)
  81. AMDGPU/GlobalISel: Precommit xnor matching test (details)
  82. [ELF] Ignore the maximum of input section alignments for two cases (details)
  83. [ELF] Warn changed output section address (details)
  84. [lldb-vscode] Use libOption with tablegen to parse command line options. (details)
  85. [ELF] Shuffle .init_array/.fini_array with --shuffle-sections= (details)
  86. [TargetLowering] Apply basic shift combines before recursive SimplifyDemandedBits calls. (details)
  87. AMDGPU/GlobalISel: Fix xnor matching (details)
  88. AMDGPU/GlobalISel: Commit test changes I forgot to squash (details)
  89. GlobalISel: Fix narrowing of (G_ASHR i64:x, 32) (details)
  90. [AArch64][SVE] Add +fullfp16 to sve-vector-splat.ll (details)
  91. [DSE,MSSA] Add debug counter. (details)
  92. [AST matchers] Add basic matchers for googletest EXPECT/ASSERT calls. (details)
  93. [VectorCombine] refactor matching code to reduce duplication; NFC (details)
  94. [AArch64][SVE] Add intrinsics for SVE2 bitwise ternary operations (details)
  95. AMDGPU: Use default operand for VOP3P clamp (details)
  96. [SystemZ]  Return scalarized costs for vector instructions on older archs. (details)
  97. [gn build] Port 23444edf30b (details)
  98. [SimplifyLibCalls][IRBuilder] Accept any IRBuilder in SimplifyLibCalls (details)
  99. [X86] Fix SDLoc initialization (details)
  100. [VectorUtils] Move ToVectorTy to VectorUtils.h (NFC). (details)
  101. [DSE,MSSA] Dbg counters required assertions. Mark test accordingly. (details)
  102. [InstCombine] Use replaceOperand() in more places (details)
  103. [Clang interpreter] Rename Block.{h,cpp} to InterpBlock.{h,cpp} (details)
  104. [BFI] Fix missed BFI updates in MachineSink. (details)
  105. [InstCombine] Improve simplify demanded bits worklist management (details)
  106. [llvm][CodeGen] DAG Combiner folds for vscale. (details)
  107. [MLIR] Allow Loop dialect IfOp and ForOp to define values (details)
  108. [XCOFF][AIX] Put undefined symbol name into StringTable when neccessary (details)
  109. [LoopVectorize][X86] Regenerate tests. NFCI. (details)
  110. Fix MSVC "not all control paths return a value" warning. NFCI. (details)
  111. AMDGPU/GlobalISel: Select G_SHUFFLE_VECTOR (details)
  112. AMDGPU/GlobalISel: Select VOP3P instructions (details)
  113. AMDGPU/GlobalISel: Select llvm.amdgcn.fdot2 (details)
  114. AMDGPU: Move dot intrinsic patterns to instruction def (details)
  115. [lldb/cmake] Enable more verbose find_package output. (details)
  116. AMDGPU/GlobalISel: Fix SALU mapping for v2s16 min/max (details)
  117. [ARM] Change ARMAttributeParser::Parse to use support::endianness and simplify (details)
  118. [libc++] Do not set the `availability=XXX` feature when not testing against a system libc++ (details)
  119. [AArch64][SVE] Add backend support for splats of immediates (details)
  120. [CodeGen][RISCV] Fix clang/test/CodeGen/atomic_ops.c for RISC-V (details)
  121. [mlir][spirv] Add lowering for load/store zero-rank memref from std to SPIR-V. (details)
  122. [MLIR] Remove constexpr from LoopOps.td (details)
  123. [Hexagon] Simplify intrinsic (vandvrt (vandqrt q b) m) -> q if possible (details)
  124. Move StandardOps/Ops.h to StandardOps/IR/Ops.h (details)
  125. [llvm][aarch64] SVE addressing modes. (details)
  126. [VectorCombine] refactor cost calcs to reduce duplication; NFC (details)
  127. [llvm][CodeGen][aarch64] Add contiguous prefetch intrinsics for SVE. (details)
  128. [IR] Update BasicBlock::validateInstrOrdering comments, NFC (details)
  129. [X86] Add a new format type for instructions that represent named prefix bytes like data16 and rep. Use it to make a simpler version of isPrefix. (details)
  130. [macho][NFC] Extract all CPU_(SUB_)TYPE logic to BinaryFormat (details)
  131. Allow customized relative PYTHONHOME (details)
  132. [gn build] Port 1874dee5662 (details)
  133. [VectorCombine] refactor to reduce duplicated code; NFC (details)
  134. AMDGPU/GlobalISel: Better code for one case of G_SHUFFLE_VECTOR on v2i16 (details)
  135. [AArch64][SVE] Add support for DestructiveBinary and DestructiveBinaryComm DestructiveInstTypes (details)
  136. [llvm-objcopy][MachO] Change the storage of sections (details)
  137. [lldb/test] Move `platform process list` tests to its own directory (NFC) (details)
  138. [lldb/Plugins] Add ability to fetch crash information on crashed processes (details)
  139. [AArch64][SVE] Fix -Wimplicit-fallthrough after D73711 (details)
  140. clang/Modules: Finish renaming CompilerInstance::ModuleManager, NFC. (details)
  141. [SelectionDAG] remove unused isFast() helper function; NFC (details)
  142. [AArch64][SVE] Fix -DBUILD_SHARED_LIBS=on builds after -D74808/1874dee5662603c9251228c71b66de72cec0c979 (details)
  143. [AArch64] Delete an unneeded dependency on Object after 1874dee5662603c9251228c71b66de72cec0c979 (details)
  144. [Hexagon] Define __ELF__ by default. (details)
  145. [CloneFunction] Update loop headers after cloning all blocks in loop. (details)
  146. [Attributor][FIX] Undo 16188f9 until SCC iterator bug is fixed (details)
  147. [GISel][KnownBits] Add a cache mechanism to speed compile time (details)
  148. [Attributor][FIX] Disable a test to unblock the builders (details)
  149. [Target] Remove libObject dependency in lib/Target (details)
  150. Revert "Allow customized relative PYTHONHOME" (details)
  151. [Analysis][Docs] Parents of loops documentation. (details)
  152. [mlir][DeclarativeParser] Add support for the TypesMatchWith trait. (details)
  153. [mlir][DeclarativeParser] Add basic support for optional groups in the assembly format. (details)
  154. [mlir][DeclarativeParser] Add an 'attr-dict-with-keyword' directive (details)
  155. [mlir] Add a utility iterator range that repeats a given value `n` times. (details)
  156. [mlir][ODS] Add support for specifying the successors of an operation. (details)
  157. [mlir][DeclarativeParser] Add support for formatting the successors of an operation. (details)
  158. [mlir][Tutorial] Add a section to Toy Ch.2 detailing the custom assembly format. (details)
  159. [llvm-objdump] Print method name from debug info in disassembly output. (details)
  160. [MC][ELF] Error for sh_type, sh_flags or sh_entsize change (details)
  161. [lldb/test] Tweak libcxx string test on Apple+ARM devices (details)
  162. Revert "[AMDGPU] Don’t marke the .note section as ALLOC" (details)
  163. [mlir][DeclarativeParser][NFC] Use explicit type names in TypeSwitch to (details)
  164. [Driver] Escape the program path for -frecord-command-line (details)
  165. AMDGPU/GlobalISel: Remove dead code (details)
  166. Allow customized relative PYTHONHOME (Attemp 1) (details)
  167. [llvm-objdump][test] Fix source-interleave-function-from-debug.test on Windows after D74507 (details)
  168. [WebAssembly] Fix a non-determinism problem in FixIrreducibleControlFlow (details)
  169. Flags for displaying only hot nodes in CFGPrinter graph (details)
  170. [lldb][test] Fix sh_type of .debug_cu_index and .debug_tu_index (details)
  171. Remove unused variable (details)
  172. [X86] Teach combineCVTPH2PS to shrink v8i16 loads when the output type is v4f32. Remove extra isel patterns. (details)
  173. [lldb][test] Fix sh_flags and sh_entsize of .debug_str.dwo (details)
  174. [libc] Lay out framework for fuzzing libc functions. (details)
  175. [GISel][KnownBits] Suppress unused warning on the dump method (details)
  176. [Preprocessor][test] Move AArch64 tests from init.c to init-aarch.c (details)
  177. [Preprocessor][test] Fix __VERSION__ in init-aarch64.c (details)
  178. [Frontend] Replace CC1 option -mcode-model with -mcmodel= (details)
  179. [AArch64] Predefine __AARCH64_CMODEL_*__ as GCC does (details)
  180. [Preprocessor][X86] Fix __code_model_*__ predefine macros (details)
  181. Update Quantization.md (details)
  182. Update ShapeInference.md (details)
  183. [VE][fix] missing include (details)
  184. [yaml2obj] - Automatically assign sh_addr for allocatable sections. (details)
  185. [lldb][test] - Update basic-elf.yaml to fix build bot. (details)
  186. [NFC] Remove some GCC warning from c9e93c84f61400d1aac7d195a0578e80bc48c69a (details)
  187. [libcxx] [test] Suppress MSVC++ warning 4640 under /Zc:threadSafeInit- (details)
  188. Add a llvm::shuffle and use it in lld (details)
  189. [Sema] Fix pointer-to-int-cast diagnostic for _Bool (details)
  190. [ORC] Add errors for missing and extraneous symbol definitions. (details)
  191. [ORC] Update LLJIT to automatically run specially named initializer functions. (details)
  192. [X86] Use movlps for i64 atomic stores on 32-targets with sse1. (details)
  193. [X86] Teach EltsFromConsecutiveLoads that it's ok to form a v4f32 VZEXT_LOAD with a 64 bit memory size on SSE1 targets. (details)
  194. [X86] Add AddToWorklist(N) after calls to SimplifyDemandedBits/SimplifyDemandedVectorElts that are called on an operand of N. (details)
  195. [X86] Add sse2 command lines to sse-intrinsics-fast-isel.ll. (details)
  196. [NFC] Test commit access. Drop trivial braces. (details)
  197. [NFC] fix test nan value (details)
  198. [clangd] Debounce rebuilds responsively to rebuild times. (details)
  199. [clangd] Reapply b60896fad926 Fall back to selecting token-before-cursor if token-after-cursor fails. (details)
  200. Revert "[clangd] Reapply b60896fad926 Fall back to selecting token-before-cursor if token-after-cursor fails." (details)
  201. [DSE] Track overlapping stores. (details)
  202. [SDAG] fold fsub -0.0, undef to undef rather than NaN (details)
  203. [X86] Regenerate some tests to show FMA4 comments. NFC (details)
  204. Recommit "[PatternMatch] Match XOR variant of unsigned-add overflow check." (details)
  205. [AArch64] Update new test. (details)
  206. [clangd] Reapply b60896fad926 Fall back to selecting token-before-cursor if token-after-cursor fails. (details)
  207. Updating a comment to clarify that SkipUntil handles balanced delimiters. (details)
  208. [clangd] Try to fix buildbots - copy elision not happening here? (details)
  209. [SystemZ]  Support the kernel back chain. (details)
  210. [X86] Use FIST for i64 atomic stores on 32-bit targets without SSE. (details)
  211. [X86] Enable the use of movlps for i64 atomic load on 32-bit targets with sse1. (details)
  212. [X86] Remove most X86 specific subclasses of MemSDNode. Just use a MemIntrinsicSDNode as we usually do. (details)
  213. [SelectionDAG] Remove SelectionDAG::getTargetMemSDNode now that its not used. (details)
  214. IR printing for single function with the new pass manager. (details)
  215. [NFC][PowerPC] Refactor the tryAndWithMask() (details)
  216. [Driver][X86] Add helptext for malign-branch*, mbranches-within-32B-boundaries (details)
  217. [libc] Add a README to the sub-directories under the utils directory. (details)
  218. [SelectionDAG] Remove ISD::LIFETIME_START/LIFETIME_END from assert in getMemIntrinsicNode. (details)
  219. [X86] Use custom isel for gather/scatter instructions. (details)
  220. [X86] When creating X86ISD::MGATHER nodes from AVX2 gather intrinsics, cast the mask to integer type. (details)
  221. [JITLink] Add a MachO x86-64 GOT and Stub bypass optimization. (details)
  222. [lldb] Remove all the 'current_id'  logging counters from the lookup code. (details)
  223. [ARM][MVE] Combine more extending masked loads (details)
  224. [lldb/DWARF] Don't index dwp file multiple times (details)
  225. [lldb/test] simplify basic-elf.yaml (details)
  226. [lldb] Disable auto fix-its when evaluating expressions in the test suite (details)
  227. [MC] Widen the functional unit type from 32 to 64 bits. (details)
  228. Use new FailedWithMessage matcher in DWARFDebugLineTest.cpp (details)
  229. [profile] Don't dump counters when forking and don't reset when calling exec** functions (details)
  230. [Intrinsic] Add fixed point saturating division intrinsics. (details)
  231. Add a basic tiling pass for parallel loops (details)
  232. Silence compiler warnings (details)
  233. [AArch64][SVE] Add intrinsics for SVE2 cryptographic instructions (details)
  234. [ORC] Remove spammy debug print (details)
  235. Use temporary directory for tests in D74346 (details)
  236. [CostModel][X86] Try to check against common prefixes before using target-specific cpu checks (details)
  237. [ARM] FP16 bitcast test. NFC (details)
  238. [ARM,MVE] Remove 64-bit variants of vbrsrq* intrinsics (details)
  239. Fix TryParsePtrOperatorSeq. (details)
  240. [RDA][ARM][LowOverheadLoops] Iteration count IT blocks (details)
  241. [AArch64][SVE] Add the SVE dupq_lane intrinsic (details)
  242. [MIR][ARM] MachineOperand comments (details)
  243. [CostModel][X86] We don't need a scale factor for SLM extract costs (details)
  244. add release notes for ffp-model and ffp-exception-behavior (details)
  245. [AIX][Frontend] C++ ABI customizations for AIX boilerplate (details)
  246. [OpenMP] Refactor the analysis in checkMapClauseBaseExpression using StmtVisitor class. (details)
  247. [libc++] Implementation of C++20's P1135R6 for libcxx (details)
  248. [libc++] Adapt a few things around the implementation of P1135R6 (details)
  249. [libc++] Mark the C++03 version of std::function as deprecated (details)
  250. [lldb/DWARF] Fix dwp search path in the separate-debug-file case (details)
  251. [PowerPC][AIX] Spill/restore the callee-saved condition register bits. (details)
  252. [X86] getTargetShuffleInputs - check that the source inputs are all the right size. (details)
  253. [gn build] (manually) merge 54fa9ecd308 (details)
  254. [libc++] Fix CI and Linux failures after landing D68480 (details)
  255. [gn build] remove -std=c++11 in libcxx build pending discussion in 80e73f2 review thread (details)
  256. Revert "Rework go bindings so that validation works fine" (details)
  257. [NFC] Fix typo in error message (details)
  258. [libc++] Drop redundant check for -std=c++14 (details)
  259. [ReleaseNotes] Mention the `vector-function-abi-variant` attribute. (details)
  260. [CMake] Default to static linking for subprojects. (details)
  261. [XCOFF][AIX] Fix incorrect alignment for function descriptor csect (details)
  262. [AVR] Use correct register class for mul instructions (details)
  263. [AVR] Don't assert on an undefined operand (details)
  264. [X86] combineX86ShuffleChain - select X86ISD::FAND/ISD::AND based on MaskVT (details)
  265. [AVR] Disassemble register operands (details)
  266. [bindings/go] Add RemoveFromParentAsInstruction (details)
  267. [MachO] Add cpu(sub)type tests and improve error handling (details)
  268. [SelectionDAG] Merge constant SDNode arithmetic into foldConstantArithmetic (details)
  269. [LLVM-C] Add bindings for addCoroutinePassesToExtensionPoints (details)
  270. [mlir][spirv] NFC: Move test passes to test/lib (details)
  271. [libc++] Give headers that require C++14 a cplusplus14 requires in the modulemap (details)
  272. [AMDGPU] use llvm_unreachable instead of default for rp set (details)
  273. [X86] Add back fmaddsub intrinsics to work towards fixing the strict fp implementation (details)
Commit 3f785212e9ceb85251183b1fcf5902715df923fb by francisvm
Revert "[macho][NFC] Extract all CPU_(SUB_)TYPE logic to libObject"

This reverts commit 726c342ce27ada28efe90cb04ffb69c75065710a.

This breaks the windows bots with linker errors.
The file was modifiedllvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
The file was modifiedllvm/lib/Object/MachOObjectFile.cpp
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64MachObjectWriter.cpp
The file was modifiedllvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
The file was modifiedllvm/include/llvm/Object/MachO.h
The file was modifiedllvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h
The file was modifiedllvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
Commit da181d4ba0cdbae487ba1571917adb8677456e55 by sd.fertile
[PowerPC][NFC] Cleanup some of the Darwin mentions in the README.txt.
The file was modifiedllvm/lib/Target/PowerPC/README.txt
Commit 064cd2ecdb3d0c52be5b6cf4fc67125baa714d3a by spatel
[x86] allow peeking through an extract_subvector to find a splatted operand

The motivating case is seen in "splat4_v8f32_load_store" and based on code in PR42024:
https://bugs.llvm.org/show_bug.cgi?id=42024
(I haven't stepped through the v8i32 sibling test yet to see why that diverged.)

There are other potential improvements visible like allowing scalarization or vector
narrowing.

Differential Revision: https://reviews.llvm.org/D74909
The file was modifiedllvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-512-v32.ll
The file was modifiedllvm/test/CodeGen/X86/pr34653.ll
The file was modifiedllvm/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll
The file was modifiedllvm/test/CodeGen/X86/x86-interleaved-access.ll
The file was modifiedllvm/test/CodeGen/X86/avx-intrinsics-fast-isel.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/extractelement-load.ll
The file was modifiedllvm/test/CodeGen/X86/fma.ll
The file was modifiedllvm/test/CodeGen/X86/avx-splat.ll
The file was modifiedllvm/test/CodeGen/X86/insertelement-var-index.ll
The file was modifiedllvm/test/CodeGen/X86/masked_gather.ll
The file was modifiedllvm/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
Commit 5d2baa956ac3784e3956e35f610e118cacc7128b by alexbrachetmialot
[libc] Add Initial Support for Signals

Summary:
This patch adds signal support on Linux. The current implementation gets the SIG* macros and types like `sigset_t` from <linux/signals.h>

This patch also adds raise(3), and internal routines  `block_all_signals` and `restore_signals`

Reviewers: sivachandra, MaskRay, gchatelet

Reviewed By: sivachandra

Subscribers: libc-commits, mgorny, tschuett

Differential Revision: https://reviews.llvm.org/D74528
The file was addedlibc/src/signal/linux/signal.h
The file was modifiedlibc/config/linux/api.td
The file was modifiedlibc/test/src/CMakeLists.txt
The file was modifiedlibc/include/CMakeLists.txt
The file was modifiedlibc/src/CMakeLists.txt
The file was addedlibc/src/signal/raise.h
The file was addedlibc/test/src/signal/CMakeLists.txt
The file was addedlibc/include/signal.h.def
The file was addedlibc/config/linux/signal.h.in
The file was modifiedlibc/spec/stdc.td
The file was modifiedlibc/spec/linux.td
The file was addedlibc/src/signal/linux/CMakeLists.txt
The file was addedlibc/src/signal/linux/raise.cpp
The file was modifiedlibc/lib/CMakeLists.txt
The file was addedlibc/test/src/signal/raise_test.cpp
The file was addedlibc/src/signal/CMakeLists.txt
Commit 8928c6dbbf7d1de32e84f3ec2b778c006fc70091 by riddleriver
Fix some typos in the MLIR documentation.

Summary: Fix minor typos in the tutorial and the "writing a pass" page.

Differential Revision: https://reviews.llvm.org/D74905
The file was modifiedmlir/docs/Tutorials/Toy/Ch-6.md
The file was modifiedmlir/docs/Tutorials/Toy/Ch-5.md
The file was modifiedmlir/docs/WritingAPass.md
The file was modifiedmlir/docs/Tutorials/Toy/Ch-4.md
Commit 6de21c556d159d29e7957821fa8b83ef68083b76 by Lang Hames
[ORC][examples] Fix ThinLtoJIT example after changes in 85fb997659b.
The file was modifiedllvm/examples/ThinLtoJIT/ThinLtoJIT.cpp
Commit 813b1b9fd6c19706b735a595d33f7b8ebcd08be7 by Lang Hames
[ORC] Add a convenience method for setting the ExecutionSession to LLJITBuilder.

Can be used to set a custom pre-configured ExecutionSession for the LLJIT or
LLLazyJIT instance being constructed.
The file was modifiedllvm/include/llvm/ExecutionEngine/Orc/LLJIT.h
Commit e2c2eb0a5509ed8e013c4e4d880de27e60641b9a by llvm-dev
[X86] Fix NSW/NUW typo in avg test (PR44973)

The not_avg_v16i8_wide_constants test shouldn't assume NSW/NUW for the addition of -1 - copy + paste typo from other avg tests
The file was modifiedllvm/test/CodeGen/X86/avg.ll
Commit a11ff39ba2ad3975a40e2684948a4dd2ada89bd3 by jbcoe
[clang-format] Merge name and colon into a single token for C# named arguments

Summary:
Merge 'argumentName' and ':' into a single token in foo(argumentName: bar).

Add C# named argument as a token type.

Reviewers: krasimir, MyDeveloperDay

Reviewed By: krasimir

Tags: #clang-format

Differential Revision: https://reviews.llvm.org/D74894
The file was modifiedclang/unittests/Format/FormatTestCSharp.cpp
The file was modifiedclang/lib/Format/FormatTokenLexer.h
The file was modifiedclang/lib/Format/FormatTokenLexer.cpp
The file was modifiedclang/lib/Format/FormatToken.h
Commit 7a7c753b0cca6abb61f054842fb087dfc30dc563 by thakis
libclang: Make shared object symbol exporting by default

https://reviews.llvm.org/D74564 enabled static building for libclang,
and for non CMake consumers they had to set the `CMAKE_EXPORTS` define
when consuming libclang.

This commit makes the non CMake users of the static building have to define `CMAKE_NO_EXPORTS`.

Differential Revision: https://reviews.llvm.org/D74907
The file was modifiedclang/include/clang-c/Platform.h
The file was modifiedclang/tools/libclang/CMakeLists.txt
Commit 967eeb109bedc4ae606fdf6ad6eca58ffbac6739 by daltenty
[AIX] Pack BasicBlockBits

Summary:
D51664 introduces a new structure BasicBlockBits which it expects to be
packed a certain way. This change is very similar to D60164, and we apply the
same fix:

"On AIX, the canonical layout of bit-fields would cause
these ... to span four bytes. Applying the pack pragma for compilers that
employ the AIX canonical layout allows these ... to fit within the expected
two bytes. In the future, the pragma would also likely need to be applied when
building with Clang on AIX."

Reviewers: jasonliu, hubert.reinterpretcast, sfertile, xingxue

Reviewed By: sfertile

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74911
The file was modifiedllvm/include/llvm/IR/BasicBlock.h
Commit 2f56789c8fe8edb57bc7a193592ecd35a393fe4a by Jan Korous
[clang][doxygen] Fix false -Wdocumentation warning for tag typedefs

For tag typedefs like this one:

/*!
@class Foo
*/
typedef class { } Foo;

clang -Wdocumentation gives:

warning: '@class' command should not be used in a comment attached to a
non-struct declaration [-Wdocumentation]

... while doxygen seems fine with it.

Differential Revision: https://reviews.llvm.org/D74746
The file was modifiedclang/include/clang/AST/CommentSema.h
The file was modifiedclang/lib/AST/CommentSema.cpp
The file was addedclang/test/Sema/warn-documentation-tag-typedef.cpp
Commit e4a9225f5d10f35cf9cf3664bb93620880228782 by qcolombet
[GISel][KnownBits] Give up on PHI analysis as soon as we don't know anything

When analyzing PHIs, we gather the known bits for every operand and
merge them together to get the known bits of the result of the PHI.
It is not unusual that merging the information leads to know nothing
on the result (e.g., phi a: i8 3, b: i8 unknown, ..., after looking at the
second argument we know we will know nothing on the result), thus, as
soon as we reach that state, stop analyzing the following operand (i.e.,
on the previous example, we won't process anything after looking at `b`).

This improves compile time in particular with PHIs with a large number
of operands.

NFC.
The file was modifiedllvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
Commit 6d34a87bae6ea211076c25faef7da5d29cb8e46d by richard
[cxx_status] Update -std= instructions for C++20.

We merged support for -std=c++20 to the Clang 10 branch, so -std=c++2a
is only needed in Clang 9 and earlier.
The file was modifiedclang/www/cxx_status.html
Commit 0c8fa6db90ae856b844d7d2925672cbaef3e0668 by francesco.petrogalli
[llvm][build] Fix shared lib builds. [NFC]

The code at https://reviews.llvm.org/D74808 has broken builds that are
configured with -DBUILD_SHARED_LIBS=On.

This patch adds the correct library dependencies.
The file was modifiedllvm/lib/Target/PowerPC/MCTargetDesc/LLVMBuild.txt
The file was modifiedllvm/lib/Target/ARM/MCTargetDesc/LLVMBuild.txt
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/LLVMBuild.txt
Commit 3d0564c7e07b00a4ddd672e5efb12b75501f47d9 by SourabhSingh.Tomar
Revert "[NFCI][DebugInfo]: Corrected a Typo."

This reverts commit 3e1090922a0b808f424ff424b744752b0d53a3ee
as per Paul Robinson's suggestion.
The file was modifiedllvm/lib/DebugInfo/DWARF/DWARFAbbreviationDeclaration.cpp
Commit 7ddbf802cf64e89b77ef2ce44182248921a42172 by spatel
[ConstantFold] add/move tests for FP with undef operand; NFC
The file was modifiedllvm/test/Transforms/InstSimplify/fp-undef.ll
The file was addedllvm/test/Analysis/ConstantFolding/fp-undef.ll
Commit 6f4d9d10293d8e93d7cf3397e3a82ac19c8b629f by thakis
Revert "[AArch64][SVE] Add intrinsics for SVE2 bitwise ternary operations"

This reverts commit ce70e2899879e092b153a4078b993833b6696713.
It broke MC/AArch64/SVE2/bsl-diagnostics.s everywhere.
The file was removedllvm/test/CodeGen/AArch64/sve2-bitwise-ternary.ll
The file was modifiedllvm/include/llvm/IR/IntrinsicsAArch64.td
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
Commit e84444781aad23ed66d46d23637df4768677e76e by thakis
Revert "libclang: Add static build support for Windows" and
follow-up "libclang: Make shared object symbol exporting by default"

This reverts commit 7a7c753b0cca6abb61f054842fb087dfc30dc563.
This reverts commit 7ff1f55a1219719f57a6f7905c26ce41d1767e4c.

They broke building libclang.dll on Windows, see
https://reviews.llvm.org/D74564
The file was modifiedclang/include/clang-c/Platform.h
The file was modifiedclang/tools/libclang/CMakeLists.txt
Commit 714265dabb606bfef2f85694234f152edbfa91ac by craig.topper
[X86] Replace a bad use of MVT::getVectorVT with EVT::getVectorVT

The type here isn't guaranteed to be a simple type.

Fixes PR44976
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was addedllvm/test/CodeGen/X86/pr44976.ll
Commit 1d8860f90bcec1902e2d247c6b1261955a4b6353 by craig.topper
Revert 714265dabb606bfef2f85694234f152edbfa91ac "[X86] Replace a bad use of MVT::getVectorVT with EVT::getVectorVT"

I accidentally messed up the author on the previous commit somehow.
The file was removedllvm/test/CodeGen/X86/pr44976.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit c7b54a196e1363cbe43122f01a728cd71fa1686a by craig.topper
Recommit "[X86] Replace a bad use of MVT::getVectorVT with EVT::getVectorVT""

With the correct author this time
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was addedllvm/test/CodeGen/X86/pr44976.ll
Commit 9e0c95572e5a245b79eff2b214d9b3580e703e4d by daltenty
[AIX] Improve 32/64-bit build configuration

Summary:
AIX supports both 32-bit and 64-bit environments (with 32-bit being the default). This patch improves support for building LLVM on AIX in both 32-bit and 64-bit mode.

  - Change host detection to return correct 32/64-bit triple as config_guess does not return the correct version on 64-bit. This can confuse JIT tests and other things that care about what the host triple is.
  - Remove manual setting of 64-bit flags on AIX. AIX provides OBJECT_MODE environment variable to enable the user to obtain a 64-bit development environment. CMake will properly set these flags provided the user sets the correct OBJECT_MODE before configuring and setting them manually will interfere with 32-bit builds.
  - Don't present the LLVM_BUILD_32_BITS option on AIX, users should use OBJECT_MODE when running CMake instead.

Reviewers: hubert.reinterpretcast, DiggerLin, stevewan

Reviewed By: DiggerLin, stevewan

Subscribers: mgorny, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74256
The file was modifiedllvm/CMakeLists.txt
The file was modifiedllvm/cmake/modules/HandleLLVMOptions.cmake
The file was modifiedllvm/cmake/modules/GetHostTriple.cmake
Commit bf3f427ba239bd2942bfaa350d06ed072935f048 by shafik
[ASTImporter] Add linkage check to ASTNodeImporter::hasSameVisibilityContext and rename to hasSameVisibilityContextAndLinkage

This fixed is based on the assert in LinkageComputer::getLVForDecl(...) which assumes that all the decls in a redecl chain have the same linkage.

Differential Revision: https://reviews.llvm.org/D74639
The file was modifiedclang/lib/AST/ASTImporter.cpp
Commit 6123074d0c0de3614f1552f2f2d6b9db7b32cebe by scott.linder
[Driver] Escape the program path for -frecord-command-line

Similar to the rest of the command line that is recorded, the program
path must also have spaces and backslashes escaped. Without this
parsing the recorded command line becomes hard on platforms like
Windows where spaces and backslashes are common.

Patch By: Ravi Ramaseshan
Differential Revision: https://reviews.llvm.org/D74811
The file was modifiedclang/test/Driver/clang_f_opts.c
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
Commit c767cf24e48d9f6c17179abf2e42497601c7165b by efriedma
[SVE] Add support for lowering GEPs involving scalable vectors.

This includes both GEPs where the indexed type is a scalable vector, and
GEPs where the result type is a scalable vector.

Differential Revision: https://reviews.llvm.org/D73602
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was addedllvm/test/CodeGen/AArch64/sve-gep.ll
Commit 99809f98d7bb18dbe3be543942a4b467dff7e92e by flo
[SCCP] Do not mark unknown loads as overdefined.

For tracked globals that are unknown after solving, we expect all
non-store uses to be replaced.

This is a follow-up to f8045b250d80, which removed forcedconstant.

We should not mark unknown loads as overdefined, as they either load
from an unknown pointer or an undef global. Restore the original logic
for loads.
The file was addedllvm/test/Transforms/SCCP/loadtest2.ll
The file was modifiedllvm/test/Transforms/SCCP/apint-bigint2.ll
The file was modifiedllvm/lib/Transforms/Scalar/SCCP.cpp
The file was modifiedllvm/test/Transforms/IPConstantProp/PR26044.ll
The file was modifiedllvm/test/Transforms/SCCP/loadtest.ll
Commit ee260c1a0f1c0a8fd1179cdab9fb4312086dcc54 by ajcbik
[mlir] [VectorOps] Multi-dim reductions for lowering vector.contract

Summary:
This implements the last step for lowering vector.contract progressively
to LLVM IR (except for masks). Multi-dimensional reductions that remain
after expanding all parallel dimensions are lowered into into simpler
vector.contract operations until a trivial 1-dim reduction remains.

Reviewers: nicolasvasilache, andydavis1

Reviewed By: andydavis1

Subscribers: mehdi_amini, rriddle, jpienaar, burmako, shauheen, antiagainst, nicolasvasilache, arpith-jacob, mgester, lucyrfox, liufengdb, Joonsoo, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74880
The file was modifiedmlir/test/Dialect/VectorOps/vector-contract-transforms.mlir
The file was modifiedmlir/lib/Dialect/VectorOps/VectorTransforms.cpp
Commit 6d60d8695d2066c9ef9360603c88ce938ca65491 by riddleriver
[mlir] Use LLJIT::getMainJITDylib instead of hardcoding '<main>'

This fixes test failures caused by a change to the name of the main
dylib, now called 'main'. It also hardens the engine against potential
future changes to the name.
The file was modifiedmlir/lib/ExecutionEngine/ExecutionEngine.cpp
Commit 3ee281082737d18585abff3b482a7ab86af73b5a by Jonas Devlieghere
[lldb/Plugin] Don't mark ProcessNetBSD as a plugin

ProcessNetBSD has no initializers so it's just a regular library and
shouldn't have the PLUGIN argument in add_lldb_library.
The file was modifiedlldb/source/Plugins/Process/NetBSD/CMakeLists.txt
Commit 577d9ce35532439203411c999deefc9c80e04c69 by scott.linder
Revert "[Driver] Escape the program path for -frecord-command-line"

This reverts commit 6123074d0c0de3614f1552f2f2d6b9db7b32cebe.

Quoting/escaping rules seem host specific, so the test is failing on
some bots.
The file was modifiedclang/test/Driver/clang_f_opts.c
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
Commit 51bf5d3cc19ac113de2ff185fb5bc2b99b8d89bc by riddleriver
[mlir][Parser] Update DenseElementsAttr to print in hex when the number of elements is over a certain threshold.

Summary: DenseElementsAttr is used to store tensor data, which in some cases can become extremely large(100s of mb). In these cases it is much more efficient to format the data as a string of hex values instead.

Differential Revision: https://reviews.llvm.org/D74922
The file was modifiedmlir/lib/IR/AsmPrinter.cpp
The file was modifiedmlir/test/IR/invalid.mlir
The file was addedmlir/test/IR/dense-elements-hex.mlir
The file was modifiedmlir/include/mlir/IR/Attributes.h
The file was modifiedmlir/lib/IR/Attributes.cpp
The file was modifiedmlir/lib/Parser/Parser.cpp
Commit 0d19b016226dc2c442a34abfe9b9c06ab4d7ea1e by Jonas Devlieghere
[lldb/Test] Remove stale README in test/API

Now that the test live in the same directory the README is no longer
relevant.
The file was removedlldb/test/API/README.md
Commit 07c559caef967cda9812ab7b6ab94c20748e6ac9 by Louis Dionne
[libc++] Explain XFAILs with std::uncaught_exceptions test
The file was modifiedlibcxx/test/std/language.support/support.exception/uncaught/uncaught_exceptions.pass.cpp
Commit d95a10a7f976188e4ffec77d82000afc53a6d39a by craig.topper
[X86] Custom legalize v1i1 add/sub/mul to xor/xor/and with avx512.

We already did this for v2i1, v4i1, v8i1, etc.
The file was modifiedllvm/test/CodeGen/X86/avx512-mask-op.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 5228a5544b2c887dab3aede7baf818ca4244141e by craig.topper
[X86] Fix a couple copy mistakes in v4i1 or/and/xor isel patterns.

VK1 was being used as the output of the copy to regclass, but it
should be VK2/VK4. Shouldn't matter in practice though since
VK1/VK2/VK4/VK8/VK16 are all identicaly and just have different VTs.
The file was modifiedllvm/lib/Target/X86/X86InstrAVX512.td
Commit b00ef8951b52451eb31f9e41848246c8fb17a2bb by craig.topper
[X86] Custom legalize v1i1 UADDSAT/USUBSAT/SADDSAT/UADDSAT to match v2i1/v4i1/v8i1 etc.
The file was modifiedllvm/test/CodeGen/X86/avx512-mask-op.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 7e927698621f476e698eea14e6954057c81ccf4b by craig.topper
[X86] Expand vselect of v1i1 under avx512.

We already do this for v2i1, v4i1, etc.
The file was modifiedllvm/test/CodeGen/X86/avx512-select.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit e5782377f3f6184abc73a7098c9a0cea0a93350f by craig.topper
[X86] Add CMOV_VK1 pseudo so we don't crash on v1i1 ISD::SELECT
The file was modifiedllvm/lib/Target/X86/X86InstrCompiler.td
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/avx512-select.ll
Commit 72ce0c8073bc8dfa109d25a3c5f245ee0285568c by Louis Dionne
[libc++][regex] Validate backreferences in the constructor.

This patch enables throwing exceptions for invalid backreferences
in the constructor when using the basic, extended,  grep, or egrep grammar.

This fixes bug 34297.

Differential Revision: https://reviews.llvm.org/D62453
The file was modifiedlibcxx/test/std/re/re.regex/re.regex.construct/bad_backref.pass.cpp
The file was modifiedlibcxx/include/regex
Commit d4ded05ba851304b26a437896bc3962ef56f62cb by bigcheesegs
[libunwind][CMake] Treat S files as C to work around CMake bug.

The OSX_ARCHITECTURES property is supposed to add the -arch flag when
targeting Apple platforms. However, due to a bug in CMake
(https://github.com/Kitware/CMake/blob/master/Source/cmLocalGenerator.cxx#L1780),
this does not apply to assembly files. This results in a linker error
when trying to build libunwind for i386 on MacOS.

rdar://59642189
The file was modifiedlibunwind/src/CMakeLists.txt
Commit 2fe457690da0fc38bc7f9f1d0aee2ba6a6a16ada by isanbard
Filter callbr insts from critical edge splitting

Similarly to how splitting predecessors with an indirectbr isn't handled
in the generic way, we also shouldn't split callbrs, for similar
reasons.
The file was modifiedllvm/lib/Transforms/Utils/BasicBlockUtils.cpp
The file was modifiedllvm/lib/Transforms/Scalar/LICM.cpp
The file was addedllvm/test/Transforms/LICM/callbr-crash.ll
Commit 7593a480dbce4e26f7dda4aa8f15bffd03acbfdb by Vedant Kumar
[Dominators] Use Instruction::comesBefore for block-local queries, NFC

Use the lazy instruction ordering facility for block-local dominance
queries.

Differential Revision: https://reviews.llvm.org/D74931
The file was modifiedllvm/unittests/IR/DominatorTreeTest.cpp
The file was modifiedllvm/lib/IR/Dominators.cpp
Commit e27b61c1ea3dbc8329673003e16ecba96600933a by tclin914
[XCore] Add instruction pattern for bitrev

Summary:
Add support for lowering bitreverse to the bitrev instruction.
Fix https://bugs.llvm.org/show_bug.cgi?id=34628.

Reviewers: RKSimon, rtrieu, robertlytton

Reviewed By: RKSimon

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74748
The file was modifiedllvm/lib/Target/XCore/XCoreISelLowering.cpp
The file was modifiedllvm/lib/Target/XCore/XCoreInstrInfo.td
The file was addedllvm/test/CodeGen/XCore/bitrev.ll
Commit 4b540fa8a1c1077468cf8eb7c32fd2481cdbc520 by johannes
[OpenMP][NFC] Remove leftover debug messages
The file was modifiedclang/lib/CodeGen/CGOpenMPRuntime.cpp
Commit c32c8fd1437c69f90f48c91c7545a53d33d6ba20 by riddleriver
[mlir] Use getOperation()->setAttr when generating attribute set
methods.

This avoids the need to resolve overloads when the current operation
also defines a 'setAttr' method.
The file was modifiedmlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
The file was modifiedmlir/test/mlir-tblgen/op-attribute.td
Commit d8969a1cb963caa979a7cfd298f79108b9f0c0ca by mvels
Split _LIBCPP_STRING_EXTERN_TEMPLATE_LIST up into a V1 and UNSTABLE version.

This change splits the _LIBCPP_STRING_EXTERN_TEMPLATE_LIST up into a _LIBCPP_STRING_V1_EXTERN_TEMPLATE_LIST containing the stable ABI, and a _LIBCPP_STRING_UNSTABLE_EXTERN_TEMPLATE_LIST containing the unstable ABI.

The purpose is to explicitly define and maintain the two lists, where the unstable ABI allows for ABI breaking changes for purposes such as optimization while offering a strong guarantee that any change inside the unstable ABI does not affect the stable ABI.

As per the comment in the __string header, we do still allow etries to be added to the stable ABI list as the c++ versions and corresponding c++ std API changes.
The file was modifiedlibcxx/include/string
The file was modifiedlibcxx/src/string.cpp
The file was modifiedlibcxx/include/__string
Commit 78be61871704a451a5d9462d7e96ed6c982746d4 by craig.topper
[X86] Add CMOV_VR64 pseudo instruction for MMX. Remove mmx handling from combineSelect.

The combineSelect code was casting to i64 without any check that
i64 was legal. This can break after type legalization.

It also required splitting the mmx register on 32-bit targets.
It's not clear that this makes sense. Instead switch to using
a cmov pseudo like we do for XMM/YMM/ZMM.
The file was modifiedllvm/lib/Target/X86/X86InstrCompiler.td
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/select-mmx.ll
Commit efeafa1bdaa715733fc100bcd9d21f93c7272368 by jano.vesely
libclc: Use acos implementation from amd_builtins

Fixes acos CTS (1 thread, scalar) on AMD Turks.
Reviewer: tstellar
Differential Revision: https://reviews.llvm.org/D74011
The file was removedlibclc/generic/lib/math/acos.inc
The file was modifiedlibclc/generic/lib/math/acos.cl
Commit 457660683154014db4b649e852d152354844338a by craig.topper
[X86] Remove unnecessary isNullConstant in LowerSelect. NFC

At this point in the code we know that Op1 or Op2 is
all ones. Y points to the other operand. In the case that
Op2 is zero, Op1 must be all ones and Y is Op2. The OR
ORs Y into Res. But if Y is 0 the OR will be folded away by
getNode so we don't need to check for it.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit df74033ec9fceb0c7c1c44a61f240c05c4d5b368 by sbc
[WebAssembly] Remove unneeded getWasmKindForNamedSection function

I believe this was carried over from getELFKindForNamedSection since
the wasm backend originally used ELF object writing as a template.

Differential Revision: https://reviews.llvm.org/D74565
The file was modifiedllvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
Commit 3bc525af235038602a2e1143f5491d3b802a8b5b by craig.topper
[X86] Autogenerate complete checks. NFC
The file was modifiedllvm/test/CodeGen/X86/cmov-fp.ll
Commit 263bef2bbcb0b3bad1f9113a638d6e6c92920a6b by craig.topper
[X86] Make combineCMov not create unsupported FCMOVs when f32/f64 are using X87.

This makes the behavior consistent with what's in LowerSELECT.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/cmov-fp.ll
The file was modifiedllvm/test/CodeGen/X86/pseudo_cmov_lower.ll
Commit 97f11600e0b87b69b01412af8df4fc37af652fce by craig.topper
[X86] Don't bother avoiding illegal FCMOVs if we don't have the cmov subtarget feature.

We'll be forced to emit branches so we might as well use the most
direct condition.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/cmov-fp.ll
The file was modifiedllvm/test/CodeGen/X86/pseudo_cmov_lower.ll
Commit e326f52430419af1ca5aed635168672fbaab5654 by hokein.wu
[clangd] Fix the incomplete template specialization in findTarget.

Summary:
FindTarget doesn't report the TemplatePattern for incomplete
specialization.

Reviewers: sammccall

Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, kadircet, usaxena95, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D74900
The file was modifiedclang-tools-extra/clangd/FindTarget.cpp
The file was modifiedclang-tools-extra/clangd/unittests/FindTargetTests.cpp
The file was modifiedclang-tools-extra/clangd/unittests/XRefsTests.cpp
Commit 0e5ed1b26264f7eee32b23c533371c18ce1cdec0 by Raphael Isemann
[lldb][NFC] Split up ClangASTSource::FindExternalVisibleDecls

This function has two functions hidden inside it. Let's make
them proper functions.
The file was modifiedlldb/source/Plugins/ExpressionParser/Clang/ClangASTSource.h
The file was modifiedlldb/source/Plugins/ExpressionParser/Clang/ClangASTSource.cpp
Commit bc498198b5559829d8f7138db01b0f51afefe2a7 by hokein.wu
[clangd] Allow renaming class templates in cross-file rename.

Summary:
It was disabled because we don't handle explicit template
specialization well (due to the index limitation).

renaming templates is normal in practic, rather than disabling it, this patch
allows to rename them though it is not perfect (just a known limitation).

Context: https://github.com/clangd/clangd/issues/280

Reviewers: kbobyrev

Reviewed By: kbobyrev

Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, kadircet, usaxena95, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D74709
The file was modifiedclang-tools-extra/clangd/refactor/Rename.cpp
The file was modifiedclang-tools-extra/clangd/unittests/RenameTests.cpp
Commit e5eeb8465f29bf4e9cf6f1edb88573338fc12725 by sebastian.neubauer
Make unittests include path relative

This change is relevant when embedding the llvm cmake project into
another project.  It should not change the build behavior of a normal
llvm build.

In the case where llvm is embedded as a cmake subproject,
CMAKE_SOURCE_DIR does not point to the expected directory and building
the tests fails.
Using CMAKE_CURRENT_SOURCE_DIR fixes this problem, as it will always
point to the same directory.

Differential Revision: https://reviews.llvm.org/D73466
The file was modifiedllvm/unittests/TableGen/CMakeLists.txt
Commit d0b09f89e0ed01730173e8b609f25da33e826fa6 by zinenko
[NFC][mlir] Adding more operators to EDSC TemplatedIndexedValue

This change adds some missing arithmetic and logical operators to
`TemplatedIndexedValue` for EDSC usage.

Differential Revision: https://reviews.llvm.org/D74686
The file was modifiedmlir/include/mlir/Dialect/AffineOps/EDSC/Builders.h
The file was modifiedmlir/include/mlir/EDSC/Builders.h
Commit 32e4e7196630dfe23072990ef4071df4aaa41bb6 by nicolai.haehnle
test/CodeGen/AMDGPU: Add a test case that shows a miscompilation

Related to https://reviews.llvm.org/D74908

Change-Id: I6ebf3b5c7a32493016994f30d6796c41e95aecde
The file was modifiedllvm/test/CodeGen/AMDGPU/skip-if-dead.ll
Commit a24d46318f669b3882f6c87f58633098e2a157bf by sguelton
[NFC] Corrected a minor typo in a comment
The file was modifiedllvm/lib/Target/ARM/README-Thumb.txt
The file was modifiedllvm/lib/Support/YAMLTraits.cpp
Commit 99b03c1c18de3e4228e31ef04d38f2d530d335be by sguelton
Detect and disable openmp tests that require multiple hardware processor to run

Team tests seem to require at least two physical cores, and using the same trick
as in https://reviews.llvm.org/D55598 doesn't work (why?) .
Using lit configuration instead.

Differential Revision: https://reviews.llvm.org/D74921
The file was modifiedopenmp/runtime/test/lit.cfg
The file was modifiedopenmp/runtime/test/ompt/teams/parallel_team.c
The file was modifiedopenmp/runtime/test/ompt/teams/serial_teams.c
Commit d799190851fdd94800428ba335f864ce5fd8135b by spatel
[ConstantFold] fold fsub -0.0, undef to undef rather than NaN

A question about this behavior came up on llvm-dev:
http://lists.llvm.org/pipermail/llvm-dev/2020-February/139003.html
...and as part of backend improvements in D73978, but this is an IR
change first because we already have fairly thorough tests in place
here.

We decided not to implement a more general change that would have
folded any FP binop with nearly arbitrary constant + undef operand
to undef because that is not theoretically correct (even if it is
practically correct).

Differential Revision: https://reviews.llvm.org/D74713
The file was modifiedllvm/test/Analysis/ConstantFolding/fp-undef.ll
The file was modifiedllvm/lib/IR/ConstantFold.cpp
Commit b0761bbc7639d0901d623e1fbf53ccf6ce066b16 by evgueni.brevnov
[DependenceAnalysis] Memory dependence analysis internal caching mechanism is broken in presence of TBAA (PR42733).

Summary:
There is a flaw in memory dependence analysis caching mechanism when memory accesses with TBAA are involved. Assume we first analysed and cached results for access with TBAA. Later we request dependence for the same memory but without TBAA (or different TBAA). By design these two queries should share one entry in the internal cache which corresponds to a general access (without TBAA).  Thus upon second request internal cached is cleared and we continue analysis for access as if there is no TBAA.

The problem is that even though internal cache is cleared the set of visited nodes is not. That means we won't traverse visited nodes again and populate internal cache with the corresponding dependence results. So we end up  with internal cache in an incomplete state. Current implementation tries to signal that situation by resetting CacheInfo->Pair at line 1104. But that doesn't actually help since later code ignores this invalidation and relies on 'Cache->empty()' property to decide on cache completeness.

Reviewers: reames, hfinkel, chandlerc, fedor.sergeev, asbirlea, fhahn, john.brawn, Prazek, sunfish

Reviewed By: john.brawn

Subscribers: DaniilSuchkov, kosarev, jfb, dantrushin, hiraditya, bmahjour, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D73032
The file was modifiedllvm/lib/Analysis/MemoryDependenceAnalysis.cpp
The file was modifiedllvm/include/llvm/Analysis/MemoryDependenceAnalysis.h
The file was addedllvm/test/Analysis/MemoryDependenceAnalysis/memdep_with_tbaa.ll
Commit c51b0bede82b9eeddce78151dfc257cf738bf367 by kparzysz
[Hexagon] Introduce noop intrinsic to cast between vector predicate types

The (overloaded) intrinsic is llvm.hexagon.V6.pred.typecast[.128B]. The
types of the operand and the return value are HVX boolean vector types.
For each cast, there needs to be a corresponding intrinsic declared,
with different suffixes appended to the name, e.g.
  ; cast <128 x i1> to <32 x i1>
  declare <32 x i1> @llvm.hexagon.V6.pred.typecast.128B.s1(<128 x i1>)
  ; cast <32 x i1> to <64 x i1>
  declare <64 x i1> @llvm.hexagon.V6.pred.typecast.128B.s2(<32 x i1>)
etc.
The file was modifiedllvm/lib/Target/Hexagon/HexagonISelLowering.cpp
The file was modifiedllvm/include/llvm/IR/IntrinsicsHexagon.td
The file was modifiedllvm/lib/Target/Hexagon/HexagonISelLowering.h
The file was modifiedllvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
The file was addedllvm/test/CodeGen/Hexagon/autohvx/vector-predicate-typecast.ll
Commit 35b685270b410f6a1351c2a527021f22330c25b9 by antiagainst
[mlir] Add a signedness semantics bit to IntegerType

Thus far IntegerType has been signless: a value of IntegerType does
not have a sign intrinsically and it's up to the specific operation
to decide how to interpret those bits. For example, std.addi does
two's complement arithmetic, and std.divis/std.diviu treats the first
bit as a sign.

This design choice was made some time ago when we did't have lots
of dialects and dialects were more rigid. Today we have much more
extensible infrastructure and different dialect may want different
modelling over integer signedness. So while we can say we want
signless integers in the standard dialect, we cannot dictate for
others. Requiring each dialect to model the signedness semantics
with another set of custom types is duplicating the functionality
everywhere, considering the fundamental role integer types play.

This CL extends the IntegerType with a signedness semantics bit.
This gives each dialect an option to opt in signedness semantics
if that's what they want and helps code sharing. The parser is
modified to recognize `si[1-9][0-9]*` and `ui[1-9][0-9]*` as
signed and unsigned integer types, respectively, leaving the
original `i[1-9][0-9]*` to continue to mean no indication over
signedness semantics. All existing dialects are not affected (yet)
as this is a feature to opt in.

More discussions can be found at:

https://groups.google.com/a/tensorflow.org/d/msg/mlir/XmkV8HOPWpo/7O4X0Nb_AQAJ

Differential Revision: https://reviews.llvm.org/D72533
The file was modifiedmlir/include/mlir/Dialect/StandardOps/Ops.td
The file was modifiedmlir/include/mlir/IR/Operation.h
The file was modifiedmlir/lib/Dialect/GPU/IR/GPUDialect.cpp
The file was modifiedmlir/lib/Dialect/StandardOps/Ops.cpp
The file was modifiedmlir/lib/IR/TypeDetail.h
The file was modifiedmlir/lib/Dialect/SPIRV/SPIRVOps.cpp
The file was modifiedmlir/lib/Dialect/SPIRV/Serialization/Deserializer.cpp
The file was modifiedmlir/include/mlir/Dialect/QuantOps/UniformSupport.h
The file was modifiedmlir/lib/IR/MLIRContext.cpp
The file was modifiedmlir/lib/Dialect/VectorOps/VectorOps.cpp
The file was modifiedmlir/lib/Dialect/AffineOps/EDSC/Builders.cpp
The file was modifiedmlir/lib/Dialect/FxpMathOps/Transforms/UniformKernelUtils.h
The file was modifiedmlir/lib/IR/AsmPrinter.cpp
The file was modifiedmlir/lib/Parser/Token.h
The file was modifiedmlir/include/mlir/IR/Matchers.h
The file was modifiedmlir/lib/Transforms/LoopFusion.cpp
The file was modifiedmlir/include/mlir/IR/Builders.h
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Promotion.cpp
The file was modifiedmlir/lib/Parser/Lexer.cpp
The file was modifiedmlir/lib/IR/Operation.cpp
The file was modifiedmlir/test/lib/TestDialect/TestPatterns.cpp
The file was modifiedmlir/test/mlir-tblgen/predicate.td
The file was modifiedmlir/lib/Analysis/Utils.cpp
The file was modifiedmlir/include/mlir/IR/Attributes.h
The file was modifiedmlir/include/mlir/IR/Types.h
The file was modifiedmlir/include/mlir/Dialect/FxpMathOps/FxpMathOps.td
The file was modifiedmlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
The file was modifiedmlir/lib/IR/StandardTypes.cpp
The file was modifiedmlir/lib/Parser/TokenKinds.def
The file was modifiedmlir/lib/Dialect/SPIRV/TargetAndABI.cpp
The file was modifiedmlir/test/IR/invalid.mlir
The file was modifiedmlir/test/IR/parser.mlir
The file was modifiedmlir/test/lib/TestDialect/TestDialect.cpp
The file was modifiedmlir/include/mlir/Dialect/VectorOps/VectorOps.td
The file was modifiedmlir/docs/LangRef.md
The file was modifiedmlir/docs/Rationale.md
The file was modifiedmlir/include/mlir/IR/StandardTypes.h
The file was modifiedmlir/include/mlir/IR/OpBase.td
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
The file was modifiedmlir/lib/Dialect/Linalg/Utils/Utils.cpp
The file was modifiedmlir/lib/IR/Attributes.cpp
The file was modifiedmlir/lib/Parser/Token.cpp
The file was modifiedmlir/include/mlir/Dialect/QuantOps/QuantPredicates.td
The file was modifiedmlir/test/mlir-tblgen/op-attribute.td
The file was modifiedmlir/lib/IR/Builders.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td
The file was modifiedmlir/include/mlir/IR/OpDefinition.h
The file was modifiedmlir/lib/Parser/Parser.cpp
The file was modifiedmlir/include/mlir/Dialect/GPU/GPUOps.td
The file was modifiedmlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
Commit 86c52af05a64c4aa9d61984eeda8fb7849a4b0fa by llvm-dev
[TargetLowering] SimplifyDemandedBits - use getValidShiftAmountConstant helper.

Use the SelectionDAG::getValidShiftAmountConstant helper to get const/constsplat shift amounts, which allows us to drop the out of range shift amount early-out.

First step towards better non-uniform shift amount support in SimplifyDemandedBits.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit d33e96b68c6f6424dc81145b1301f4cd478e84a2 by llvm-dev
[X86] Regenerate hi reg tests
The file was modifiedllvm/test/CodeGen/X86/h-register-addressing-32.ll
The file was modifiedllvm/test/CodeGen/X86/h-register-addressing-64.ll
Commit b55c58a2d569f2d92333b05c1a7a00114d75e0a6 by pavel
[Error/unittests] Add a FailedWithMessage gtest matcher

Summary:
We already have a "Failed" matcher, which can be used to check any
property of the Error object. However, most frequently one just wants to
check the error message, and while this is possible with the "Failed"
matcher, it is also very convoluted
(Failed<ErrorInfoBase>(testing::Property(&ErrorInfoBase::message, "the
message"))).

Now, one can just write: FailedWithMessage("the message"). I expect that
most of the usages will remain this simple, but the argument of the
matcher is not limited to simple strings -- the argument of the matcher
can be any other matcher, so one can write more complicated assertions
if needed (FailedWithMessage(ContainsRegex("foo|bar"))). If one wants to
match multiple error messages, he can pass multiple arguments to the
matcher.

If one wants to match the message list as a whole (perhaps to check the
message count), I've also included a FailedWithMessageArray matcher,
which takes a single matcher receiving a vector of error message
strings.

Reviewers: sammccall, dblaikie, jhenderson

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74898
The file was modifiedllvm/unittests/Support/ErrorTest.cpp
The file was modifiedllvm/include/llvm/Testing/Support/Error.h
Commit 4fdaac0e1eb8e75fe59de0bd01cf72329dacbdb4 by sd.fertile
[PowerPC][NFC] Remove Darwin specific logic in frame finalization.

Remove some cumbersome Darwin specific logic for updating the frame
offsets of the condition-register spill slots. The containing function has an
early return if the subtarget is not ELF based which makes the Darwin logic
dead.
The file was modifiedllvm/lib/Target/PowerPC/PPCFrameLowering.cpp
Commit a49a41e7855fad426abf6ee9b8b88a535e8d33cc by gabor.marton
[AST][NFC] Update outdated comments in ASTStructuralEquivalence.cpp
The file was modifiedclang/lib/AST/ASTStructuralEquivalence.cpp
Commit 175f6e309ab911d43ab21707587615341112f3b5 by sd.fertile
[PowerPC][NFC] Add a test for vrsave usage iinline asm.

Add a lit test that that uses vrsave register in the clobber list, and
tests the extended mnemonics mtvrsave and mfvrsave.
The file was addedllvm/test/CodeGen/PowerPC/vrsave-inline-asm.ll
Commit de8793b9184ece0d24f46bc2d86711092848f938 by pavel
[lldb/DWARF] Add support for type units in dwp files

all that was needed was to teach lldb's DWARF context about the
debug_tu_index section.
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/DWARFContext.cpp
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/DWARFContext.h
The file was addedlldb/test/Shell/SymbolFile/DWARF/dwp-debug-types.s
Commit f0c642e82274158f692d184de177be65eba814c1 by epastor
Remove unused functions in llvm-ml

On review, these functions will likely not be needed even in the final MasmParser.
The file was modifiedllvm/lib/MC/MCParser/MasmParser.cpp
Commit 5125803d344b848cdfc9441edfcc36dc8e488407 by alexandre.ganea
[mlir] Silence error: call to constructor of 'llvm::APInt' is ambiguous

I was getting this error when using Clang 9.0.1 for compiling.

F:\llvm-project\mlir\lib\IR\Builders.cpp(119,27): error: call to constructor of 'llvm::APInt' is ambiguous
                          APInt(32, value, /*isSigned=*/false));
                          ^     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
F:\llvm-project\llvm\include\llvm/ADT/APInt.h(277,3): note: candidate constructor
  APInt(unsigned numBits, uint64_t val, bool isSigned = false)
  ^
F:\llvm-project\llvm\include\llvm/ADT/APInt.h(304,3): note: candidate constructor
  APInt(unsigned numBits, unsigned numWords, const uint64_t bigVal[]);
  ^
1 error generated.
The file was modifiedmlir/lib/IR/Builders.cpp
Commit b64aa8c715112ac4b9fd1ae8eb5ecb981ecd091a by arsenm2
AMDGPU/GlobalISel: Fix constant bus violation with source modifiers

This looked through copies to find the source modifiers, which may
have been SGPR->VGPR copies added to avoid potential constant bus
violations. Re-insert a copy to a VGPR if this happens.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/constant-bus-restriction.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s32.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s64.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
Commit fab4cdea3911b19d1b1819102aee0252cbd4eba4 by arsenm2
AMDGPU/GlobalISel: Select llvm.amdgcn.fmul.legacy
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fmul.legacy.ll
Commit 79ff188addeeea127c7a7edd808c5821917d4bb6 by arsenm2
AMDGPU/GlobalISel: Legalize G_FPOW

There are few differences from the DAG handling. First, the DAG
handling uses a primitive selection pattern instead of custom
legalizing it. Because of this, this makes use of source modifiers
while the DAG does not.

Also instead of promoting f16, try to use the f16 log/exp. There's no
f16 fmul_legacy, so widen just for the multiply, although I'm not sure
that's the best solution.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
Commit ac7abe0ba9ae4c6a2248cc3ef4e4fe7e6d270105 by arsenm2
AMDGPU/GlobalISel: Manually select G_BUILD_VECTOR_TRUNC

We have patterns for s_pack* selection, but they assume the inputs are
a build_vector with 16-bit inputs, not a truncating build
vector. Since there's still outstanding work for how to handle
mismatched result and source element vector operations, and since I'm
trying a different packed vector strategy than SelectionDAG, just
manually select this for now.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir
Commit 83012cb217189bb6faa1256cc44fd0c306363264 by david.green
[ARM] Correct Formatting. NFC

Also removed an unnecessary TODO that I don't believe is relevant for
the instruction in question.
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
Commit 89dc8fe6222041319e073ceb8ee0cb38d045ea16 by arsenm2
AMDGPU/GlobalISel: Precommit xnor matching test
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll
Commit 6ed8e2014330b6a48d238cdc4357e788cdd6d445 by maskray
[ELF] Ignore the maximum of input section alignments for two cases

Follow-up for D74286.

Notations:

* alignExpr: the computed ALIGN value
* max_input_align: the maximum of input section alignments

This patch changes the following two cases to match GNU ld:

* When ALIGN is present, GNU ld sets output sh_addr to alignExpr, while lld use max(alignExpr, max_input_align)
* When addrExpr is specified but alignExpr is not, GNU ld sets output sh_addr to addrExpr, while lld uses `advance(0, max_input_align)`

Note, sh_addralign is still set to max(alignExpr, max_input_align).

lma-align.test is enhanced a bit to check we don't overalign sh_addr.

fixSectionAlignments() sets addrExpr but not alignExpr for the `!hasSectionsCommand` case.
This patch sets alignExpr as well so that max_input_align will be respected.

Reviewed By: grimar

Differential Revision: https://reviews.llvm.org/D74736
The file was modifiedlld/test/ELF/linkerscript/outsections-addr.s
The file was modifiedlld/ELF/Writer.cpp
The file was addedlld/test/ELF/linkerscript/section-align2.test
The file was modifiedlld/test/ELF/linkerscript/lma-align.test
The file was modifiedlld/ELF/LinkerScript.cpp
Commit de0dda54d38137d0714c279a540074fe73822b8b by maskray
[ELF] Warn changed output section address

When the output section address (addrExpr) is specified, GNU ld warns if
sh_addr is different. This patch implements the warning.

Note, LinkerScript::assignAddresses can be called more than once. We
need to record the changed section addresses, and only report the
warnings after the addresses are finalized.

Reviewed By: grimar

Differential Revision: https://reviews.llvm.org/D74741
The file was modifiedlld/ELF/LinkerScript.h
The file was modifiedlld/test/ELF/linkerscript/lma-align.test
The file was modifiedlld/test/ELF/linkerscript/section-align2.test
The file was modifiedlld/ELF/LinkerScript.cpp
The file was modifiedlld/ELF/Writer.cpp
Commit c47e0e2d37d32ec56c760f1a2c9740d69c370b57 by Jonas Devlieghere
[lldb-vscode] Use libOption with tablegen to parse command line options.

This change will bring lldb-vscode in line with how several other llvm
tools process command line arguments and make it easier to add future
options.

Differential revision: https://reviews.llvm.org/D74798
The file was addedlldb/tools/lldb-vscode/Options.td
The file was modifiedlldb/tools/lldb-vscode/lldb-vscode.cpp
The file was modifiedlldb/tools/lldb-vscode/CMakeLists.txt
The file was addedlldb/test/Shell/VSCode/TestOptions.test
The file was modifiedlldb/test/Shell/helper/toolchain.py
Commit dbd7281aa775a0e23c43a02583593900cd4c05be by maskray
[ELF] Shuffle .init_array/.fini_array with --shuffle-sections=

Useful for detecting static initialization order fiasco.

Reviewed By: grimar

Differential Revision: https://reviews.llvm.org/D74887
The file was addedlld/test/ELF/shuffle-sections-init-fini.s
The file was modifiedlld/ELF/Writer.cpp
Commit 42ec6fdce92090c02a10506fbdb2257fdbc2d1fd by llvm-dev
[TargetLowering] Apply basic shift combines before recursive SimplifyDemandedBits calls.

Minor refactor/cleanup before we begin adding non-uniform support.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Commit 043ed2e22ac442c2116f5df6367d3889ea0b9de1 by arsenm2
AMDGPU/GlobalISel: Fix xnor matching

We should try the generated matchers before the manual selection. This
means the patterns are now handling the common cases, but the manual
selection code is not yet dead. It's still handling the non-s32/s64
cases (like v2s16 and v2s32). Currently tablegen doesn't have a nice
way to have a single pattern that covers multiple types.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-or3.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
Commit 6a479220b5e8b25ec3ffe193c463cb3fdaac0e06 by arsenm2
AMDGPU/GlobalISel: Commit test changes I forgot to squash

These should have been in ac7abe0ba9ae4c6a2248cc3ef4e4fe7e6d270105
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir
Commit cab39e4b8c826ec5dfebe17a18137272022e64ac by jay.foad
GlobalISel: Fix narrowing of (G_ASHR i64:x, 32)

Reviewers: arsenm

Subscribers: jvesely, wdng, nhaehnle, rovka, hiraditya, volkan, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74950
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/combine-ashr-narrow.mir
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
Commit 9fff6e823cf79075d1f386e1e875b73405368620 by mcinally
[AArch64][SVE] Add +fullfp16 to sve-vector-splat.ll

Add +fullfp16 to sve-vector-splat.ll so we can test folding of immediates into moves.

This attribute can go away later when SVE has a full set of fp16 patterns in place.

Differential Revision: https://reviews.llvm.org/D74965
The file was modifiedllvm/test/CodeGen/AArch64/sve-vector-splat.ll
Commit 134bab7cd5679673d6807595ae77b5bc0c3b83c2 by flo
[DSE,MSSA] Add debug counter.

Can be used like
-debug-counter=dse-memoryssa-skip=10,dse-memoryssa-counter-count=20

Reviewers: dmgreen, rnk, efriedma, bryant, asbirlea

Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D72147
The file was modifiedllvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
The file was addedllvm/test/Transforms/DeadStoreElimination/MSSA/debug-counter.ll
Commit 23444edf30ba00ccefa3a582ac7ddc29774e9da5 by yitzhakm
[AST matchers] Add basic matchers for googletest EXPECT/ASSERT calls.

Summary:
This revision adds matchers that match calls to the gtest EXPECT and ASSERT
macros almost like function calls. The matchers are placed in separate files
(GtestMatchers...), because they are specific to the gtest library.

Reviewers: gribozavr2

Subscribers: mgorny, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D74840
The file was modifiedclang/lib/ASTMatchers/CMakeLists.txt
The file was addedclang/include/clang/ASTMatchers/GtestMatchers.h
The file was modifiedclang/unittests/ASTMatchers/CMakeLists.txt
The file was addedclang/lib/ASTMatchers/GtestMatchers.cpp
The file was addedclang/unittests/ASTMatchers/GtestMatchersTest.cpp
Commit fc4455891c00bfa16c85d0cebe6158fafe11667d by spatel
[VectorCombine] refactor matching code to reduce duplication; NFC

cmp/binop were already diverging even though they are largely
the same logic.
The file was modifiedllvm/lib/Transforms/Vectorize/VectorCombine.cpp
Commit db9c40f5624e6d55e0cbafe3f3980a7223e197c4 by danilo.carvalho.grael
[AArch64][SVE] Add intrinsics for SVE2 bitwise ternary operations

Summary:
Add intrinsics for the following operations:
- eor3, bcax
- bsl, bsl1n, bsl2n, nbsl

Fix MC tests for bsl instructions.

Reviewers: kmclaughlin, c-rhodes, sdesmalen, efriedma, rengolin

Reviewed By: efriedma

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74785
The file was modifiedllvm/test/MC/AArch64/SVE2/bsl-diagnostics.s
The file was modifiedllvm/test/MC/AArch64/SVE2/bsl2n-diagnostics.s
The file was modifiedllvm/include/llvm/IR/IntrinsicsAArch64.td
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
The file was modifiedllvm/test/MC/AArch64/SVE2/nbsl-diagnostics.s
The file was addedllvm/test/CodeGen/AArch64/sve2-bitwise-ternary.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was modifiedllvm/test/MC/AArch64/SVE2/bsl1n-diagnostics.s
Commit 60023e347116e5004295e8c7f2f09cc1855d4d84 by arsenm2
AMDGPU: Use default operand for VOP3P clamp

We don't use this, and matching from the def doesn't make much sense.

There are multiple tablegen bugs with default operand
handling. undef_tied_input should work to handle the vdst_in
correctly, but this breaks the operand register class constraint which
it should be able to infer.
The file was modifiedllvm/lib/Target/AMDGPU/VOP3Instructions.td
The file was modifiedllvm/lib/Target/AMDGPU/VOP3PInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.td
Commit 41bd9ead35f60823c59367efe4f3d5ade87e756d by paulsson
[SystemZ]  Return scalarized costs for vector instructions on older archs.

A cost query for a vector instruction should return a cost even without
target vector support, and not trigger an assert.

VectorCombine does this with an input containing source code vectors.

Review: Ulrich Weigand
The file was addedllvm/test/Analysis/CostModel/SystemZ/oldarch-vectors.ll
The file was modifiedllvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
Commit 8c70a2597f53457efc8eb2798c1d1056bb105ec3 by llvmgnsyncbot
[gn build] Port 23444edf30b
The file was modifiedllvm/utils/gn/secondary/clang/lib/ASTMatchers/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/clang/unittests/ASTMatchers/BUILD.gn
Commit a8db806d52ce02ddca179b811da164023316d4b9 by nikita.ppv
[SimplifyLibCalls][IRBuilder] Accept any IRBuilder in SimplifyLibCalls

This changes the SimplifyLibCalls utility to accept an IRBuilderBase,
which allows us to pass through the IRBuilder used by InstCombine.
This will ensure that new instructions get added to the worklist.
The annotated test-case drops from 4 to 2 InstCombine iterations thanks
to this.

To achieve this, I'm adding an IRBuilderBase::OperandBundlesGuard,
which is basically the same as the existing InsertPointGuard and
FastMathFlagsGuard, but for operand bundles. Also add a
setDefaultOperandBundles() method so these can be set outside the
constructor.

Differential Revision: https://reviews.llvm.org/D74792
The file was modifiedllvm/include/llvm/Transforms/Utils/SimplifyLibCalls.h
The file was modifiedllvm/test/Transforms/InstCombine/simplify-libcalls.ll
The file was modifiedllvm/include/llvm/IR/IRBuilder.h
The file was modifiedllvm/lib/CodeGen/CodeGenPrepare.cpp
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
The file was modifiedllvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
Commit c90ea87cfd71f8da05f2e684d3cf139f9773c15d by nikita.ppv
[X86] Fix SDLoc initialization

Fixes -Wparentheses warning, in this case indicating a genuine
bug.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 98f5268a7292c2996e2f718382e2d5404eb5d112 by flo
[VectorUtils] Move ToVectorTy to VectorUtils.h (NFC).

ToVectorTy is defined and used in multiple places. Hoist it to
VectorUtils.h to avoid duplication and improve re-usability.

Reviewers: rengolin, hsaito, Ayal, gilr, fpetrogalli

Reviewed By: fpetrogalli

Differential Revision: https://reviews.llvm.org/D74959
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was modifiedllvm/lib/Transforms/Utils/InjectTLIMappings.cpp
The file was modifiedllvm/include/llvm/Analysis/VectorUtils.h
Commit deb0a8bfc4923356beaa47b960d14b0c46a14721 by flo
[DSE,MSSA] Dbg counters required assertions. Mark test accordingly.
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/debug-counter.ll
Commit 656dff9af48bd242fc0f8a20cf50c6d0921df052 by nikita.ppv
[InstCombine] Use replaceOperand() in more places

Followup to D73919 with another batch of replacements of
setOperand() -> replaceOperand(), to make sure the old
operand gets DCEd right away.

Differential Revision: https://reviews.llvm.org/D74932
The file was modifiedllvm/lib/Transforms/InstCombine/InstructionCombining.cpp
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
Commit e4df934ca7b408cfb52531016198545a8d50f41a by maskray
[Clang interpreter] Rename Block.{h,cpp} to InterpBlock.{h,cpp}

The Blocks runtime provide a header named Block.h.
It is generally preferable to avoid name collision with system headers
(reducing reliance on -isystem order, more friendly when navigating files in
an editor, etc).

Reviewed By: gribozavr2

Differential Revision: https://reviews.llvm.org/D74934
The file was addedclang/lib/AST/Interp/InterpBlock.cpp
The file was removedclang/lib/AST/Interp/Block.h
The file was removedclang/lib/AST/Interp/Block.cpp
The file was modifiedclang/lib/AST/Interp/Pointer.cpp
The file was modifiedclang/lib/AST/Interp/Pointer.h
The file was addedclang/lib/AST/Interp/InterpBlock.h
The file was modifiedclang/lib/AST/CMakeLists.txt
The file was modifiedllvm/utils/gn/secondary/clang/lib/AST/BUILD.gn
Commit 0e3e242209c7f84009c9d88fe52982f8ba21c68b by yamauchi
[BFI] Fix missed BFI updates in MachineSink.

Summary:
This prevents BFI queries on new blocks (from
MachineSinking::GetAllSortedSuccessors) and fixes a bunch of assert failures
under -check-bfi-unknown-block-queries=true.

Reviewers: davidxl

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74511
The file was modifiedllvm/include/llvm/CodeGen/MachineBlockFrequencyInfo.h
The file was modifiedllvm/lib/CodeGen/MachineSink.cpp
The file was modifiedllvm/test/CodeGen/X86/machine-sink.ll
The file was modifiedllvm/lib/CodeGen/MachineBlockFrequencyInfo.cpp
Commit b178555318cdccecc9d3fb4af89b4a765cb0e48c by nikita.ppv
[InstCombine] Improve simplify demanded bits worklist management

This fixes a small mistake from D72944: The worklist add should
happen before assigning the new operand, not after.

In case an actual replacement happens, the old operand needs to
be added for DCE. If no actual replacement happens, then old/new
are the same, so it doesn't matter.

This drops one iteration from the annotated test case.
The file was modifiedllvm/test/Transforms/InstCombine/2010-11-01-lshr-mask.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
Commit 31ec721516b5ed36f7dbed180a903e269f29716d by francesco.petrogalli
[llvm][CodeGen] DAG Combiner folds for vscale.

Summary:
This patch simplifies the DAGs generated when using the intrinsic `@llvm.vscale.*` as follows:

* Fold (add (vscale * C0), (vscale * C1)) to (vscale * (C0 + C1)).
* Canonicalize (sub X, (vscale * C)) to (add X,  (vscale * -C)).
* Fold (mul (vscale * C0), C1) to (vscale * (C0 * C1)).
* Fold (shl (vscale * C0), C1) to (vscale * (C0 << C1)).

The test `sve-gep-ll` have been updated to reflect the folding introduced by this patch.

Reviewers: efriedma, sdesmalen, andwar, rengolin

Reviewed By: sdesmalen

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74782
The file was addedllvm/test/CodeGen/AArch64/sve-vscale-combine.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/test/CodeGen/AArch64/sve-gep.ll
Commit bc7b26c333f51b4b534abb81d597c0b86123718c by diego.caballero
[MLIR] Allow Loop dialect IfOp and ForOp to define values

This patch implements the RFCs proposed here:
https://llvm.discourse.group/t/rfc-modify-ifop-in-loop-dialect-to-yield-values/463
https://llvm.discourse.group/t/rfc-adding-operands-and-results-to-loop-for/459/19.

It introduces the following changes:
- All Loop Ops region, except for ReduceOp, terminate with a YieldOp.
- YieldOp can have variadice operands that is used to return values out of IfOp and ForOp regions.
- Change IfOp and ForOp syntax and representation to define values.
- Add unit-tests and update .td documentation.
- YieldOp is a terminator to loop.for/if/parallel
- YieldOp custom parser and printer

Lowering is not supported at the moment, and will be in a follow-up PR.

Thanks.

Reviewed By: bondhugula, nicolasvasilache, rriddle

Differential Revision: https://reviews.llvm.org/D74174
The file was modifiedmlir/lib/Conversion/AffineToStandard/AffineToStandard.cpp
The file was modifiedmlir/examples/toy/Ch7/mlir/LowerToLLVM.cpp
The file was modifiedmlir/test/Conversion/LoopsToGPU/parallel_loop.mlir
The file was modifiedmlir/include/mlir/Dialect/LoopOps/LoopOps.td
The file was modifiedmlir/test/Dialect/Loops/invalid.mlir
The file was modifiedmlir/test/Dialect/Linalg/parallel_loops.mlir
The file was modifiedmlir/lib/Conversion/GPUToSPIRV/ConvertGPUToSPIRV.cpp
The file was modifiedmlir/test/Dialect/Loops/ops.mlir
The file was modifiedmlir/test/Dialect/Loops/parallel-loop-fusion.mlir
The file was modifiedmlir/lib/Dialect/LoopOps/LoopOps.cpp
The file was modifiedmlir/include/mlir/IR/OpImplementation.h
The file was modifiedmlir/examples/toy/Ch6/mlir/LowerToLLVM.cpp
The file was modifiedmlir/lib/Parser/Parser.cpp
Commit 6b4a193defbe59b2b93e9d0289b2a7d9c2d842b9 by jasonliu
[XCOFF][AIX] Put undefined symbol name into StringTable when neccessary

Summary:
When we have a long name for the undefined symbol, we would hit this assertion:
Assertion failed: I != StringIndexMap.end() && "String is not in table!"
This patch addresses that.

Reviewed by: DiggerLin, daltenty

Differential Revision: https://reviews.llvm.org/D74924
The file was modifiedllvm/lib/MC/XCOFFObjectWriter.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/aix-undef-func-call.ll
Commit 2769fb90f0a4e6178306b521c5e79708b16de1fc by llvm-dev
[LoopVectorize][X86] Regenerate tests. NFCI.
The file was modifiedllvm/test/Transforms/LoopVectorize/X86/interleaving.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/X86/strided_load_cost.ll
Commit 1723f219939e1d4dc1c53ec7caf10c9380822b99 by llvm-dev
Fix MSVC "not all control paths return a value" warning. NFCI.
The file was modifiedclang/lib/ASTMatchers/GtestMatchers.cpp
Commit 72eef820d528ab93982e54cd49c44fabf20e83a5 by arsenm2
AMDGPU/GlobalISel: Select G_SHUFFLE_VECTOR

G_SHUFFLE_VECTOR is legal since it theoretically may help match op_sel
for VOP3P instructions. Expand it in some other way in case it doesn't
fold into the use instructions.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shuffle-vector.v2s16.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
Commit dfce5fd50a00110890ad95dacca75886c6fd456d by arsenm2
AMDGPU/GlobalISel: Select VOP3P instructions

This only handles the basic cases. More work is needed to make better
use of op_sel.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUGISel.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.v2s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.v2s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.v2s16.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.v2s16.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.v2s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.v2s16.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.v2s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.v2s16.mir
Commit 4c1c9422a3adab64433b8fde31f1ac346459b491 by arsenm2
AMDGPU/GlobalISel: Select llvm.amdgcn.fdot2

I'm slighly worried about the generated checks, since they won't catch
incorrect modifiers being added at the end of the line.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fdot2.ll
The file was modifiedllvm/lib/Target/AMDGPU/VOP3PInstructions.td
Commit db06870dbd5e85acbd39bb8dc3b2e1c751904f86 by arsenm2
AMDGPU: Move dot intrinsic patterns to instruction def

I tried to use some of the new tablegen features to avoid creating
different operand list permutations, but I still don't see a way to
programmatically build a source pattern dag.

Also add GlobalISel tests, which now all import successfully.

Some of the fneg fold tests are incorrect, which need to be fixed in a
future commit
The file was modifiedllvm/lib/Target/AMDGPU/VOP3PInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/VOP3Instructions.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot8.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot2.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot8.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot2.ll
Commit 07d2cdae11633139947f105888163adfd5646ce7 by nullptr
[lldb/cmake] Enable more verbose find_package output.

Summary:
The purpose of this patch is to make identifying missing dependencies clearer to the user.
`find_package` will report if a package is not found, that output, combined with the exiting
status message, is clearer than not having the additional verbosity.

If the SWIG dependency is required {LLDB_ENABLE_PYTHON, LLDB_ENABLE_LUA}
and SWIG is not available, fail the configuration step.  Terminate the
configure early rather than later with a clear error message.

We could possibly modify:
`llvm-project/lldb/cmake/modules/FindPythonInterpAndLibs.cmake`
However, the patch here seems clear in my opinion.

Reviewers: aadsm, hhb, JDevlieghere

Reviewed By: JDevlieghere

Subscribers: labath, jrm, mgorny, lldb-commits

Tags: #lldb

Differential Revision: https://reviews.llvm.org/D74917
The file was modifiedlldb/cmake/modules/FindPythonInterpAndLibs.cmake
The file was modifiedlldb/cmake/modules/FindLuaAndSwig.cmake
Commit 00955a62e4333c7ca889043d6a9033cb8cbf800d by arsenm2
AMDGPU/GlobalISel: Fix SALU mapping for v2s16 min/max

The legalizer helper functions are unusably awkward to perform the 3-5
part legalization. This needs to be widened, scalarized, lowered, and
we should avoid creating vector extends and truncates. Manually do all
of this and expand.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir
Commit 73d8d83a6d9adac3216ea8a39eb502b2a5c4d083 by maskray
[ARM] Change ARMAttributeParser::Parse to use support::endianness and simplify
The file was modifiedllvm/include/llvm/Support/ARMAttributeParser.h
The file was modifiedllvm/unittests/Support/ARMAttributeParser.cpp
The file was modifiedlld/ELF/InputFiles.cpp
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp
The file was modifiedllvm/include/llvm/Object/ELFObjectFile.h
The file was modifiedllvm/lib/Support/ARMAttributeParser.cpp
Commit 7dd6a862e5ece866c787d4509a5a5cad19531fbc by Louis Dionne
[libc++] Do not set the `availability=XXX` feature when not testing against a system libc++

Otherwise, the `availability=XXX` lit feature is set even when we're
testing trunk and _LIBCPP_DISABLE_AVAILABILITY is defined, which causes
tests that check for availability markup to be enabled and unexpectedly
pass.
The file was modifiedlibcxx/utils/libcxx/test/config.py
Commit 266959c0f72ff359a60fe43da0cf336604611029 by mcinally
[AArch64][SVE] Add backend support for splats of immediates

This patch adds backend support for splats of both Int and FP immediates.

Differential Revision: https://reviews.llvm.org/D74856
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was modifiedllvm/test/CodeGen/AArch64/sve-vector-splat.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
Commit 0781e93a6eaa71ec5d87be3bbeeeed053067f7ee by luismarques
[CodeGen][RISCV] Fix clang/test/CodeGen/atomic_ops.c for RISC-V

By default the RISC-V target doesn't have the atomics standard extension
enabled. The first RUN line in `clang/test/CodeGen/atomic_ops.c` didn't
specify a target triple, which meant that on RISC-V Linux hosts it would
target RISC-V, but because it used clang cc1 we didn't get the toolchain
driver functionality to automatically turn on the extensions implied by
the target triple (riscv64-linux includes atomics). This would cause the
test to fail on RISC-V hosts.

This patch changes the test to have RUN lines for two explicit targets,
one with native atomics and one without. To work around FileCheck
limitations and more accurately match the output, some tests now have
separate prefixes for the two cases.

Reviewers: jyknight, eli.friedman, lenary, efriedma
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D74847
The file was modifiedclang/test/CodeGen/atomic_ops.c
Commit 29ad9d6b26ee92c7843c06392625d894d58658c2 by hanchung
[mlir][spirv] Add lowering for load/store zero-rank memref from std to SPIR-V.

Differential Revision: https://reviews.llvm.org/D74874
The file was modifiedmlir/test/Conversion/StandardToSPIRV/std-to-spirv.mlir
The file was modifiedmlir/lib/Dialect/SPIRV/SPIRVLowering.cpp
The file was modifiedmlir/test/Dialect/SPIRV/Serialization/memory-ops.mlir
Commit 042d97eda9fabbf7718e32fc5efe9150c7d8bfa9 by diego.caballero
[MLIR] Remove constexpr from LoopOps.td

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D74978
The file was modifiedmlir/include/mlir/Dialect/LoopOps/LoopOps.td
Commit d2b7c09e79a12cb61fc424429b348b2c04364d07 by kparzysz
[Hexagon] Simplify intrinsic (vandvrt (vandqrt q b) m) -> q if possible

When each byte in b&m is non-zero, this conversion Q->V->Q is a no-op.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
The file was addedllvm/test/Transforms/InstCombine/Hexagon/simplify-hvx-qvq.ll
The file was addedllvm/test/Transforms/InstCombine/Hexagon/lit.local.cfg
Commit 69d757c0e8ffc5b49fda10df38e470a56d616ef4 by riddleriver
Move StandardOps/Ops.h to StandardOps/IR/Ops.h

Summary:
NFC - Moved StandardOps/Ops.h to a StandardOps/IR dir to better match surrounding
directories. This is to match other dialects, and prepare for moving StandardOps
related transforms in out for Transforms and into StandardOps/Transforms.

Differential Revision: https://reviews.llvm.org/D74940
The file was modifiedmlir/include/mlir/Dialect/Linalg/Utils/Utils.h
The file was modifiedmlir/lib/Transforms/PipelineDataTransfer.cpp
The file was modifiedmlir/include/mlir/Dialect/StandardOps/CMakeLists.txt
The file was modifiedmlir/examples/toy/Ch6/mlir/LowerToAffineLoops.cpp
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
The file was modifiedmlir/lib/Conversion/GPUCommon/OpToFuncCallLowering.h
The file was modifiedmlir/lib/Dialect/VectorOps/VectorOps.cpp
The file was modifiedmlir/lib/Conversion/StandardToSPIRV/ConvertStandardToSPIRV.cpp
The file was modifiedmlir/lib/Conversion/AffineToStandard/AffineToStandard.cpp
The file was modifiedmlir/lib/Conversion/StandardToSPIRV/StandardToSPIRV.td
The file was modifiedmlir/lib/Transforms/MemRefDataFlowOpt.cpp
The file was addedmlir/include/mlir/Dialect/StandardOps/IR/Ops.h
The file was addedmlir/include/mlir/Dialect/StandardOps/IR/CMakeLists.txt
The file was modifiedmlir/lib/Analysis/AffineStructures.cpp
The file was modifiedmlir/lib/Conversion/LoopsToGPU/LoopsToGPUPass.cpp
The file was modifiedmlir/lib/Conversion/LinalgToSPIRV/LinalgToSPIRV.cpp
The file was modifiedmlir/lib/Transforms/AffineLoopInvariantCodeMotion.cpp
The file was modifiedmlir/lib/Dialect/StandardOps/CMakeLists.txt
The file was modifiedmlir/lib/Dialect/VectorOps/VectorTransforms.cpp
The file was modifiedmlir/lib/Transforms/Utils/Utils.cpp
The file was modifiedmlir/include/mlir/InitAllDialects.h
The file was modifiedmlir/lib/Dialect/Linalg/Analysis/DependenceAnalysis.cpp
The file was modifiedmlir/lib/Dialect/FxpMathOps/Transforms/LowerUniformRealMath.cpp
The file was addedmlir/lib/Dialect/StandardOps/IR/Ops.cpp
The file was modifiedmlir/test/lib/Transforms/TestConstantFold.cpp
The file was modifiedmlir/test/lib/Transforms/TestMemRefDependenceCheck.cpp
The file was modifiedmlir/lib/Conversion/LoopToStandard/ConvertLoopToStandard.cpp
The file was modifiedmlir/lib/Dialect/VectorOps/VectorUtils.cpp
The file was modifiedmlir/examples/toy/Ch6/mlir/LowerToLLVM.cpp
The file was modifiedmlir/test/lib/Transforms/TestOpaqueLoc.cpp
The file was modifiedmlir/examples/toy/Ch7/mlir/LowerToLLVM.cpp
The file was modifiedmlir/lib/Dialect/QuantOps/Transforms/ConvertConst.cpp
The file was removedmlir/lib/Dialect/StandardOps/Ops.cpp
The file was modifiedmlir/examples/toy/Ch7/mlir/LowerToAffineLoops.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/EDSC/Builders.h
The file was modifiedmlir/lib/Dialect/Linalg/Utils/Utils.cpp
The file was modifiedmlir/lib/Transforms/LoopFusion.cpp
The file was modifiedmlir/include/mlir/Dialect/StandardOps/EDSC/Builders.h
The file was modifiedmlir/lib/Analysis/NestedMatcher.cpp
The file was modifiedmlir/lib/Dialect/GPU/Transforms/KernelOutlining.cpp
The file was modifiedmlir/lib/Dialect/LoopOps/LoopOps.cpp
The file was modifiedmlir/lib/Transforms/LoopCoalescing.cpp
The file was modifiedmlir/lib/Conversion/LoopsToGPU/LoopsToGPU.cpp
The file was modifiedmlir/test/lib/Transforms/TestInlining.cpp
The file was modifiedmlir/lib/Conversion/StandardToSPIRV/LegalizeStandardForSPIRV.cpp
The file was modifiedmlir/lib/Dialect/LoopOps/Transforms/ParallelLoopFusion.cpp
The file was modifiedmlir/lib/Dialect/AffineOps/AffineOps.cpp
The file was modifiedmlir/test/lib/Transforms/TestLoopFusion.cpp
The file was modifiedmlir/lib/Analysis/AffineAnalysis.cpp
The file was addedmlir/include/mlir/Dialect/StandardOps/IR/Ops.td
The file was modifiedmlir/lib/Quantizer/Configurations/FxpMathConfig.cpp
The file was modifiedmlir/lib/Dialect/GPU/IR/GPUDialect.cpp
The file was modifiedmlir/lib/Transforms/Vectorize.cpp
The file was modifiedmlir/lib/Transforms/Utils/FoldUtils.cpp
The file was modifiedmlir/test/lib/Transforms/TestMemRefBoundCheck.cpp
The file was modifiedmlir/lib/Dialect/GPU/Transforms/AllReduceLowering.cpp
The file was modifiedmlir/test/lib/Transforms/TestVectorTransforms.cpp
The file was removedmlir/include/mlir/Dialect/StandardOps/Ops.td
The file was modifiedmlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
The file was modifiedmlir/lib/Conversion/StandardToLLVM/ConvertStandardToLLVM.cpp
The file was modifiedmlir/test/lib/DeclarativeTransforms/TestVectorTransformPatterns.td
The file was modifiedmlir/examples/toy/Ch5/mlir/LowerToAffineLoops.cpp
The file was removedmlir/include/mlir/Dialect/StandardOps/Ops.h
The file was modifiedmlir/lib/Analysis/Utils.cpp
The file was modifiedmlir/test/lib/IR/TestMatchers.cpp
The file was modifiedmlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp
The file was modifiedmlir/lib/Transforms/Utils/LoopFusionUtils.cpp
The file was modifiedmlir/test/lib/Transforms/TestMemRefStrideCalculation.cpp
The file was modifiedmlir/lib/Conversion/GPUToVulkan/ConvertLaunchFuncToVulkanCalls.cpp
The file was modifiedmlir/include/mlir/Transforms/Utils.h
Commit e2ed1d14d6c2d11d1a5df23bd679bcb7e6cbf433 by francesco.petrogalli
[llvm][aarch64] SVE addressing modes.

Summary:
Added register + immediate and register + register addressing modes for the following intrinsics:

1. Masked load and stores:
     * Sign and zero extended load and truncated stores.
     * No extension or truncation.
2. Masked non-temporal load and store.

Reviewers: andwar, efriedma

Subscribers: cameron.mcinally, sdesmalen, tschuett, kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74254
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
The file was addedllvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll
The file was addedllvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was addedllvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-reg.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
The file was addedllvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-reg.ll
Commit 34e3485560cbe8b0e843a1a9ef0cf796e6a4e237 by spatel
[VectorCombine] refactor cost calcs to reduce duplication; NFC

More cleanup is possible now, but we probably need to
resolve the TODO about the existing difference between
compares and binops.
The file was modifiedllvm/lib/Transforms/Vectorize/VectorCombine.cpp
Commit 33bf1196475cbc9b84914c41308cf252764803ee by francesco.petrogalli
[llvm][CodeGen][aarch64] Add contiguous prefetch intrinsics for SVE.

Summary: The patch covers both register/register and register/immediate addressing modes.

Reviewers: efriedma, andwar, sdesmalen

Reviewed By: sdesmalen

Subscribers: sdesmalen, tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74581
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
The file was modifiedllvm/include/llvm/IR/IntrinsicsAArch64.td
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was addedllvm/test/CodeGen/AArch64/sve-intrinsics-contiguous-prefetches.ll
Commit 446b150065c331daa82a9f5436f4987e340e5d6f by rnk
[IR] Update BasicBlock::validateInstrOrdering comments, NFC

Pointed out by Jay Foad.
The file was modifiedllvm/lib/IR/BasicBlock.cpp
The file was modifiedllvm/include/llvm/IR/BasicBlock.h
Commit 8875ee18d72b1b395331c1b7217d2b91fb4dc4b7 by craig.topper
[X86] Add a new format type for instructions that represent named prefix bytes like data16 and rep. Use it to make a simpler version of isPrefix.

isPrefix was added to support the patches to align branches.
it relies on a switch over instruction names.

This moves those opcodes to a new format so the information is
tablegen and we can just check for a specific value in some bits
in TSFlags instead.

I've left the other function in place for now so that the
existing patches in phabricator will still work. I'll work with
the owner to get them migrated.
The file was modifiedllvm/lib/Target/X86/X86InstrFormats.td
The file was modifiedllvm/lib/Target/X86/X86InstrTSX.td
The file was modifiedllvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
The file was modifiedllvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
The file was modifiedllvm/tools/llvm-exegesis/lib/X86/Target.cpp
The file was modifiedllvm/lib/Target/X86/X86InstrSystem.td
The file was modifiedllvm/utils/TableGen/X86RecognizableInstr.h
The file was modifiedllvm/lib/Target/X86/X86InstrInfo.td
The file was modifiedllvm/utils/TableGen/X86RecognizableInstr.cpp
Commit 1874dee5662603c9251228c71b66de72cec0c979 by francisvm
[macho][NFC] Extract all CPU_(SUB_)TYPE logic to BinaryFormat

This moves all the logic of converting LLVM Triples to
MachO::CPU_(SUB_)TYPE from the specific target (Target)AsmBackend to
more convenient functions in lib/BinaryFormat.

This also gets rid of the separate two X86AsmBackend classes.

The previous attempt was to add it to libObject, but that adds an
unnecessary dependency to libObject from all the targets.

Differential Revision: https://reviews.llvm.org/D74808
The file was modifiedllvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
The file was modifiedllvm/include/llvm/BinaryFormat/MachO.h
The file was modifiedllvm/lib/BinaryFormat/CMakeLists.txt
The file was modifiedllvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
The file was modifiedllvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
The file was modifiedllvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h
The file was addedllvm/lib/BinaryFormat/MachO.cpp
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64MachObjectWriter.cpp
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
Commit 0bb90628b5f7c170689d2d3f019af773772fc649 by hhb
Allow customized relative PYTHONHOME

Summary:
This change allows a hard coded relative PYTHONHOME setting. So that
python can easily be packaged together with lldb.

The change includes:
1. Extend LLDB_RELOCATABLE_PYTHON to all platforms. It defaults to ON
for platforms other than Windows, to keep the behavior compatible.
2. Allows to customize LLDB_PYTHON_HOME. But still defaults to
PYTHON_HOME.
3. LLDB_PYTHON_HOME can be a path relative to liblldb. If it is
relative, we will resolve it before send it to Py_DecodeLocale.

Subscribers: mgorny, lldb-commits

Tags: #lldb

Differential Revision: https://reviews.llvm.org/D74727
The file was modifiedlldb/include/lldb/Host/Config.h.cmake
The file was modifiedlldb/cmake/modules/LLDBConfig.cmake
The file was modifiedlldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
Commit 8fa776b8ed02f36e6bc072c6748725890dfadcbe by llvmgnsyncbot
[gn build] Port 1874dee5662
The file was modifiedllvm/utils/gn/secondary/llvm/lib/BinaryFormat/BUILD.gn
Commit e9c79a7aef19b14e68ed50eb9382856e9453c5a0 by spatel
[VectorCombine] refactor to reduce duplicated code; NFC

This should be the last step in the current cleanup.
Follow-ups should resolve the TODO about cost calc
and enable the more general case where we extract
different elements.
The file was modifiedllvm/lib/Transforms/Vectorize/VectorCombine.cpp
Commit b72f1448ce42f4e38f0c2a33418089f2320ab8f3 by jay.foad
AMDGPU/GlobalISel: Better code for one case of G_SHUFFLE_VECTOR on v2i16

Reviewers: arsenm

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74987
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shuffle-vector.v2s16.mir
Commit a5b22b768f5a6f34c8f41eea6a32880794c1690b by mcinally
[AArch64][SVE] Add support for DestructiveBinary and DestructiveBinaryComm DestructiveInstTypes

Add support for DestructiveBinaryComm DestructiveInstType, as well as the lowering code to expand the new Pseudos into the final movprfx+instruction pairs.

Differential Revision: https://reviews.llvm.org/D73711
The file was modifiedllvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.h
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrFormats.td
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetMachine.cpp
The file was addedllvm/test/CodeGen/AArch64/sve-intrinsics-fp-arith-merging.ll
The file was modifiedllvm/test/CodeGen/AArch64/O0-pipeline.ll
The file was modifiedllvm/test/CodeGen/AArch64/O3-pipeline.ll
Commit dc046c70de96784772050e2704141c9e2a478220 by alexshap
[llvm-objcopy][MachO] Change the storage of sections

In this diff we change the storage of a section to unique_ptr.
This refactoring was factored out from D71647.

Test plan: make check-all

Differential revision: https://reviews.llvm.org/D74946
The file was modifiedllvm/tools/llvm-objcopy/MachO/MachOWriter.cpp
The file was modifiedllvm/tools/llvm-objcopy/MachO/Object.cpp
The file was modifiedllvm/tools/llvm-objcopy/MachO/MachOObjcopy.cpp
The file was modifiedllvm/tools/llvm-objcopy/MachO/MachOLayoutBuilder.cpp
The file was modifiedllvm/tools/llvm-objcopy/MachO/MachOReader.cpp
The file was modifiedllvm/tools/llvm-objcopy/MachO/Object.h
Commit 1f04d1b7069bf6c513526f36b8c7327c8dec6604 by medismail.bennani
[lldb/test] Move `platform process list` tests to its own directory (NFC)

Since the `platform process` commamnd has more tests now, this commits
separates each of the `platform process` subcommand's test in its own directory.

Differential Revision: https://reviews.llvm.org/D74836

Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
The file was addedlldb/test/API/commands/platform/process/list/main.cpp
The file was removedlldb/test/API/commands/platform/process/main.cpp
The file was addedlldb/test/API/commands/platform/process/list/Makefile
The file was removedlldb/test/API/commands/platform/process/TestProcessList.py
The file was removedlldb/test/API/commands/platform/process/Makefile
The file was addedlldb/test/API/commands/platform/process/list/TestProcessList.py
Commit d7c403e64043281b9c5883e3e034da5ebaf4985a by medismail.bennani
[lldb/Plugins] Add ability to fetch crash information on crashed processes

Currently, in macOS, when a process crashes, lldb halts inside the
implementation disassembly without yielding any useful information.
The only way to get more information is to detach from the process, then wait
for ReportCrash to generate a report, find the report, then see what error
message was included in it. Instead of waiting for this to happen, lldb could
locate the error_string and make it available to the user.

This patch addresses this issue by enabling the user to fetch extended
crash information for crashed processes using `process status --verbose`.

Depending on the platform, this will try to gather different crash information
into an structured data dictionnary. This dictionnary is generic and extensible,
as it contains an array for each different type of crash information.

On Darwin Platforms, lldb will iterate over each of the target's images,
extract their `__crash_info` section and generated a StructuredData::Array
containing, in each entry, the module spec, its UUID, the crash messages
and the abort cause. The array will be inserted into the platform's
`m_extended_crash_info` dictionnary and `FetchExtendedCrashInformation` will
return its JSON representation like this:

```
{
  "crash-info annotations": [
    {
      "abort-cause": 0,
      "image": "/usr/lib/system/libsystem_malloc.dylib",
      "message": "main(76483,0x1000cedc0) malloc: *** error for object 0x1003040a0: pointer being freed was not allocated",
      "message2": "",
      "uuid": "5747D0C9-900D-3306-8D70-1E2EA4B7E821"
    },
    ...
  ],
  ...
}
```

This crash information can also be fetched using the SB API or lldb-rpc protocol
using SBTarget::GetExtendedCrashInformation().

rdar://37736535

Differential Revision: https://reviews.llvm.org/D74657

Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
The file was modifiedlldb/source/Plugins/Platform/MacOSX/PlatformDarwin.cpp
The file was modifiedlldb/include/lldb/Target/Platform.h
The file was modifiedlldb/include/lldb/Target/Process.h
The file was modifiedlldb/include/lldb/API/SBTarget.h
The file was modifiedlldb/bindings/interface/SBTarget.i
The file was modifiedlldb/source/API/SBTarget.cpp
The file was addedlldb/test/API/functionalities/process_crash_info/main.c
The file was modifiedlldb/source/Commands/Options.td
The file was modifiedlldb/source/Plugins/Platform/MacOSX/PlatformDarwin.h
The file was addedlldb/test/API/functionalities/process_crash_info/Makefile
The file was addedlldb/test/API/functionalities/process_crash_info/TestProcessCrashInfo.py
The file was modifiedlldb/source/Commands/CommandObjectProcess.cpp
Commit 5c33a81b7a46373aa695ab676bec8b70b1abd0e2 by maskray
[AArch64][SVE] Fix -Wimplicit-fallthrough after D73711
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
Commit a6c8698924d2b31a2f096e0f4c06a7015ecccb5e by vsapsai
clang/Modules: Finish renaming CompilerInstance::ModuleManager, NFC.

Follow-up to 20d51b2f14ac4488f684f8fc57cb0ba718a6b91d, rename the setter to
make it consistent with the getter. Also fixed a few comments along the
way, didn't try to find all references to a module manager.

Reviewed By: dexonsmith

Differential Revision: https://reviews.llvm.org/D74939
The file was modifiedclang/lib/Frontend/CompilerInstance.cpp
The file was modifiedclang/lib/Frontend/ChainedIncludesSource.cpp
The file was modifiedclang/lib/Frontend/FrontendAction.cpp
The file was modifiedclang/include/clang/Frontend/CompilerInstance.h
Commit 0ad6fc9928d8a5e3bd148a112d6e772248e515ae by spatel
[SelectionDAG] remove unused isFast() helper function; NFC

We want flag users to check individual fast-math flags,
not that all of them are set. This was also probably
not working as intended because NoFPExcept isn't always
set on non-strict nodes.
The file was modifiedllvm/include/llvm/CodeGen/SelectionDAGNodes.h
Commit fad1c750f16c5f7a7ef8ec7d78ae1df4bc473c4a by maskray
[AArch64][SVE] Fix -DBUILD_SHARED_LIBS=on builds after -D74808/1874dee5662603c9251228c71b66de72cec0c979
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/LLVMBuild.txt
The file was modifiedllvm/lib/Target/ARM/MCTargetDesc/LLVMBuild.txt
The file was modifiedllvm/lib/Target/PowerPC/MCTargetDesc/LLVMBuild.txt
The file was modifiedllvm/lib/Target/X86/MCTargetDesc/LLVMBuild.txt
Commit fddbff147357a7f5618fb6166b716ad60c3eb9fc by maskray
[AArch64] Delete an unneeded dependency on Object after 1874dee5662603c9251228c71b66de72cec0c979

1874dee5662603c9251228c71b66de72cec0c979 moved CPU_(SUB_)TYPE logic to
BinaryFormat. Object is not directly referenced.
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/LLVMBuild.txt
Commit d37cbda5f9a47a4206439632ef4fa1534e66f856 by sidneym
[Hexagon] Define __ELF__ by default.

Differential Revision: https://reviews.llvm.org/D74972
The file was modifiedclang/lib/Basic/Targets/Hexagon.cpp
The file was modifiedclang/test/Preprocessor/hexagon-predefines.c
The file was modifiedcompiler-rt/lib/builtins/CMakeLists.txt
Commit 0a70edd696264ba69914f4d4ecb28d559cbe5444 by whitneyt
[CloneFunction] Update loop headers after cloning all blocks in loop.

Summary:
Blocks in a loop can be in any order as long as the loop header is the
first block in Blocks.
With some order of Blocks, cloneLoopWithPreheader would trigger the
assertion in addBasicBlockToLoop.

Example:

define void @test(i64 %N) {
preheader.i:
  br label %header.i

header.i:
  %i = phi i64 [ 0, %preheader.i ], [ %inc.i, %latch.i ]
  br label %header.j

header.j:
  %j = phi i64 [ 0, %header.i ], [ %inc.j, %latch.j ]
  br label %header.k

header.k:
  %k = phi i64 [ 0, %header.j ], [ %inc.k, %latch.k ]
  call void @baz(i64 %i, i64 %j, i64 %k)
  br label %latch.k

latch.k:
  %inc.k = add nsw i64 %k, 1
  %cmp.k = icmp slt i64 %inc.k, %N
  br i1 %cmp.k, label %header.k, label %latch.j

latch.j:
  %inc.j = add nsw i64 %j, 1
  %cmp.j = icmp slt i64 %inc.j, %N
  br i1 %cmp.j, label %header.j, label %latch.i

latch.i:
  %inc.i = add nsw i64 %i, 1
  %cmp.i = icmp slt i64 %inc.i, %N
  br i1 %cmp.i, label %header.i, label %exit.i

exit.i:
  ret void
}
declare void @baz(i64, i64, i64)
If the blocks of loop-i is in the order: header.i, latch.k, header.k,
header.j, latch.j, latch.i,
then cloneLoopWithPreheader would trigger the assertion in
addBasicBlockToLoop
assert(contains(SameHeader) && getHeader() == SameHeader->getHeader() &&
"Incorrect LI specified for this loop!");

As latch.k is in both loop-j and loop-k, it would be set as the header
of both loops after adding latch.k.
If we update loop headers during cloning blocks, then after adding
header.k,
the header of loop-k would be updated with header.k,
while the header of loop-j stays as latch.k.

When adding header.j, SameHeader is loop-k, SameHeader->getHeader() is
header.k, but getHeader() is latch.k, which trigger the assertion.
Reviewer: jdoerfert, Meinersbur, fhahn, kbarton, hfinkel, bmahjour,
etiotto
Reviewed By: Meinersbur
Subscribers: hiraditya, llvm-commits
Tag: LLVM
Differential Revision: https://reviews.llvm.org/D74382
The file was modifiedllvm/lib/Transforms/Utils/CloneFunction.cpp
Commit 9708279c725a515c69c41130aaaa36dc6a0b34d8 by johannes
[Attributor][FIX] Undo 16188f9 until SCC iterator bug is fixed

The buildbot
  http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win
shows some strange SCC iterator bug since 16188f9 which we need to
investigate. This patch should remove the part of 16188f9 that could
have exposed the problem.
The file was modifiedllvm/lib/Transforms/IPO/Attributor.cpp
Commit 618dec2aeffd9d7778b581176e0897b10731e273 by qcolombet
[GISel][KnownBits] Add a cache mechanism to speed compile time

This patch adds a cache that is valid only for the duration of a call
to getKnownBits. With such short lived cache we avoid all the problems
of cache invalidation while still getting the benefits of reusing
the information we already computed.

This cache is useful whenever an instruction occurs more than once
in a chain of computation.
E.g.,
v0 = G_ADD v1, v2
v3 = G_ADD v0, v1

Previously we would compute the known bits for:
v1, v2, v0, then v1 again and finally v3.

With the patch, now we won't have to recompute v1 again.

NFC
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/GISelKnownBits.h
The file was modifiedllvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
Commit 528a6a1d4cceda58d57c28a75a524dcdd8d35f3e by johannes
[Attributor][FIX] Disable a test to unblock the builders

To unblock the builders this disables a test for which the CHECK lines
need to be updated. The patch causing the failure was not reverted
because it is needed for a different problem we are investigating. Here
we just need to update the CHECK lines which will happen in the
meantime.
The file was modifiedllvm/test/Transforms/Attributor/liveness.ll
Commit a32d539798e4f0b97420e7b60b223b3a3fae5ff1 by francisvm
[Target] Remove libObject dependency in lib/Target

This removes a couple useless includes and the dependency of X86Desc on Object,
which was useless as well.
The file was modifiedllvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
The file was modifiedllvm/lib/Target/X86/MCTargetDesc/LLVMBuild.txt
The file was modifiedllvm/lib/Target/VE/MCTargetDesc/VEMCExpr.cpp
Commit 215a31115f89c851331a822e67aa4528ba5c21e6 by stilis
Revert "Allow customized relative PYTHONHOME"

This reverts commit 0bb90628b5f7c170689d2d3f019af773772fc649 since it is causing failures on the Windows LLDB buildbot:

http://lab.llvm.org:8011/builders/lldb-x64-windows-ninja/builds/14048
The file was modifiedlldb/include/lldb/Host/Config.h.cmake
The file was modifiedlldb/cmake/modules/LLDBConfig.cmake
The file was modifiedlldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
Commit 393f4e8ac263d0debecb571bbab69bcf31474cdb by llvm-project
[Analysis][Docs] Parents of loops documentation.

Recently I had to use it and although one assumes it returns null if
there's no parent loop, I think it helps to doc it.

Reviewed By: Meinersbur

Differential Revision: https://reviews.llvm.org/D74890
The file was modifiedllvm/include/llvm/Analysis/LoopInfo.h
The file was modifiedllvm/docs/LoopTerminology.rst
Commit 26222db01b079023d0fe3bb60f2c1b38f4f19d5a by riddleriver
[mlir][DeclarativeParser] Add support for the TypesMatchWith trait.

This allows for injecting type constraints that are not direct 1-1 mappings, for example when one type is equal to the element type of another. This allows for moving over several more parsers to the declarative form.

Differential Revision: https://reviews.llvm.org/D74648
The file was modifiedmlir/tools/mlir-tblgen/OpFormatGen.cpp
The file was modifiedmlir/lib/Dialect/StandardOps/IR/Ops.cpp
The file was modifiedmlir/include/mlir/IR/OperationSupport.h
The file was modifiedmlir/lib/Dialect/VectorOps/VectorOps.cpp
The file was modifiedmlir/test/IR/invalid-ops.mlir
The file was modifiedmlir/include/mlir/IR/OpImplementation.h
The file was modifiedmlir/include/mlir/Dialect/VectorOps/VectorOps.td
The file was modifiedmlir/include/mlir/Dialect/StandardOps/IR/Ops.td
Commit 2d0477a003687588886ae6e9b59b9355f8bb6b8c by riddleriver
[mlir][DeclarativeParser] Add basic support for optional groups in the assembly format.

When operations have optional attributes, or optional operands(i.e. empty variadic operands), the assembly format often has an optional section to represent these arguments. This revision adds basic support for defining an "optional group" in the assembly format to support this. An optional group is defined by wrapping a set of elements in `()` followed by `?` and requires the following:

* The first element of the group must be either a literal or an operand argument.
  - This is because the first element must be optionally parsable.
* There must be exactly one argument variable within the group that is marked as the anchor of the group. The anchor is the element whose presence controls whether the group should be printed/parsed. An element is marked as the anchor by adding a trailing `^`.
* The group must only contain literals, variables, and type directives.
  - Any attribute variables may be used, but only optional attributes can be marked as the anchor.
  - Only variadic, i.e. optional, operand arguments can be used.
  - The elements of a type directive must be defined within the same optional group.

An example of this can be seen with the assembly format for ReturnOp, which has a variadic number of operands.

```
def ReturnOp : ... {
  let arguments = (ins Variadic<AnyType>:$operands);

  // We only print the operands+types if there are a non-zero number
  // of operands.
  let assemblyFormat = "attr-dict ($operands^ `:` type($operands))?";
}
```

Differential Revision: https://reviews.llvm.org/D74681
The file was modifiedmlir/include/mlir/Dialect/StandardOps/IR/Ops.td
The file was modifiedmlir/docs/OpDefinitions.md
The file was modifiedmlir/lib/Dialect/StandardOps/IR/Ops.cpp
The file was modifiedmlir/tools/mlir-tblgen/OpFormatGen.cpp
The file was modifiedmlir/test/mlir-tblgen/op-format-spec.td
Commit ca4ea51c0af2dd3f3c73adc587c8e642c9dcdeec by riddleriver
[mlir][DeclarativeParser] Add an 'attr-dict-with-keyword' directive

This matches the '(print|parse)OptionalAttrDictWithKeyword' functionality provided by the assembly parser/printer.

Differential Revision: https://reviews.llvm.org/D74682
The file was modifiedmlir/docs/OpDefinitions.md
The file was modifiedmlir/test/lib/TestDialect/TestOps.td
The file was modifiedmlir/test/mlir-tblgen/op-format.mlir
The file was modifiedmlir/tools/mlir-tblgen/OpFormatGen.cpp
The file was modifiedmlir/test/mlir-tblgen/op-format-spec.td
Commit 93813e5feb18ece7becd1eece24d0138c955fd53 by riddleriver
[mlir] Add a utility iterator range that repeats a given value `n` times.

This range is useful when an desired API expects a range or when comparing two different ranges for equality, but the underlying data is a splat. This range removes the need to explicitly construct a vector in those cases.

Differential Revision: https://reviews.llvm.org/D74683
The file was modifiedmlir/include/mlir/Support/STLExtras.h
Commit b1de971ba8c83c82ef63077b666aaff3ba8e56b9 by riddleriver
[mlir][ODS] Add support for specifying the successors of an operation.

This revision add support in ODS for specifying the successors of an operation. Successors are specified via the `successors` list:
```
let successors = (successor AnySuccessor:$target, AnySuccessor:$otherTarget);
```

Differential Revision: https://reviews.llvm.org/D74783
The file was modifiedmlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
The file was modifiedmlir/include/mlir/TableGen/Constraint.h
The file was modifiedmlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
The file was modifiedmlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
The file was modifiedmlir/include/mlir/Dialect/StandardOps/IR/Ops.td
The file was modifiedmlir/include/mlir/Dialect/SPIRV/SPIRVControlFlowOps.td
The file was modifiedmlir/include/mlir/IR/OpBase.td
The file was modifiedmlir/docs/OpDefinitions.md
The file was modifiedmlir/lib/TableGen/Operator.cpp
The file was modifiedmlir/test/lib/TestDialect/TestOps.td
The file was modifiedmlir/lib/Dialect/SPIRV/SPIRVOps.cpp
The file was addedmlir/lib/TableGen/Successor.cpp
The file was modifiedmlir/lib/TableGen/CMakeLists.txt
The file was modifiedmlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
The file was modifiedmlir/include/mlir/TableGen/Operator.h
The file was addedmlir/include/mlir/TableGen/Successor.h
The file was modifiedmlir/test/Dialect/SPIRV/control-flow-ops.mlir
The file was modifiedmlir/lib/TableGen/Constraint.cpp
Commit 9eb436feaa7f5f01dc4852396647a5b46311c8eb by riddleriver
[mlir][DeclarativeParser] Add support for formatting the successors of an operation.

This revision add support for formatting successor variables in a similar way to operands, attributes, etc.

Differential Revision: https://reviews.llvm.org/D74789
The file was modifiedmlir/lib/Dialect/StandardOps/IR/Ops.cpp
The file was modifiedmlir/test/mlir-tblgen/op-format-spec.td
The file was modifiedmlir/lib/Parser/Parser.cpp
The file was modifiedmlir/include/mlir/Dialect/StandardOps/IR/Ops.td
The file was modifiedmlir/test/mlir-tblgen/op-format.mlir
The file was modifiedmlir/test/lib/TestDialect/TestOps.td
The file was modifiedmlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
The file was modifiedmlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
The file was modifiedmlir/docs/OpDefinitions.md
The file was modifiedmlir/include/mlir/Dialect/SPIRV/SPIRVControlFlowOps.td
The file was modifiedmlir/include/mlir/IR/OpImplementation.h
The file was modifiedmlir/lib/Dialect/SPIRV/SPIRVOps.cpp
The file was modifiedmlir/test/IR/invalid.mlir
The file was modifiedmlir/test/Dialect/SPIRV/control-flow-ops.mlir
The file was modifiedmlir/tools/mlir-tblgen/OpFormatGen.cpp
Commit 0050e8f0cf5782217ebd78fa2b58be3aa9f8d9e2 by riddleriver
[mlir][Tutorial] Add a section to Toy Ch.2 detailing the custom assembly format.

Summary:
This details the C++ format as well as the new declarative format. This has been one of the major missing pieces from the toy tutorial.

Differential Revision: https://reviews.llvm.org/D74938
The file was modifiedmlir/examples/toy/Ch2/mlir/Dialect.cpp
The file was modifiedmlir/examples/toy/Ch5/mlir/Dialect.cpp
The file was modifiedmlir/docs/Tutorials/Toy/Ch-2.md
The file was modifiedmlir/test/Examples/Toy/Ch7/struct-opt.mlir
The file was modifiedmlir/test/Examples/Toy/Ch2/codegen.toy
The file was modifiedmlir/test/Examples/Toy/Ch4/codegen.toy
The file was modifiedmlir/examples/toy/Ch3/include/toy/Ops.td
The file was modifiedmlir/examples/toy/Ch4/include/toy/Ops.td
The file was modifiedmlir/test/Examples/Toy/Ch3/codegen.toy
The file was modifiedmlir/docs/Tutorials/Toy/Ch-4.md
The file was modifiedmlir/docs/Tutorials/Toy/Ch-7.md
The file was modifiedmlir/docs/Tutorials/Toy/Ch-6.md
The file was modifiedmlir/test/Examples/Toy/Ch3/scalar.toy
The file was modifiedmlir/test/Examples/Toy/Ch6/scalar.toy
The file was modifiedmlir/test/Examples/Toy/Ch7/scalar.toy
The file was modifiedmlir/test/Examples/Toy/Ch2/scalar.toy
The file was modifiedmlir/test/Examples/Toy/Ch6/shape_inference.mlir
The file was modifiedmlir/test/Examples/Toy/Ch7/struct-codegen.toy
The file was modifiedmlir/test/Examples/Toy/Ch7/llvm-lowering.mlir
The file was modifiedmlir/test/Examples/Toy/Ch4/shape_inference.mlir
The file was modifiedmlir/examples/toy/Ch7/mlir/Dialect.cpp
The file was modifiedmlir/test/Examples/Toy/Ch7/shape_inference.mlir
The file was modifiedmlir/test/Examples/Toy/Ch7/affine-lowering.mlir
The file was modifiedmlir/test/Examples/Toy/Ch5/affine-lowering.mlir
The file was modifiedmlir/examples/toy/Ch5/include/toy/Ops.td
The file was modifiedmlir/examples/toy/Ch7/include/toy/Ops.td
The file was modifiedmlir/test/Examples/Toy/Ch6/codegen.toy
The file was modifiedmlir/examples/toy/Ch6/mlir/Dialect.cpp
The file was modifiedmlir/test/Examples/Toy/Ch5/shape_inference.mlir
The file was modifiedmlir/test/Examples/Toy/Ch6/llvm-lowering.mlir
The file was modifiedmlir/examples/toy/Ch3/mlir/Dialect.cpp
The file was modifiedmlir/examples/toy/Ch6/include/toy/Ops.td
The file was modifiedmlir/test/Examples/Toy/Ch4/scalar.toy
The file was modifiedmlir/docs/Tutorials/Toy/Ch-5.md
The file was modifiedmlir/examples/toy/Ch4/mlir/Dialect.cpp
The file was modifiedmlir/examples/toy/Ch2/include/toy/Ops.td
The file was modifiedmlir/test/Examples/Toy/Ch5/scalar.toy
The file was modifiedmlir/test/Examples/Toy/Ch7/codegen.toy
The file was modifiedmlir/test/Examples/Toy/Ch5/codegen.toy
The file was modifiedmlir/test/Examples/Toy/Ch6/affine-lowering.mlir
The file was modifiedmlir/docs/Tutorials/Toy/Ch-3.md
Commit 266877a2a8b2d1939f3b08fcfb711890fefc96e3 by rupprecht
[llvm-objdump] Print method name from debug info in disassembly output.

Summary:
GNU objdump prints the method name in disassembly output, and upon further investigation this seems to come from debug info, not the symbol table.

Some additional refactoring is necessary to make this work even when the line number is 0/the filename is unknown. The added test case includes a note for this scenario.

See http://llvm.org/PR41341 for more info.

Reviewers: dblaikie, MaskRay, jhenderson

Reviewed By: MaskRay

Subscribers: ormris, jvesely, aprantl, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74507
The file was modifiedllvm/test/tools/llvm-objdump/X86/source-interleave-x86_64.test
The file was addedllvm/test/tools/llvm-objdump/X86/source-interleave-function-from-debug.test
The file was modifiedllvm/test/tools/llvm-objdump/embedded-source.test
The file was modifiedllvm/tools/llvm-objdump/llvm-objdump.cpp
The file was modifiedllvm/test/tools/llvm-objdump/AMDGPU/source-lines.ll
The file was modifiedllvm/test/tools/llvm-objdump/Hexagon/source-interleave-hexagon.ll
Commit 75af9da755721123e62b45cd0bc0c5e688a9722a by maskray
[MC][ELF] Error for sh_type, sh_flags or sh_entsize change

Heads-up message: https://lists.llvm.org/pipermail/llvm-dev/2020-February/139390.html

GNU as started to emit warnings for changed sh_type or sh_flags in 2000.
GNU as>=2.35 will emit errors for most sh_type/sh_flags change, and error for entsize change.

Some cases remain warnings for legacy reasons:

   .section .init_array,"ax", @progbits
   .section .init_array,"ax", @init_array
   # And some obscure sh_flags changes (OS/Processor specific flags)

The rationale of a diagnostic (warning or error) is that sh_type,
sh_flags or sh_entsize changes usually indicate user errors. The values
are taken from the first .section directive. Successive directives are ignored.

We just try to be rigid and emit errors for all sh_type/sh_flags/sh_entsize change.

A possible improvement in the future is to reuse
llvm-readobj/ELFDumper.cpp:getSectionTypeString so that we can name the
type in the diagnostics.

Reviewed By: psmith

Differential Revision: https://reviews.llvm.org/D73999
The file was modifiedllvm/lib/MC/MCParser/ELFAsmParser.cpp
The file was addedllvm/test/MC/ELF/section-entsize-changed.s
The file was addedllvm/test/MC/ELF/section-type-changed.s
The file was addedllvm/test/MC/ELF/section-flags-changed.s
The file was modifiedllvm/test/MC/ELF/exclude-debug-dwo.s
Commit 8a0f0e2656abf76b771037c6543caf9a31744120 by Vedant Kumar
[lldb/test] Tweak libcxx string test on Apple+ARM devices

On Apple platforms, is __arm__ isn't defined and we're not on Intel, we use an
alternate std::string layout. I.e., the libcxx string test fails on phones
because the hand-crafted "garbage" string structs are actually valid strings.

See:

```
  // _LIBCPP_ALTERNATE_STRING_LAYOUT is an old name for
  // _LIBCPP_ABI_ALTERNATE_STRING_LAYOUT left here for backward compatibility.
  #if (defined(__APPLE__) && !defined(__i386__) && !defined(__x86_64__) &&       \
       (!defined(__arm__) || __ARM_ARCH_7K__ >= 2)) ||                           \
      defined(_LIBCPP_ALTERNATE_STRING_LAYOUT)
  #define _LIBCPP_ABI_ALTERNATE_STRING_LAYOUT
  #endif
```

Disable inspection of the garbage structs on Apple+ARM devices.
The file was modifiedlldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/string/TestDataFormatterLibcxxString.py
Commit d3e170c4388693b6628fa91cbf78506a5fb45439 by mark.searles
Revert "[AMDGPU] Don’t marke the .note section as ALLOC"

This reverts commit 977cd661cf019039dec7ffdd15bf0ac500828c87.

It breaks OpenCL testing. OpenCL Runtime is using PT_LOAD information
to calculate memory for global variables. This commit should be relanded once
the OpenCL runtime stops relying on PT_LOAD information for calculating global
variable memory size.

Differential Revision: https://reviews.llvm.org/D74995
The file was modifiedllvm/test/CodeGen/AMDGPU/hsa.ll
The file was modifiedllvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
Commit 42060c0a987076567814f97abdf485a55bf6018a by riddleriver
[mlir][DeclarativeParser][NFC] Use explicit type names in TypeSwitch to
appease older GCC.

Older versions of GCC are unable to properly capture 'this' in template lambdas,
resulting in errors.
The file was modifiedmlir/tools/mlir-tblgen/OpFormatGen.cpp
Commit 340feac6721e840f88c1e77dd79931eea5eaccf3 by scott.linder
[Driver] Escape the program path for -frecord-command-line

Similar to the rest of the command line that is recorded, the program
path must also have spaces and backslashes escaped. Without this
parsing the recorded command line becomes hard on platforms like
Windows where spaces and backslashes are common.

This was originally reverted in
577d9ce35532439203411c999deefc9c80e04c69; this version makes a test
agnostic to the presence of backslashes in paths on some platforms.

Patch By: Ravi Ramaseshan
Differential Revision: https://reviews.llvm.org/D74811
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was modifiedclang/test/Driver/clang_f_opts.c
Commit bf4933b4ea657128f1afcf19758866d41e5aebf9 by arsenm2
AMDGPU/GlobalISel: Remove dead code
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
Commit 3ec3f62f0a0b1ac13230922c91ffc988c1b1e8d5 by hhb
Allow customized relative PYTHONHOME (Attemp 1)

Summary:
This is another attempt of 0bb90628b5f7c170689d2d3f019af773772fc649.

The difference is that g_python_home is not declared as const. Since
some versions of python do not expect that.

Subscribers: mgorny, lldb-commits

Tags: #lldb

Differential Revision: https://reviews.llvm.org/D74998
The file was modifiedlldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
The file was modifiedlldb/cmake/modules/LLDBConfig.cmake
The file was modifiedlldb/include/lldb/Host/Config.h.cmake
Commit d17123b2577e610b2a19de1f530cecea353c8c7a by maskray
[llvm-objdump][test] Fix source-interleave-function-from-debug.test on Windows after D74507
The file was modifiedllvm/test/tools/llvm-objdump/X86/source-interleave-function-from-debug.test
Commit 3648370a79235ddc7a26c2db5b968725c320f6aa by aheejin
[WebAssembly] Fix a non-determinism problem in FixIrreducibleControlFlow

Summary:
We already sorted the blocks when fixing up a set of mutual
loop entries, however, there can be multiple sets of such
mutual loop entries, and the order we encounter them
should not be random, so sort them too.

Fixes https://bugs.llvm.org/show_bug.cgi?id=44982

Patch by Alon Zakai (kripken)

Reviewers: aheejin, sbc100, dschuff

Subscribers: mgrang, sunfish, hiraditya, jgravelle-google, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74999
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp
Commit e33c9bb245a0c17cdd5c06897a911f908215db50 by apilipenko
Flags for displaying only hot nodes in CFGPrinter graph

Added two flags to omit uncommon or dead paths in the CFG graphs:
  -cfg-hide-unreachable-paths
  -cfg-hide-deoptimize-paths

The main purpose is performance analysis when such block are not
"interesting" from perspective of common path performance.

Reviewed By: apilipenko, davidxl

Differential Revision: https://reviews.llvm.org/D74346
The file was addedllvm/test/Other/cfg_deopt_unreach.ll
The file was modifiedllvm/include/llvm/Analysis/CFGPrinter.h
The file was modifiedllvm/lib/Analysis/CFGPrinter.cpp
Commit ebee131259719fa9c06cd346e21ace3fa8ac0888 by maskray
[lldb][test] Fix sh_type of .debug_cu_index and .debug_tu_index

They do not have the SHF_EXCLUDE flag.
After D73999, MC errors `changed section type for .debug_cu_index, expected: 0x0`
The file was modifiedlldb/test/Shell/SymbolFile/DWARF/dwp.s
The file was modifiedlldb/test/Shell/SymbolFile/DWARF/dwp-debug-types.s
Commit 1b1a97e9b55754302c4b41f6bddc8fbc3870f68a by alexbrachetmialot
Remove unused variable
The file was modifiedlibc/src/signal/linux/raise.cpp
Commit 228a2bc9b70c3d93bd28f0038a8664ef8dac042e by craig.topper
[X86] Teach combineCVTPH2PS to shrink v8i16 loads when the output type is v4f32. Remove extra isel patterns.

Similar to what do for other operations that use a subset of bits.
Allows us to remove a pattern that shrinks a load. Which was
incorrect if the load was volatile.
The file was modifiedllvm/lib/Target/X86/X86InstrAVX512.td
The file was modifiedllvm/lib/Target/X86/X86InstrSSE.td
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit e29065a105342a904871437d18a4e6fab09e5bc1 by maskray
[lldb][test] Fix sh_flags and sh_entsize of .debug_str.dwo

sh_flags: SHF_MERGE | SHF_STRINGS | SHF_EXCLUDE
sh_entsize: 1

Incorrect sh_flags or sh_entsize is an error after the assembler change made by D73999.
The file was modifiedlldb/test/Shell/SymbolFile/DWARF/dwp.s
Commit a4f45ee73a9e948622488f874d5e01408dffba2a by paulatoth
[libc] Lay out framework for fuzzing libc functions.

Summary:
Added fuzzing test for strcpy and some documentation related to fuzzing.
This will be the first step in integrating this with oss-fuzz.

Reviewers: sivachandra, abrachet

Reviewed By: sivachandra, abrachet

Subscribers: gchatelet, abrachet, mgorny, MaskRay, tschuett, libc-commits

Tags: #libc-project

Differential Revision: https://reviews.llvm.org/D74091
The file was addedlibc/fuzzing/string/strcpy_fuzz.cpp
The file was modifiedlibc/CMakeLists.txt
The file was modifiedlibc/docs/source_layout.rst
The file was modifiedlibc/cmake/modules/LLVMLibCRules.cmake
The file was addedlibc/docs/fuzzing.rst
The file was addedlibc/fuzzing/CMakeLists.txt
The file was addedlibc/fuzzing/string/CMakeLists.txt
Commit b6d63c92ec37a4416009c3bd279561421429c396 by qcolombet
[GISel][KnownBits] Suppress unused warning on the dump method

NFC
The file was modifiedllvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
Commit 59a572eb742437c17b78f6cf63f14d4b808fe61f by maskray
[Preprocessor][test] Move AArch64 tests from init.c to init-aarch.c
The file was addedclang/test/Preprocessor/init-aarch64.c
The file was modifiedclang/test/Preprocessor/aarch64-target-features.c
The file was modifiedclang/test/Preprocessor/init.c
Commit 0123744d46a1fd6041755b403633af2d6c47f64a by maskray
[Preprocessor][test] Fix __VERSION__ in init-aarch64.c
The file was modifiedclang/test/Preprocessor/init-aarch64.c
Commit fc6057e34fb3b1cfbbfcd5d71ae25ba24eb3ffa3 by maskray
[Frontend] Replace CC1 option -mcode-model with -mcmodel=

Before:

% clang -mcmodel=x -xc /dev/null
error: invalid argument 'x' in '-mcode-model x'

Now:

% clang -mcmodel=x -xc /dev/null
clang-11: error: invalid argument 'x' to -mcmodel=
The file was modifiedclang/include/clang/Driver/Options.td
The file was removedclang/test/Driver/code-model.c
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was addedclang/test/Driver/mcmodel.c
The file was modifiedllvm/docs/Extensions.rst
The file was modifiedclang/test/CodeGen/codemodels.c
The file was modifiedclang/include/clang/Driver/CC1Options.td
Commit d2e949eed5b49ca70a8845dfaf7bac6ca40c429d by maskray
[AArch64] Predefine __AARCH64_CMODEL_*__ as GCC does

Make Clang on aarch64 targets predefine `__AARCH64_CMODEL_SMALL__`
or `__AARCH64_CMODEL_TINY__`, etc.  These are the names that GCC
uses for its predefines.

Reviewed By: tamur, MaskRay

Differential Revision: https://reviews.llvm.org/D75002
The file was modifiedclang/test/Preprocessor/init-aarch64.c
The file was modifiedclang/lib/Basic/Targets/AArch64.cpp
Commit 271f96477328f42cbf31a2b42433cdef8ed91914 by maskray
[Preprocessor][X86] Fix __code_model_*__ predefine macros

GCC defines __code_model_*__ (two trailing underscores), not
__code_model_*_ (one trailing underscore).

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D75003
The file was modifiedclang/lib/Basic/Targets/X86.cpp
The file was modifiedclang/test/Preprocessor/init.c
Commit d192a4ab2b8c0f80efcb006a4b200ad3ba73d485 by sguelton
Update Quantization.md

Various typographic, grammatical and formatting edits and tidy ups.
The file was modifiedmlir/docs/Quantization.md
Commit 453cd2dbe57bce945c9d9a2bbf43677252b53597 by sguelton
Update ShapeInference.md

Variety of editorial and typographic and formatting tweaks.
The file was modifiedmlir/docs/ShapeInference.md
Commit 635034f19387427e7df60efb985d2de7766a1e58 by simon.moll
[VE][fix] missing include
The file was modifiedllvm/lib/Target/VE/MCTargetDesc/VEMCExpr.cpp
Commit 31f2ad9c368d47721508cbd0d120d626f9041715 by grimar
[yaml2obj] - Automatically assign sh_addr for allocatable sections.

I've noticed that it is not convenient to create YAMLs from
binaries (using obj2yaml) that have to be test cases for obj2yaml
later (after applying yaml2obj).

The problem, for example is that obj2yaml emits "DynamicSymbols:"
key instead of .dynsym. It also does not create .dynstr.
And when a YAML document without explicitly defined .dynsym/.dynstr
is given to yaml2obj, we have issues:

1) These sections are placed after non-allocatable sections (I've fixed it in D74756).
2) They have VA == 0. User needs create descriptions for such sections explicitly manually
    to set a VA.

This patch addresses (2). I suggest to let yaml2obj assign virtual addresses by itself.
It makes an output binary to be much closer to "normal" ELF.
(It is still possible to use "Address: 0x0" for a section to get the original behavior
if it is needed)

Differential revision: https://reviews.llvm.org/D74764
The file was modifiedllvm/test/tools/llvm-readobj/ELF/versioninfo.test
The file was modifiedllvm/test/tools/obj2yaml/elf-gnu-hash-section.yaml
The file was modifiedllvm/include/llvm/ObjectYAML/ELFYAML.h
The file was modifiedllvm/test/tools/llvm-readobj/ELF/verneed-invalid.test
The file was modifiedllvm/test/tools/llvm-objcopy/ELF/only-keep-debug.test
The file was modifiedllvm/tools/obj2yaml/elf2yaml.cpp
The file was addedllvm/test/tools/yaml2obj/ELF/section-address-assign.yaml
The file was modifiedllvm/lib/ObjectYAML/ELFEmitter.cpp
The file was modifiedllvm/lib/ObjectYAML/ELFYAML.cpp
Commit a6370d5798313e99d37fb85db5d78f1141506864 by grimar
[lldb][test] - Update basic-elf.yaml to fix build bot.

D74764 (https://reviews.llvm.org/rG31f2ad9c368d47721508cbd0d120d626f9041715)
changed the behavior of the yaml2obj. Now it assigns virtual addresses
for allocatable sections.

SymbolFile/Breakpad/symtab.test started to fail after this change:
(http://lab.llvm.org:8011/builders/lldb-x86_64-debian/builds/5520/steps/test/logs/stdio)

Command Output (stderr):
--
/home/worker/lldb-x86_64-debian/lldb-x86_64-debian/llvm-project/lldb/test/Shell/SymbolFile/Breakpad/symtab.test:6:10: error: CHECK: expected string not found in input
# CHECK: Symtab, file = {{.*}}symtab.out, num_symbols = 5:
         ^
<stdin>:15:1: note: scanning from here
Symtab, file = /home/worker/lldb-x86_64-debian/lldb-x86_64-debian/build/tools/lldb/test/SymbolFile/Breakpad/Output/symtab.out, num_symbols = 6:
^
<stdin>:15:99: note: possible intended match here
Symtab, file = /home/worker/lldb-x86_64-debian/lldb-x86_64-debian/build/tools/lldb/test/SymbolFile/Breakpad/Output/symtab.out, num_symbols = 6:

For now I've updated the basic-elf.yaml so that now it produce the same layout as before D74764.
Breakpad/symtab.test should be updated it seems.
The file was modifiedlldb/test/Shell/SymbolFile/Breakpad/Inputs/basic-elf.yaml
Commit 837d8129e916765123f83f47ce380ff436191f6e by tyker
[NFC] Remove some GCC warning from c9e93c84f61400d1aac7d195a0578e80bc48c69a
The file was modifiedllvm/unittests/Transforms/Utils/KnowledgeRetentionTest.cpp
The file was modifiedllvm/lib/Transforms/Utils/KnowledgeRetention.cpp
Commit e48849a2404128175df25168f961a83d6c0a901e by bion
[libcxx] [test] Suppress MSVC++ warning 4640 under /Zc:threadSafeInit-
The file was modifiedlibcxx/test/support/count_new.h
The file was modifiedlibcxx/test/support/type_id.h
Commit 7b44f0428af4000372af5f016995c032a959d17e by i
Add a llvm::shuffle and use it in lld

With this --shuffle-sections=seed produces the same result in every
host.

Reviewed By: grimar, MaskRay

Differential Revision: https://reviews.llvm.org/D74971
The file was modifiedlld/ELF/Writer.cpp
The file was modifiedlld/test/ELF/shuffle-sections-init-fini.s
The file was modifiedlld/test/ELF/shuffle-sections.s
The file was modifiedllvm/include/llvm/ADT/STLExtras.h
Commit 56eb15a1c71061043d50aa669407816bc08dfb5d by koraq
[Sema] Fix pointer-to-int-cast diagnostic for _Bool

The diagnostic added in D72231 also shows a diagnostic when casting to a
_Bool. This is unwanted. This patch removes the diagnostic for _Bool types.

Differential Revision: https://reviews.llvm.org/D74860
The file was modifiedclang/test/Sema/cast.c
The file was modifiedclang/lib/Sema/SemaCast.cpp
The file was modifiedclang/test/Sema/MicrosoftExtensions.c
The file was modifiedclang/test/SemaCXX/cstyle-cast.cpp
Commit 81726894d3c8af556eb86007c8c26d7e2d9639f3 by Lang Hames
[ORC] Add errors for missing and extraneous symbol definitions.

This patch adds new errors and error checking to the ObjectLinkingLayer to
catch cases where a compiled or loaded object either:
(1) Contains definitions not covered by its responsibility set, or
(2) Is missing definitions that are covered by its responsibility set.

Proir to this patch providing the correct set of definitions was treated as
an API contract requirement, however this requires that the client be confident
in the correctness of the whole compiler / object-cache pipeline and results
in difficult-to-debug assertions upon failure. Treating this as a recoverable
error results in clearer diagnostics.

The performance overhead of this check is one comparison of densemap keys
(symbol string pointers) per linking object, which is minimal. If this overhead
ever becomes a problem we can add the check under a flag that can be turned off
if the client fully trusts the rest of the pipeline.
The file was modifiedllvm/lib/ExecutionEngine/Orc/ObjectLinkingLayer.cpp
The file was modifiedllvm/lib/ExecutionEngine/OrcError/OrcError.cpp
The file was modifiedllvm/include/llvm/ExecutionEngine/Orc/OrcError.h
The file was modifiedllvm/lib/ExecutionEngine/Orc/Core.cpp
The file was modifiedllvm/include/llvm/ExecutionEngine/Orc/Core.h
Commit 1df947ab403a9ec3bb1bf4cd83610a997dc4f3bc by Lang Hames
[ORC] Update LLJIT to automatically run specially named initializer functions.

The GenericLLVMIRPlatformSupport class runs a transform on all LLVM IR added to
the LLJIT instance to replace instances of llvm.global_ctors with a specially
named function that runs the corresponing static initializers (See
(GlobalCtorDtorScraper from lib/ExecutionEngine/Orc/LLJIT.cpp). This patch
updates the GenericIRPlatform class to check for this specially named function
in other materialization units that are added to the JIT and, if found, add
the function to the initializer work queue. Doing this allows object files
that were compiled from IR and cached to be reloaded in subsequent JIT sessions
without their initializers being skipped.

To enable testing this patch also updates the lli tool's -jit-kind=orc-lazy mode
to respect the -enable-cache-manager and -object-cache-dir options, and modifies
the CompileOnDemandLayer to rename extracted submodules to include a hash of the
names of their symbol definitions. This allows a simple object caching scheme
based on module names (which was already implemented in lli) to work with the
lazy JIT.
The file was modifiedllvm/lib/ExecutionEngine/Orc/LLJIT.cpp
The file was addedllvm/test/ExecutionEngine/OrcLazy/static-initializers-in-objectfiles.ll
The file was modifiedllvm/tools/lli/lli.cpp
The file was modifiedllvm/lib/ExecutionEngine/Orc/CompileOnDemandLayer.cpp
Commit e7a184fc7c044b883ab782fa05e56f873050bd72 by craig.topper
[X86] Use movlps for i64 atomic stores on 32-targets with sse1.

This is similar to using movd which we do for sse2 targets.

I've added a DAG combine for VEXTRACT_STORE to use SimplifyDemandedVectorElts
to clean up some artifacts from type legalization.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/atomic-fp.ll
The file was modifiedllvm/test/CodeGen/X86/atomic-non-integer.ll
Commit bdb1729c8347c2b7d932976f8588e524b4f7b8d5 by craig.topper
[X86] Teach EltsFromConsecutiveLoads that it's ok to form a v4f32 VZEXT_LOAD with a 64 bit memory size on SSE1 targets.

We can use MOVLPS which will load 64 bits, but we need a v4f32
result type. We already have isel patterns for this.

The code here is a little hacky. We can probably improve it with
more isel patterns.
The file was modifiedllvm/test/CodeGen/X86/atomic-fp.ll
The file was modifiedllvm/test/CodeGen/X86/atomic-non-integer.ll
The file was modifiedllvm/test/CodeGen/X86/merge-consecutive-loads-128.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 84cd968f75bbd6e0fbabecc29d2c1090263adec7 by craig.topper
[X86] Add AddToWorklist(N) after calls to SimplifyDemandedBits/SimplifyDemandedVectorElts that are called on an operand of N.

If a simplication occurs the operand will be added to the worklist.
But since the demanded mask was based on N, we need to make sure
we revisit N in case there are more simplifications to be done.
Returning SDValue(N, 0) as we do, only tells DAG combine that
something changed, but that won't make it add anything to the
worklist.

Found while playing around with using VEXTRACT_STORE in more cases.
But I guess this doesn't affect any of our existing tests.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 57923617181b0181e8d5c2f2e940a94a82737c7c by craig.topper
[X86] Add sse2 command lines to sse-intrinsics-fast-isel.ll.

The extra available vector types on sse2 causes us to produce
different code.
The file was modifiedllvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll
Commit 21316f6f928301fb7b4fb1cbd8836cdbbcc62b41 by khalikov.denis
[NFC] Test commit access. Drop trivial braces.
The file was modifiedmlir/tools/mlir-vulkan-runner/VulkanRuntime.cpp
Commit 98ac6e76960aec89ac5094702d124678e8524afa by nunoplopes
[NFC] fix test nan value
The file was modifiedllvm/test/Transforms/InstCombine/fneg.ll
Commit 7d3f8b1e2dcda99b245a9e3a254090aa1b5cfd66 by sam.mccall
[clangd] Debounce rebuilds responsively to rebuild times.

Summary:
Old: 500ms always. New: rebuild time, up to 500ms.

Fixes https://github.com/clangd/clangd/issues/275

Reviewers: hokein

Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, kadircet, usaxena95, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D73949
The file was modifiedclang-tools-extra/clangd/ClangdServer.h
Commit a2ce807eb72a8e154abca09b1e968b2d99ba6933 by sam.mccall
[clangd] Reapply b60896fad926 Fall back to selecting token-before-cursor if token-after-cursor fails.

This reverts commit 6af1ad20d60ef8ea23f2cfdb02d299b3b3114b06.
The file was modifiedclang-tools-extra/clangd/refactor/Tweak.h
The file was modifiedclang-tools-extra/clangd/unittests/FindTargetTests.cpp
The file was modifiedclang-tools-extra/clangd/Hover.cpp
The file was modifiedclang-tools-extra/clangd/Selection.cpp
The file was modifiedclang-tools-extra/clangd/XRefs.cpp
The file was modifiedclang-tools-extra/clangd/unittests/SelectionTests.cpp
The file was modifiedclang-tools-extra/clangd/unittests/TweakTests.cpp
The file was modifiedclang-tools-extra/clangd/SemanticSelection.cpp
The file was modifiedclang-tools-extra/clangd/refactor/Rename.cpp
The file was modifiedclang-tools-extra/clangd/refactor/Tweak.cpp
The file was modifiedclang-tools-extra/clangd/ClangdServer.cpp
The file was modifiedclang-tools-extra/clangd/unittests/HoverTests.cpp
The file was modifiedclang-tools-extra/clangd/Selection.h
The file was modifiedclang-tools-extra/clangd/unittests/TweakTesting.cpp
Commit b4b9706d5da368c81b86867b1c11a2e17b4472ac by sam.mccall
Revert "[clangd] Reapply b60896fad926 Fall back to selecting token-before-cursor if token-after-cursor fails."

This reverts commit a2ce807eb72a8e154abca09b1e968b2d99ba6933.

Buildbot failures on GCC due to SelectionTree not being copyable, and
instantiating vector<Selection> in the tweak-handling in ClangdServer.
The file was modifiedclang-tools-extra/clangd/ClangdServer.cpp
The file was modifiedclang-tools-extra/clangd/XRefs.cpp
The file was modifiedclang-tools-extra/clangd/unittests/TweakTesting.cpp
The file was modifiedclang-tools-extra/clangd/unittests/SelectionTests.cpp
The file was modifiedclang-tools-extra/clangd/Selection.h
The file was modifiedclang-tools-extra/clangd/refactor/Rename.cpp
The file was modifiedclang-tools-extra/clangd/unittests/TweakTests.cpp
The file was modifiedclang-tools-extra/clangd/refactor/Tweak.h
The file was modifiedclang-tools-extra/clangd/unittests/HoverTests.cpp
The file was modifiedclang-tools-extra/clangd/SemanticSelection.cpp
The file was modifiedclang-tools-extra/clangd/refactor/Tweak.cpp
The file was modifiedclang-tools-extra/clangd/Hover.cpp
The file was modifiedclang-tools-extra/clangd/Selection.cpp
The file was modifiedclang-tools-extra/clangd/unittests/FindTargetTests.cpp
Commit af69d5e10eb7bef52521fc052795690598040dc7 by flo
[DSE] Track overlapping stores.

Add a map from BasicBlocks to overlap intervals. For partial writes, we
can keep track of those in IOLs. We only add candidates that are valid
for eliminations.

Reviewers: dmgreen, bryant, asbirlea, Tyker

Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D73757
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/OverwriteStoreBegin.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/memset-missing-debugloc.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-loops.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-memintrinsics.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/OverwriteStoreEnd.ll
The file was modifiedllvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
Commit a253a2a793cda34d1f6421ee9b7ca76a03fdfc59 by spatel
[SDAG] fold fsub -0.0, undef to undef rather than NaN

A question about this behavior came up on llvm-dev:
http://lists.llvm.org/pipermail/llvm-dev/2020-February/139003.html
...and as part of backend improvements in D73978.

We decided not to implement a more general change that would have
folded any FP binop with nearly arbitrary constant + undef operand
to undef because that is not theoretically correct (even if it is
practically correct).

This is the SDAG-equivalent to the IR change in D74713.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modifiedllvm/test/CodeGen/X86/vec_fneg.ll
Commit 31059ba5eb12ccbf18c957e76318306474af6166 by craig.topper
[X86] Regenerate some tests to show FMA4 comments. NFC
The file was modifiedllvm/test/CodeGen/X86/recip-fastmath.ll
The file was modifiedllvm/test/CodeGen/X86/recip-fastmath2.ll
Commit 7769030b9310c1865fd331edb78dc242a39b109a by flo
Recommit "[PatternMatch] Match XOR variant of unsigned-add overflow check."

This version fixes a buildbot failure cause by picking the wrong insert
point for XORs. We cannot pick the XOR binary operator as insert point,
as it is not guaranteed that both input operands for the overflow
intrinsic are defined before it.

This reverts the revert commit
c7fc0e5da6c3c36eb5f3a874a6cdeaedb26856e0.
The file was modifiedllvm/include/llvm/IR/PatternMatch.h
The file was modifiedllvm/lib/CodeGen/CodeGenPrepare.cpp
The file was modifiedllvm/test/Transforms/CodeGenPrepare/AArch64/overflow-intrinsics.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
The file was modifiedllvm/test/CodeGen/AArch64/sat-add.ll
The file was modifiedllvm/test/CodeGen/X86/sat-add.ll
The file was modifiedllvm/test/Transforms/CodeGenPrepare/X86/overflow-intrinsics.ll
Commit 335e21f9006912ce547125fc406a0441a82e8c5d by flo
[AArch64] Update new test.

Changed after 7769030b9310c1865fd331edb78dc242a39b109a.
The file was modifiedllvm/test/CodeGen/AArch64/sat-add.ll
Commit be6d07c9208e70e6453201f52e9b10dc3524abb9 by sam.mccall
[clangd] Reapply b60896fad926 Fall back to selecting token-before-cursor if token-after-cursor fails.

This reverts commit b4b9706d5da368c81b86867b1c11a2e17b4472ac.
Now avoiding expected<vector<selection>> in favor of expected<vector<unique_ptr<selection>>>
The file was modifiedclang-tools-extra/clangd/Selection.h
The file was modifiedclang-tools-extra/clangd/unittests/TweakTesting.cpp
The file was modifiedclang-tools-extra/clangd/ClangdServer.cpp
The file was modifiedclang-tools-extra/clangd/XRefs.cpp
The file was modifiedclang-tools-extra/clangd/unittests/SelectionTests.cpp
The file was modifiedclang-tools-extra/clangd/unittests/FindTargetTests.cpp
The file was modifiedclang-tools-extra/clangd/refactor/Tweak.cpp
The file was modifiedclang-tools-extra/clangd/unittests/TweakTests.cpp
The file was modifiedclang-tools-extra/clangd/SemanticSelection.cpp
The file was modifiedclang-tools-extra/clangd/refactor/Tweak.h
The file was modifiedclang-tools-extra/clangd/unittests/HoverTests.cpp
The file was modifiedclang-tools-extra/clangd/refactor/Rename.cpp
The file was modifiedclang-tools-extra/clangd/Selection.cpp
The file was modifiedclang-tools-extra/clangd/Hover.cpp
Commit 86cda4c50da4fe31771f866071c8516199c7c2b0 by aaron
Updating a comment to clarify that SkipUntil handles balanced delimiters.
The file was modifiedclang/include/clang/Parse/Parser.h
Commit e9997cfb4d44e93cc65a29d1e1bb7451f418a7c7 by sam.mccall
[clangd] Try to fix buildbots - copy elision not happening here?
The file was modifiedclang-tools-extra/clangd/ClangdServer.cpp
Commit 82879c2913da69ef2deadee9d075140a84eb6e8c by paulsson
[SystemZ]  Support the kernel back chain.

In order to build the Linux kernel, the back chain must be supported with
packed-stack. The back chain is then stored topmost in the register save
area.

Review: Ulrich Weigand

Differential Revision: https://reviews.llvm.org/D74506
The file was addedllvm/test/CodeGen/SystemZ/frame-24.ll
The file was modifiedllvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
The file was modifiedllvm/lib/Target/SystemZ/SystemZISelLowering.cpp
The file was modifiedclang/test/Driver/mbackchain.c
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was modifiedllvm/lib/Target/SystemZ/SystemZFrameLowering.h
The file was addedllvm/test/CodeGen/SystemZ/frameaddr-02.ll
The file was addedllvm/test/CodeGen/SystemZ/frame-23.ll
Commit 2a10f8019dd9525c91d1f2f74538c83edfc16bee by craig.topper
[X86] Use FIST for i64 atomic stores on 32-bit targets without SSE.
The file was modifiedllvm/test/CodeGen/X86/atomic-load-store-wide.ll
The file was modifiedllvm/test/CodeGen/X86/atomic-fp.ll
The file was modifiedllvm/test/CodeGen/X86/atomic-non-integer.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/atomic-mi.ll
Commit 15b6aa744881b6e77a3d6773afa3016fc2f9f123 by craig.topper
[X86] Enable the use of movlps for i64 atomic load on 32-bit targets with sse1.

Still a little room for improvement by using movlps to store to
the stack temporary needed to move data out of the xmm register
after the load.
The file was modifiedllvm/test/CodeGen/X86/atomic-fp.ll
The file was modifiedllvm/test/CodeGen/X86/atomic-non-integer.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 5a705186604fbd1bc762f5fe7370983cc0827ffd by craig.topper
[X86] Remove most X86 specific subclasses of MemSDNode. Just use a MemIntrinsicSDNode as we usually do.

Leave the gather/scatter subclasses, but make them inherit from
MemIntrinsicSDNode and delete their constructor and destructor.
This way we can still have the getIndex, getMask, etc. convenience
functions.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.h
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/lib/Target/X86/X86InstrFragmentsSIMD.td
Commit 384d5e33fe2ea0b40119b003b60cfa8b21e3fd15 by craig.topper
[SelectionDAG] Remove SelectionDAG::getTargetMemSDNode now that its not used.

Targets are expected to use getMemIntrinsicNode and not provide
their own subclasses. X86 was previously the only user.
The file was modifiedllvm/include/llvm/CodeGen/SelectionDAG.h
Commit bae33a7c5a1f220671e6d99cda21749afe2501a6 by aktoon
IR printing for single function with the new pass manager.

Summary:
The IR printing always prints out all functions in a module with the new pass manager, even with -filter-print-funcs specified. This is being fixed in this change. However, there are two exceptions, i.e, with user-specified wildcast switch -filter-print-funcs=* or -print-module-scope, under which IR of all functions should be printed.

Test Plan:
make check-clang
make check-llvm

Reviewers: wenlei

Reviewed By: wenlei

Subscribers: wenlei, hiraditya, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D74814
The file was modifiedllvm/lib/Passes/StandardInstrumentations.cpp
The file was modifiedllvm/test/Other/module-pass-printer.ll
Commit 8b3a62dc987288a04f84c0e105303871943e8831 by qshanz
[NFC][PowerPC] Refactor the tryAndWithMask()

Split the tryAndWithMask into several small calls.

Differential Revision: https://reviews.llvm.org/D72250
The file was modifiedllvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
Commit 6a3506a208b90e65c719b0942376f46902a08945 by shengchen.kan
[Driver][X86] Add helptext for malign-branch*, mbranches-within-32B-boundaries

Differential Revision: https://reviews.llvm.org/D75017
The file was modifiedclang/include/clang/Driver/Options.td
Commit 4d812acba61e6306181a830a18d21bcb07b9f8c7 by sivachandra
[libc] Add a README to the sub-directories under the utils directory.

Also, the source layout document has been updated to reflect the current
layout of the `utils` directory.

Reviewers: PaulkaToast

Differential Revision: https://reviews.llvm.org/D74502
The file was addedlibc/utils/UnitTest/README.md
The file was modifiedlibc/utils/CPP/README.md
The file was modifiedlibc/docs/source_layout.rst
The file was addedlibc/utils/HdrGen/README.md
Commit 3a6bb32bd24b6f1b01ae2378ea7fa726f453fb1c by craig.topper
[SelectionDAG] Remove ISD::LIFETIME_START/LIFETIME_END from assert in getMemIntrinsicNode.

These appear to have their own SDNode type and shouldn't use
MemIntrinsicSDNode.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Commit f1b8ec3398fc0022b825b709eb6e792d35276bc1 by craig.topper
[X86] Use custom isel for gather/scatter instructions.

The type profile we use for the isel patterns lied about how
many operands the gather/scatter node has to skip the index
and scale operands. This allowed us to expand the baseptr
operand into base, displacement, and segment and then merge
the index and scale with them in the final instruction during
isel. This is kind of a hack that relies on isel not checking the
number of operands at all.

This commit switches to custom isel where we can manage this
directly without relying on holes in the isel checking.
The file was modifiedllvm/lib/Target/X86/X86InstrAVX512.td
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/X86/X86InstrSSE.td
The file was modifiedllvm/lib/Target/X86/X86InstrFragmentsSIMD.td
Commit 7a7146cf72ad46f706e892f32f64405665f31ba3 by craig.topper
[X86] When creating X86ISD::MGATHER nodes from AVX2 gather intrinsics, cast the mask to integer type.

The gather intrinsics use a floating point mask when the result
type is FP. But we call DemandedBits on the mask assuming its an
integer type. We also use integer types when we create it from
generic IR. So add a bitcast to the intrinsic path to guarantee
the integer type.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Commit 27a79b721628ce0814cdc7b4d5267717bcc52421 by Lang Hames
[JITLink] Add a MachO x86-64 GOT and Stub bypass optimization.

This optimization bypasses GOT loads and calls/branches through stubs when the
ultimate target of the access/branch is found to be within range of the
reference.

Extra debugging output is also added to the generic JITLink algorithm and
basic GOT and Stubs builder utility to aid debugging.
The file was addedllvm/test/ExecutionEngine/JITLink/X86/Inputs/MachO_GOTAndStubsOptimizationHelper.s
The file was modifiedllvm/lib/ExecutionEngine/JITLink/BasicGOTAndStubsBuilder.h
The file was modifiedllvm/lib/ExecutionEngine/JITLink/JITLinkGeneric.cpp
The file was modifiedllvm/test/ExecutionEngine/JITLink/X86/MachO_x86-64_relocations.s
The file was modifiedllvm/lib/ExecutionEngine/JITLink/JITLinkGeneric.h
The file was modifiedllvm/lib/ExecutionEngine/JITLink/MachO_x86_64.cpp
The file was modifiedllvm/include/llvm/ExecutionEngine/JITLink/JITLink.h
The file was modifiedllvm/include/llvm/ExecutionEngine/JITLink/MachO_x86_64.h
The file was addedllvm/test/ExecutionEngine/JITLink/X86/MachO_GOTAndStubsOptimization.s
Commit e657a1eb23f8231296ac0c62a1cd497762bd0f3e by Raphael Isemann
[lldb] Remove all the 'current_id'  logging counters from the lookup code.

Summary:
We have a lot of code in our lookup code to pass around `current_id` counters which end up in our logs like this:
```
AOCTV::FT [234] Found XYZ
```

This patch removes all of this code because:
* I'm splitting up all humongous functions, so I need to write more and more boilerplate to pass around these ids.
* I never saw any similar counters in the LLDB/LLVM code base.
* They're essentially globals and the last thing we need in LLDB is even more global state.
* They're not really useful when readings logs. It doesn't help that there isn't just 1 or 2 counters, but 12 (!) unique counters. I always thought that if I see two identical counter values in those brackets it's the same lookup request, but it seems that's only true by accident (and you can't know which of the 12 counters is actually printed without reading the code). The only time I know I can trust the counters is when it's obvious from the log that it's the same counter like in the log below, but then why have the counters in the first place?

```
LayoutRecordType[28] on (ASTContext*)0x00007FFA1C840200 'scratch ASTContext' for (RecordDecl*)0x00007FFA0AAE8CF0 [name = '__tree']
LRT[28] returned:
LRT[28]   Original = (RecordDecl*)%p
LRT[28]   Size = %lld
LRT[28]   Alignment = %lld
LRT[28]   Fields:
LRT[28]     (FieldDecl*)0x00007FFA1A13B1D0, Name = '__begin_node_', Offset = 0 bits
LRT[28]     (FieldDecl*)0x00007FFA1C08FD30, Name = '__pair1_', Offset = 64 bits
LRT[28]     (FieldDecl*)0x00007FFA1C061210, Name = '__pair3_', Offset = 128 bits
LRT[28]   Bases:
```

Reviewers: labath, shafik, JDevlieghere

Reviewed By: labath, shafik, JDevlieghere

Subscribers: abidh, lldb-commits

Tags: #lldb

Differential Revision: https://reviews.llvm.org/D74951
The file was modifiedlldb/source/Plugins/ExpressionParser/Clang/ClangExpressionDeclMap.h
The file was modifiedlldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCDeclVendor.cpp
The file was modifiedlldb/source/Plugins/ExpressionParser/Clang/ClangASTSource.cpp
The file was modifiedlldb/source/Plugins/ExpressionParser/Clang/ClangExpressionDeclMap.cpp
The file was modifiedlldb/source/Plugins/ExpressionParser/Clang/ClangASTSource.h
Commit 03756a41979915c63d0a9eb214524e03aaff876d by sam.parker
[ARM][MVE] Combine more extending masked loads

For MVE, don't look at the users of the extending loads so that more
as desirable for folding.

Differential Revision: https://reviews.llvm.org/D74958
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/extending-loads.ll
Commit 0f7cfb25432e405aeb12251598a9798662979ced by pavel
[lldb/DWARF] Don't index dwp file multiple times

Summary:
When we added support for type units in dwo files, we changed the
"manual" dwarf index to index _all_ dwarf units in the dwo file instead
of just the split unit belonging to our skeleton unit. This was fine for
dwo files, as they contain only a single compile units and type units do
not have a split type unit which would point to them.

However, this does not work for dwp files because, these files do
contain multiple split compile units, and the current approach means
that each unit gets indexed multiple times (once for each split unit =>
n^2 complexity).

This patch teaches the manual dwarf index to treat dwp files specially.
Any type units in the dwp file added to the main list of compile units
and indexed with them in a single batch. Split compile units in dwp
files are still indexed as a part of their skeleton unit -- this is done
because we need the DW_AT_language attribute from the skeleton unit to
index them properly.

Handling of dwo files remains unchanged -- all units (type and skeleton)
are indexed when we reach the dwo file through the split unit.

Reviewers: clayborg, JDevlieghere, aprantl

Subscribers: arphaman, lldb-commits

Tags: #lldb

Differential Revision: https://reviews.llvm.org/D74964
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/DebugNamesDWARFIndex.h
The file was modifiedlldb/test/Shell/SymbolFile/DWARF/dwp-debug-types.s
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.h
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/DebugNamesDWARFIndex.cpp
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h
Commit be3b448c2e39b9f1302601935955a9f5e5f013e8 by pavel
[lldb/test] simplify basic-elf.yaml

Explicit dynsym/dynstr sections were added in a6370d5 to compensate for
a yaml2obj change D74764. This test doesn't need those sections, so
instead I just delete the explicit section blocks, and also the
"DynamicSymbols" block, which triggers their implicit generation.
The file was modifiedlldb/test/Shell/SymbolFile/Breakpad/Inputs/basic-elf.yaml
Commit c131dfefe2b404dc1dbb32a02ea484fd7edaffdc by Raphael Isemann
[lldb] Disable auto fix-its when evaluating expressions in the test suite

Summary:
Currently the test suite runs with enabled automatically applied Clang fix-its for expressions.
This is causing that sometimes incorrect expressions in tests are still evaluated even though they
are actually incorrect. Let's disable this feature in the test suite so that we know when expressions
are wrong and leave the fix-it testing to the dedicated tests for that feature.

Also updates the `lang/cpp/operators/` test as it seems Clang needs the `struct` keywords
before C and would otherwise fail without fixits.

Reviewers: jingham, JDevlieghere, shafik

Reviewed By: JDevlieghere, shafik

Subscribers: shafik, lldb-commits

Tags: #lldb

Differential Revision: https://reviews.llvm.org/D74957
The file was modifiedlldb/packages/Python/lldbsuite/test/lldbtest.py
The file was modifiedlldb/test/API/lang/cpp/operators/main.cpp
The file was modifiedlldb/test/Shell/lit-lldb-init.in
Commit c3f36acc92479f6f27ed226e52499d619308561e by bevin.hansson
[MC] Widen the functional unit type from 32 to 64 bits.

Summary:
The type used to represent functional units in MC is
'unsigned', which is 32 bits wide. This is currently
not a problem in any upstream target as no one seems
to have hit the limit on this yet, but in our
downstream one, we need to define more than 32
functional units.

Increasing the size does not seem to cause a huge
size increase in the binary (an llc debug build went
from 1366497672 to 1366523984, a difference of 26k),
so perhaps it would be acceptable to have this patch
applied upstream as well.

Subscribers: hiraditya, jsji, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D71210
The file was modifiedllvm/lib/CodeGen/ScoreboardHazardRecognizer.cpp
The file was modifiedllvm/lib/CodeGen/MachinePipeliner.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
The file was modifiedllvm/include/llvm/MC/MCInstrItineraries.h
The file was modifiedllvm/utils/TableGen/SubtargetEmitter.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
The file was modifiedllvm/include/llvm/CodeGen/ScoreboardHazardRecognizer.h
The file was modifiedllvm/lib/Target/Hexagon/HexagonInstrInfo.h
Commit 9b23024c8b5d29d352215cc2e78eb1522f82a340 by pavel
Use new FailedWithMessage matcher in DWARFDebugLineTest.cpp

Summary:
This should produce slightly better error messages in case of failures.
Only slightly, because this code was pretty careful about that to begin
with -- I've seen code which does much worse.

Reviewers: jhenderson, dblaikie

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74899
The file was modifiedllvm/unittests/DebugInfo/DWARF/DWARFDebugLineTest.cpp
Commit 8f46269f0c1cc93b080931fd9dfeffc4d364004b by calixte.denizet
[profile] Don't dump counters when forking and don't reset when calling exec** functions

Summary:
There is no need to write out gcdas when forking because we can just reset the counters in the parent process.
Let say a counter is N before the fork, then fork and this counter is set to 0 in the child process.
In the parent process, the counter is incremented by P and in the child process it's incremented by C.
When dump is ran at exit, parent process will dump N+P for the given counter and the child process will dump 0+C, so when the gcdas are merged the resulting counter will be N+P+C.
About exec** functions, since the current process is replaced by an another one there is no need to reset the counters but just write out the gcdas since the counters are definitely lost.
To avoid to have lists in a bad state, we just lock them during the fork and the flush (if called explicitely) and lock them when an element is added.

Reviewers: marco-c

Reviewed By: marco-c

Subscribers: hiraditya, cfe-commits, #sanitizers, llvm-commits, sylvestre.ledru

Tags: #clang, #sanitizers, #llvm

Differential Revision: https://reviews.llvm.org/D74953
The file was modifiedllvm/lib/Transforms/Instrumentation/GCOVProfiling.cpp
The file was modifiedcompiler-rt/lib/profile/GCDAProfiling.c
The file was modifiedclang/lib/Driver/ToolChains/Darwin.cpp
Commit 6e561d1c94edc2ecaab7b79f6b3f1a06f515d531 by bevin.hansson
[Intrinsic] Add fixed point saturating division intrinsics.

Summary:
This patch adds intrinsics and ISelDAG nodes for signed
and unsigned fixed-point division:

```
llvm.sdiv.fix.sat.*
llvm.udiv.fix.sat.*
```

These intrinsics perform scaled, saturating division
on two integers or vectors of integers. They are
required for the implementation of the Embedded-C
fixed-point arithmetic in Clang.

Reviewers: bjope, leonardchan, craig.topper

Subscribers: hiraditya, jdoerfert, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D71550
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
The file was modifiedllvm/lib/CodeGen/TargetLoweringBase.cpp
The file was modifiedllvm/include/llvm/IR/Intrinsics.td
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was modifiedllvm/include/llvm/Target/TargetSelectionDAG.td
The file was modifiedllvm/docs/LangRef.rst
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetLowering.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
The file was modifiedllvm/include/llvm/CodeGen/ISDOpcodes.h
The file was modifiedllvm/lib/IR/Verifier.cpp
The file was addedllvm/test/CodeGen/X86/sdiv_fix_sat.ll
The file was addedllvm/test/CodeGen/X86/udiv_fix_sat.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
Commit bc1947a6f51fec9239248043d1a85afa3ce586aa by benny.kra
Add a basic tiling pass for parallel loops

This exploits the fact that the iterations of parallel loops are
independent so tiling becomes just an index transformation. This pass
only tiles the innermost loop of a loop nest.

The ultimate goal is to allow vectorization of the tiled loops, but I
don't think we're there yet with the current rewriting, as the tiled
loops don't have a constant trip count.

Differential Revision: https://reviews.llvm.org/D74954
The file was modifiedmlir/lib/Dialect/LoopOps/Transforms/CMakeLists.txt
The file was modifiedmlir/include/mlir/Dialect/LoopOps/Passes.h
The file was addedmlir/test/Dialect/Loops/parallel-loop-tiling.mlir
The file was modifiedmlir/include/mlir/InitAllPasses.h
The file was addedmlir/lib/Dialect/LoopOps/Transforms/ParallelLoopTiling.cpp
Commit 3ac37eb9a93a4009f58c29497aa141fc103f4c45 by benny.kra
Silence compiler warnings

mlir/lib/Parser/Parser.cpp:4484:15: warning: 'parseAssignmentList' overrides a member function but is not marked 'override' [-Winconsistent-missing-override]
  ParseResult parseAssignmentList(SmallVectorImpl<OperandType> &lhs,
              ^
mlir/include/mlir/IR/OpImplementation.h:662:3: note: overridden virtual function is here
  parseAssignmentList(SmallVectorImpl<OperandType> &lhs,
  ^
mlir/lib/Parser/Parser.cpp:4488:12: warning: unused variable 'type' [-Wunused-variable]
      Type type;
           ^
The file was modifiedmlir/lib/Parser/Parser.cpp
Commit f2ff153401fa894844e1f365697e58297d328207 by kerry.mclaughlin
[AArch64][SVE] Add intrinsics for SVE2 cryptographic instructions

Summary:
Implements the following SVE2 intrinsics:
- @llvm.aarch64.sve.aesd
- @llvm.aarch64.sve.aesimc
- @llvm.aarch64.sve.aese
- @llvm.aarch64.sve.aesmc
- @llvm.aarch64.sve.rax1
- @llvm.aarch64.sve.sm4e
- @llvm.aarch64.sve.sm4ekey

Reviewers: sdesmalen, c-rhodes, dancgr, cameron.mcinally, efriedma, rengolin

Reviewed By: sdesmalen

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cfe-commits, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74833
The file was modifiedllvm/include/llvm/IR/IntrinsicsAArch64.td
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
The file was addedllvm/test/CodeGen/AArch64/sve2-intrinsics-crypto.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
Commit 8c893cac3f65cecf5b5a05dc32cfbfe4b82cc8e0 by benny.kra
[ORC] Remove spammy debug print
The file was modifiedllvm/lib/ExecutionEngine/Orc/RTDyldObjectLinkingLayer.cpp
Commit a4370b2ec4624c8aceb2754cf916b98c2bfc1914 by kbobyrev
Use temporary directory for tests in D74346
The file was modifiedllvm/test/Other/cfg_deopt_unreach.ll
Commit eaa41e103c568a3f97039fe64c89baa7e9b085ca by llvm-dev
[CostModel][X86] Try to check against common prefixes before using target-specific cpu checks

SLM/GLM is still a mess so not all of them have been updated yet.
The file was modifiedllvm/test/Analysis/CostModel/X86/div.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/arith-usat.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/vshift-shl-cost.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/vshift-lshr-cost.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/arith-fix.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/fcmp.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/arith.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/fshl.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/shuffle-broadcast.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/trunc.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/sitofp.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/uitofp.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/rem.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/arith-fp.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/fshr.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/fptosi.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/shuffle-transpose.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/vector-extract.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/shuffle-extract_subvector.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/alternate-shuffle-cost.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/shuffle-two-src.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/arith-ssat.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/shuffle-reverse.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/shuffle-insert_subvector.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/vector-insert.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/arith-overflow.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/icmp.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/fround.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/extend.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/shuffle-single-src.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/vshift-ashr-cost.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/fptoui.ll
Commit f287bb8cf5e48a22b5d1be47da803f73c5aa8186 by david.green
[ARM] FP16 bitcast test. NFC
The file was addedllvm/test/CodeGen/ARM/fp16-bitcast.ll
Commit 12fed51c0807b0727f9eecdd3dcf774a82fa7ecd by mikhail.maltsev
[ARM,MVE] Remove 64-bit variants of vbrsrq* intrinsics

Summary:
According to the ACLE the vbrsrq* intrinsics don't accept vectors
with 64-bit elements (and neither does the corresponding VBRSR
instruction).

Reviewers: simon_tatham, dmgreen, MarkMurrayARM, ostannard

Reviewed By: simon_tatham

Subscribers: kristof.beyls, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D75038
The file was modifiedclang/include/clang/Basic/arm_mve.td
Commit bd5b22070b6984d89c13b6cf38c3e54fc98ce291 by aaron
Fix TryParsePtrOperatorSeq.

The syntax rules for ptr-operator allow attributes after *, &,
&&, therefore we should be able to parse the following:

void fn() {
    void (*[[attr]] x)() = &fn;
    void (&[[attr]] y)() = fn;
    void (&&[[attr]] z)() = fn;
}
However the current logic in TryParsePtrOperatorSeq does not consider
the presence of attributes leading to unexpected parsing errors.

Moreover we should also consider _Atomic a possible qualifier that can
appear after the sequence of attribute specifiers.
The file was modifiedclang/test/Parser/cxx-attributes.cpp
The file was modifiedclang/lib/Parse/ParseTentative.cpp
The file was modifiedclang/test/Parser/cxx-ambig-decl-expr.cpp
The file was modifiedclang/test/CXX/dcl.decl/p4-0x.cpp
The file was modifiedclang/include/clang/Parse/Parser.h
Commit a67eb221e2281350eeab5dd4b9119895c500674c by sam.parker
[RDA][ARM][LowOverheadLoops] Iteration count IT blocks

Change the way that we remove the redundant iteration count code in
the presence of IT blocks. collectLocalKilledOperands has been
introduced to scan an instructions operands, collecting the killed
instructions and then visiting them too. This is used to delete the
code in the preheader which calculates the iteration count. We also
track any IT blocks within the preheader and, if we remove all the
instructions from the IT block, we also remove the IT instruction.
isSafeToRemove is used to remove any redundant uses of the iteration
count within the loop body.

Differential Revision: https://reviews.llvm.org/D74975
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain.mir
The file was modifiedllvm/lib/CodeGen/ReachingDefAnalysis.cpp
The file was modifiedllvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
The file was modifiedllvm/include/llvm/CodeGen/ReachingDefAnalysis.h
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-ignore-vctp.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-itercount.mir
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-random.mir
Commit f87f23c81caeb0b0b7b8e795023b7273a13115d2 by kerry.mclaughlin
[AArch64][SVE] Add the SVE dupq_lane intrinsic

Summary:
Implements the @llvm.aarch64.sve.dupq.lane intrinsic.

As specified in the ACLE, the behaviour of:
  svdupq_lane_u64(data, index)

...is identical to:
  svtbl(data, svadd_x(svptrue_b64(),
                      svand_x(svptrue_b64(), svindex_u64(0, 1), 1),
                      index * 2))

If the index is in the range [0,3], the operation is equivalent
to a single DUP (.q) instruction.

Reviewers: sdesmalen, c-rhodes, cameron.mcinally, efriedma, dancgr, rengolin

Reviewed By: sdesmalen

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cfe-commits, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74734
The file was modifiedllvm/include/llvm/IR/IntrinsicsAArch64.td
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
Commit 7efabe5c7de46fe190638741c6ee81ae13255e38 by sjoerd.meijer
[MIR][ARM] MachineOperand comments

This adds infrastructure to print and parse MIR MachineOperand comments.
The motivation for the ARM backend is to print condition code names instead of
magic constants that are difficult to read (for human beings). For example,
instead of this:

  dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14, $noreg
  t2Bcc %bb.4, 0, killed $cpsr

we now print this:

  dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14 /* CC::always */, $noreg
  t2Bcc %bb.4, 0 /* CC:eq */, killed $cpsr

This shows that MachineOperand comments are enclosed between /* and */. In this
example, the EOR instruction is not conditionally executed (i.e. it is "always
executed"), which is encoded by the 14 immediate machine operand. Thus, now
this machine operand has /* CC::always */ as a comment. The 0 on the next
conditional branch instruction represents the equal condition code, thus now
this operand has /* CC:eq */ as a comment.

As it is a comment, the MI lexer/parser completely ignores it. The benefit is
that this keeps the change in the lexer extremely minimal and no target
specific parsing needs to be done. The changes on the MIPrinter side are also
minimal, as there is only one target hooks that is used to create the machine
operand comments.

Differential Revision: https://reviews.llvm.org/D74306
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vmaxmin_vpred_r.mir
The file was modifiedllvm/lib/CodeGen/MIRPrinter.cpp
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/thumb-select-select.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-1.mir
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/t2-teq-reduce.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-liveout.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir
The file was modifiedllvm/lib/CodeGen/MIRParser/MILexer.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir
The file was modifiedllvm/test/CodeGen/ARM/load_store_opt_reg_limit.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir
The file was modifiedllvm/test/CodeGen/ARM/vldm-liveness.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-16.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/out-of-range-cbz.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix-debug.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri12.mir
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/select-pkhbt.mir
The file was modifiedllvm/test/CodeGen/ARM/fpoffset_overflow.mir
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/thumb-select-br.mir
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vpt-3-blocks-kill-vpr.mir
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vpt-block-4-ins.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-use-after.mir
The file was modifiedllvm/test/CodeGen/MIR/ARM/bundled-instructions.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-random.mir
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/select-clz.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-32.mir
The file was modifiedllvm/test/CodeGen/ARM/ifcvt_simple_bad_zero_prob_succ.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-operand-liveout.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-add-operand-liveout.mir
The file was modifiedllvm/test/CodeGen/ARM/ifcvt_triangleWoCvtToNextEdge.mir
The file was modifiedllvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-opcode-liveout.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-load.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-lr-terminator.mir
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The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/arm-select-globals-ropi-rwpi.mir
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The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vmldava_in_vpt.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-liveout-lsr-shift.mir
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vpt-2-blocks.mir
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/arm-select-copy_to_regclass-of-fptosi.mir
The file was modifiedllvm/test/CodeGen/ARM/tail-dup-bundle.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-ignore-vctp.mir
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll
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The file was modifiedllvm/test/CodeGen/Thumb2/ifcvt-cbz.mir
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The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subi3.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-cbnz.mir
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The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp16-reduce.mir
The file was modifiedllvm/test/CodeGen/ARM/constant-islands-cfg.mir
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The file was modifiedllvm/test/CodeGen/ARM/peephole-phi.mir
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The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir
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The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
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The file was modifiedllvm/include/llvm/CodeGen/TargetInstrInfo.h
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir
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The file was modifiedllvm/test/CodeGen/ARM/register-scavenger-exceptions.mir
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/irtranslator-varargs-lowering.ll
The file was modifiedllvm/test/CodeGen/ARM/expand-pseudos.mir
The file was modifiedllvm/test/CodeGen/Thumb2/peephole-cmp.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-itercount.mir
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The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/disjoint-vcmp.mir
The file was modifiedllvm/test/CodeGen/ARM/ifcvt_diamond_unanalyzable.mir
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vpt-preuse.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update2.mir
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The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-chain.mir
The file was modifiedllvm/test/DebugInfo/MIR/ARM/live-debug-values-reg-copy.mir
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vpt-block-2-ins.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir
The file was modifiedllvm/test/CodeGen/ARM/tst-peephole.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-2.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt-2.mir
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/select-fp-const.mir
The file was modifiedllvm/test/CodeGen/ARM/constant-islands-split-IT.mir
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-2-preds.mir
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/thumb-select-arithmetic-ops.mir
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The file was modifiedllvm/test/CodeGen/ARM/cmp1-peephole-thumb.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-store.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-8.mir
The file was modifiedllvm/test/CodeGen/Thumb2/mve-stacksplot.mir
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vpt-block-1-ins.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri.mir
The file was modifiedllvm/test/CodeGen/ARM/ifcvt_forked_diamond_unanalyzable.mir
The file was modifiedllvm/test/CodeGen/ARM/regcoal-invalid-subrange-update.mir
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/thumb-select-imm.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/add_reduce.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-liveout.mir
The file was modifiedllvm/test/CodeGen/Thumb2/fp16-stacksplot.mir
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The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-debug.mir
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The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-3.mir
The file was modifiedllvm/test/CodeGen/ARM/machine-copyprop.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-2.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-prev-iteration.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-def-no-mov.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/extract-element.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/wlstp.mir
The file was modifiedllvm/test/CodeGen/ARM/ifcvt_triangleSameCvtNext.mir
Commit b82438872b1f88feb393d5651bdfacb89bd2f8fa by llvm-dev
[CostModel][X86] We don't need a scale factor for SLM extract costs

D74976 will handle larger vector types, but since SLM doesn't support AVX+ then we will always be extracting from 128-bit vectors so don't need to scale the cost.
The file was modifiedllvm/test/Analysis/CostModel/X86/shuffle-extract_subvector.ll
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/alternate-cast.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/vector-extract.ll
Commit c8dadac228b7dd3a71d5fc25489d1b884a2b0f5e by melanie.blower
add release notes for ffp-model and ffp-exception-behavior
The file was modifiedclang/docs/ReleaseNotes.rst
Commit 8bee52bdb54a51ccfe1eb6c6ed5077132c2950a1 by Xiangling.Liao
[AIX][Frontend] C++ ABI customizations for AIX boilerplate

This PR enables "XL" C++ ABI in frontend AST to IR codegen. And it is driven by
static init work. The current kind in Clang by default is Generic Itanium, which
has different behavior on static init with IBM xlclang compiler on AIX.

Differential Revision: https://reviews.llvm.org/D74015
The file was modifiedclang/lib/CodeGen/ItaniumCXXABI.cpp
The file was modifiedclang/include/clang/Basic/TargetCXXABI.h
The file was modifiedclang/lib/AST/ASTContext.cpp
The file was modifiedclang/lib/Basic/Targets/OSTargets.h
The file was modifiedclang/lib/CodeGen/CodeGenModule.cpp
The file was addedclang/test/CodeGen/static-init.cpp
Commit d66d25f83824e2d72e06bf0813cc9e9e564dd74c by a.bataev
[OpenMP] Refactor the analysis in checkMapClauseBaseExpression using StmtVisitor class.

Summary: This step is the preparation of allowing lvalue in map/motion clause.

Reviewers: ABataev, jdoerfert

Reviewed By: ABataev

Subscribers: guansong, cfe-commits

Tags: #clang, #openmp

Differential Revision: https://reviews.llvm.org/D74970
The file was modifiedclang/lib/Sema/SemaOpenMP.cpp
The file was modifiedclang/test/OpenMP/target_messages.cpp
Commit 54fa9ecd3088508b05b0c5b5cb52da8a3c188655 by Louis Dionne
[libc++] Implementation of C++20's P1135R6 for libcxx

Differential Revision: https://reviews.llvm.org/D68480
The file was addedlibcxx/test/std/thread/thread.latch/version.pass.cpp
The file was addedlibcxx/src/barrier.cpp
The file was modifiedlibcxx/src/include/apple_availability.h
The file was addedlibcxx/test/std/thread/thread.semaphore/binary.pass.cpp
The file was addedlibcxx/test/std/atomics/atomics.types.operations/atomics.types.operations.wait/atomic_wait.pass.cpp
The file was addedlibcxx/test/std/thread/thread.latch/try_wait.pass.cpp
The file was addedlibcxx/test/std/thread/thread.barrier/arrive_and_drop.pass.cpp
The file was addedlibcxx/test/std/thread/thread.semaphore/timed.pass.cpp
The file was modifiedlibcxx/www/cxx2a_status.html
The file was addedlibcxx/test/std/thread/thread.semaphore/try_acquire.pass.cpp
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The file was addedlibcxx/include/barrier
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The file was addedlibcxx/test/std/thread/thread.semaphore/version.pass.cpp
The file was addedlibcxx/test/std/thread/thread.barrier/max.pass.cpp
The file was modifiedlibcxx/test/libcxx/double_include.sh.cpp
The file was addedlibcxx/test/std/thread/thread.semaphore/max.pass.cpp
The file was modifiedlibcxx/include/__threading_support
The file was modifiedlibcxx/include/CMakeLists.txt
The file was addedlibcxx/include/latch
The file was addedlibcxx/test/std/thread/thread.barrier/version.pass.cpp
The file was addedlibcxx/src/atomic.cpp
The file was addedlibcxx/test/std/thread/thread.semaphore/release.pass.cpp
The file was modifiedlibcxx/include/atomic
The file was modifiedlibcxx/include/module.modulemap
The file was addedlibcxx/test/std/atomics/types.pass.cpp
The file was addedlibcxx/test/std/thread/thread.barrier/arrive_and_wait.pass.cpp
Commit 80e73f22956c532e581c280a7388cfa87cec98e8 by Louis Dionne
[libc++] Adapt a few things around the implementation of P1135R6

- Add the new symbols to the ABI list on Darwin
- Add XFAIL markup to the tests that require dylib support on older platforms
- Add availability markup for back-deployment
The file was modifiedlibcxx/test/std/thread/thread.latch/arrive_and_wait.pass.cpp
The file was modifiedlibcxx/test/std/thread/thread.barrier/arrive_and_wait.pass.cpp
The file was modifiedlibcxx/include/__config
The file was modifiedlibcxx/test/std/thread/thread.barrier/arrive.pass.cpp
The file was modifiedlibcxx/include/barrier
The file was modifiedlibcxx/test/std/thread/thread.barrier/arrive_and_drop.pass.cpp
The file was modifiedlibcxx/test/std/thread/thread.latch/try_wait.pass.cpp
The file was modifiedlibcxx/test/std/thread/thread.latch/count_down.pass.cpp
The file was modifiedlibcxx/lib/abi/CHANGELOG.TXT
The file was modifiedlibcxx/lib/abi/x86_64-apple-darwin.v1.abilist
The file was modifiedlibcxx/include/atomic
The file was modifiedlibcxx/test/std/thread/thread.semaphore/timed.pass.cpp
The file was modifiedlibcxx/test/std/thread/thread.semaphore/try_acquire.pass.cpp
The file was modifiedlibcxx/test/std/thread/thread.semaphore/release.pass.cpp
The file was modifiedlibcxx/test/std/atomics/atomics.types.operations/atomics.types.operations.wait/atomic_wait.pass.cpp
The file was modifiedlibcxx/test/std/thread/thread.semaphore/binary.pass.cpp
The file was modifiedlibcxx/test/std/thread/thread.semaphore/acquire.pass.cpp
The file was modifiedlibcxx/test/std/thread/thread.barrier/completion.pass.cpp
The file was modifiedlibcxx/lib/abi/x86_64-apple-darwin.v2.abilist
Commit c0087164175767bd22dc4336f48098c338aa8e7a by Louis Dionne
[libc++] Mark the C++03 version of std::function as deprecated

Summary: We want to eventually remove it.

Reviewers: EricWF

Subscribers: christof, jkorous, dexonsmith, libcxx-commits

Tags: #libc

Differential Revision: https://reviews.llvm.org/D74719
The file was modifiedlibcxx/include/__functional_03
Commit c9c09ef836b49dba0a6fc784f322a96a86a9b985 by pavel
[lldb/DWARF] Fix dwp search path in the separate-debug-file case

The convention is that the dwp file name is derived from the name of the
file holding the executable code, even if the linked portion of the
debug info is elsewhere (objcopy --only-keep-debug).
The file was modifiedlldb/test/Shell/helper/toolchain.py
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
The file was modifiedlldb/test/CMakeLists.txt
The file was addedlldb/test/Shell/SymbolFile/DWARF/dwp-separate-debug-file.cpp
Commit 8efc2f5723b0892d0518bdac441c674b7d850ac6 by sd.fertile
[PowerPC][AIX] Spill/restore the callee-saved condition register bits.

Extends the existing support for spilling and restoring the condition
register to the linkage area for 32-bit targets, and enables for AIX.

Differential Revision: https://reviews.llvm.org/D74349
The file was addedllvm/test/CodeGen/PowerPC/aix32-crsave.mir
The file was modifiedllvm/lib/Target/PowerPC/PPCFrameLowering.h
The file was modifiedllvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
The file was removedllvm/test/CodeGen/PowerPC/ppc64-alloca-crspill.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCFrameLowering.cpp
The file was addedllvm/test/CodeGen/PowerPC/alloca-crspill.ll
The file was modifiedllvm/test/CodeGen/PowerPC/ppc64-crsave.mir
The file was addedllvm/test/CodeGen/PowerPC/aix-crspill.ll
Commit 59d8d13c7ba3e7bc06afcb20ed535523c1ed47ce by llvm-dev
[X86] getTargetShuffleInputs - check that the source inputs are all the right size.

I'm hoping to begin improving shuffle combining across different vector sizes, but before that we must ensure that all existing getTargetShuffleInputs calls must bail if the inputs aren't the same size.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 406a54b65fff66719778d122294edc50efdddb43 by thakis
[gn build] (manually) merge 54fa9ecd308
The file was modifiedllvm/utils/gn/secondary/libcxx/src/BUILD.gn
Commit b21405d1cd088d7d7088479861fabd55f998bf6b by Louis Dionne
[libc++] Fix CI and Linux failures after landing D68480

- Avoid using C++11-and-later features in <atomic>:
  Historically, we've supported <atomic> in C++03, so we can't use C++11
  features in that header. This is something we really need to change,
  since our implementation of <atomic> is starting to accumulate technical
  debt because of that.
- Mark a test as unsupported on single threaded systems
- Add missing symbols to the Linux ABI list
The file was modifiedlibcxx/lib/abi/x86_64-unknown-linux-gnu.v1.abilist
The file was modifiedlibcxx/test/std/atomics/types.pass.cpp
The file was modifiedlibcxx/include/atomic
The file was modifiedlibcxx/include/__threading_support
Commit 453d54865aaeb029599aae59eb89cd6049c25ea3 by thakis
[gn build] remove -std=c++11 in libcxx build pending discussion in 80e73f2 review thread
The file was modifiedllvm/utils/gn/secondary/libcxx/src/BUILD.gn
Commit 0414c5694073de26fd33a0276c47c6adea5284cf by peter
Revert "Rework go bindings so that validation works fine"

And add llvm-go back to the test dependencies.

No longer necessary now that llvm-go has been brought back.

This reverts commit e8f8873da5eaad187f82dad78ebdb3ab3df22b36.
The file was removedllvm/bindings/go/src/llvm/IRBindings.h
The file was removedllvm/bindings/go/src/llvm/transforms_ipo.go
The file was addedllvm/bindings/go/llvm/IRBindings.h
The file was addedllvm/bindings/go/llvm/InstrumentationBindings.cpp
The file was removedllvm/bindings/go/src/llvm/transforms_coroutines.go
The file was removedllvm/bindings/go/src/llvm/string.go
The file was addedllvm/bindings/go/llvm/bitreader.go
The file was removedllvm/bindings/go/src/llvm/string_test.go
The file was addedllvm/bindings/go/llvm/string.go
The file was removedllvm/bindings/go/src/llvm/InstrumentationBindings.cpp
The file was addedllvm/bindings/go/llvm/transforms_scalar.go
The file was addedllvm/bindings/go/llvm/llvm_dep.go
The file was addedllvm/bindings/go/build.sh
The file was removedllvm/bindings/go/src/llvm/ir.go
The file was removedllvm/bindings/go/src/llvm/transforms_scalar.go
The file was addedllvm/bindings/go/llvm/SupportBindings.cpp
The file was addedllvm/bindings/go/llvm/ir_test.go
The file was addedllvm/bindings/go/llvm/version.go
The file was removedllvm/bindings/go/src/llvm/bitwriter.go
The file was removedllvm/bindings/go/src/llvm/version.go
The file was addedllvm/bindings/go/llvm/transforms_pmbuilder.go
The file was addedllvm/bindings/go/llvm/transforms_instrumentation.go
The file was removedllvm/bindings/go/src/llvm/SupportBindings.cpp
The file was removedllvm/bindings/go/src/llvm/ir_test.go
The file was removedllvm/bindings/go/src/llvm/llvm_dep.go
The file was removedllvm/bindings/go/src/llvm/target.go
The file was addedllvm/bindings/go/llvm/executionengine_test.go
The file was removedllvm/bindings/go/src/llvm/transforms_pmbuilder.go
The file was modifiedllvm/test/lit.cfg.py
The file was removedllvm/bindings/go/src/llvm/IRBindings.cpp
The file was addedllvm/bindings/go/llvm/dibuilder.go
The file was removedllvm/bindings/go/src/llvm/support.go
The file was addedllvm/bindings/go/llvm/bitwriter.go
The file was addedllvm/bindings/go/llvm/ir.go
The file was addedllvm/bindings/go/llvm/llvm_config.go.in
The file was removedllvm/bindings/go/src/llvm/SupportBindings.h
The file was modifiedllvm/test/CMakeLists.txt
The file was addedllvm/bindings/go/llvm/support.go
The file was addedllvm/bindings/go/llvm/target.go
The file was removedllvm/bindings/go/src/llvm/llvm_config.go.in
The file was removedllvm/bindings/go/src/llvm/linker.go
The file was modifiedllvm/test/Bindings/Go/go.test
The file was addedllvm/bindings/go/llvm/transforms_ipo.go
The file was addedllvm/bindings/go/llvm/executionengine.go
The file was addedllvm/bindings/go/llvm/transforms_coroutines.go
The file was addedllvm/bindings/go/llvm/string_test.go
The file was removedllvm/bindings/go/src/llvm/dibuilder.go
The file was modifiedllvm/test/Bindings/Go/lit.local.cfg
The file was addedllvm/bindings/go/llvm/linker.go
The file was addedllvm/bindings/go/llvm/InstrumentationBindings.h
The file was removedllvm/bindings/go/src/llvm/bitreader.go
The file was removedllvm/bindings/go/src/llvm/analysis.go
The file was removedllvm/bindings/go/src/llvm/transforms_instrumentation.go
The file was removedllvm/bindings/go/src/llvm/InstrumentationBindings.h
The file was removedllvm/bindings/go/src/llvm/executionengine.go
The file was addedllvm/bindings/go/llvm/SupportBindings.h
The file was removedllvm/bindings/go/src/llvm/executionengine_test.go
The file was modifiedllvm/utils/lit/lit/llvm/subst.py
The file was addedllvm/bindings/go/llvm/IRBindings.cpp
The file was addedllvm/bindings/go/llvm/analysis.go
Commit 400b6c083f846d51067fd72ed388485e1817c238 by sguelton
[NFC] Fix typo in error message
The file was modifiedllvm/lib/Object/COFFObjectFile.cpp
Commit a3d58fcc034848d751f031e7d3ddfe8cf9b8e06e by Louis Dionne
[libc++] Drop redundant check for -std=c++14

We always build all components of libc++ with -std=c++14 anyway
The file was modifiedlibcxx/src/CMakeLists.txt
Commit 3d65dd1e668ee681814f83e1423e4bee5d17ffb5 by francesco.petrogalli
[ReleaseNotes] Mention the `vector-function-abi-variant` attribute.

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74969
The file was modifiedllvm/docs/ReleaseNotes.rst
Commit 6369b9bf31188bdd472299252deb6db3f650864b by llvm-project
[CMake] Default to static linking for subprojects.

Pass plugins introduced in D61446 do not support dynamic linking on
Windows, hence the option LLVM_${name_upper}_LINK_INTO_TOOLS can only
work being set to "ON". Currently, it defaults to "OFF" such that such
plugins are inoperable by default on Windows. Change the default for
subprojects to follow LLVM_ENABLE_PROJECTS.

Reviewed By: serge-sans-paille, MaskRay

Differential Revision: https://reviews.llvm.org/D72372
The file was modifiedllvm/cmake/modules/AddLLVM.cmake
The file was modifiedpolly/lib/CMakeLists.txt
Commit bee70bfff0f41a1cea5010276cf4a6229c2c3b93 by jasonliu
[XCOFF][AIX] Fix incorrect alignment for function descriptor csect

Summary:
Function descriptor csect on AIX should be 4 byte align instead of 1 byte align.

Reviewer: daltenty

Differential Revision: https://reviews.llvm.org/D74974
The file was modifiedllvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
Commit a5424ded377ea5aeedf6de2a9293e4d1b3da02be by aykevanlaethem
[AVR] Use correct register class for mul instructions

A number of multiplication instructions (muls, mulsu, fmul, fmuls,
fmulsu) had the wrong register class for an operand. This resulted in
the wrong register being used for the instruction.

Example:

    target datalayout = "e-P1-p:16:8-i8:8-i16:8-i32:8-i64:8-f32:8-f64:8-n8-a:8"
    target triple = "avr-atmel-none"

    define i16 @sliceAppend(i16, i16, i16, i16, i16, i16) addrspace(1) {
      %d = mul i16 %0, %5
      ret i16 %d
    }

The first instruction would be muls r24, r31 before this patch. The r31
should have been r15 if you look at the intermediate forms during
instruction selection / register allocation, but the generated
instruction uses r31. After this patch, an extra movw is inserted to get
%5 in range for muls.

To make sure this bug is fixed everywhere, I checked all instructions
and found that most multiplication instructions suffered from this bug,
which I have fixed with this patch. No other instructions appear to be
affected.

Differential Revision: https://reviews.llvm.org/D74281
The file was modifiedllvm/lib/Target/AVR/AVRInstrInfo.td
Commit d1af6011e56b3d9fb94596d801f46b4c0a371c7a by aykevanlaethem
[AVR] Don't assert on an undefined operand

Not all operands are correctly disassembled at the moment. This means
that some machine instructions won't have all the necessary operands
set.
To avoid asserting, print an error instead until the necessary support
has been implemented.

Differential Revision: https://reviews.llvm.org/D73958
The file was modifiedllvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
Commit daac8dba77057950190f6c393b6c0aa902a5ab3b by llvm-dev
[X86] combineX86ShuffleChain - select X86ISD::FAND/ISD::AND based on MaskVT

Noticed by inspection, we shouldn't use FloatDomain directly, we've already bitcast both inputs to MaskVT so select the opcode using that.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 5b2046c95c6701f8c8509b78a12a700c012789eb by aykevanlaethem
[AVR] Disassemble register operands

Simply by implementing a few functions I was able to correctly
disassemble a much larger amount of instructions.

Differential Revision: https://reviews.llvm.org/D74045
The file was modifiedllvm/test/MC/AVR/inst-subi.s
The file was modifiedllvm/test/MC/AVR/inst-adc.s
The file was modifiedllvm/test/MC/AVR/inst-bst.s
The file was modifiedllvm/test/MC/AVR/inst-cpse.s
The file was modifiedllvm/test/MC/AVR/inst-mov.s
The file was modifiedllvm/test/MC/AVR/inst-clr.s
The file was modifiedllvm/test/MC/AVR/inst-ser.s
The file was modifiedllvm/test/MC/AVR/inst-cpi.s
The file was modifiedllvm/test/MC/AVR/inst-tst.s
The file was modifiedllvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
The file was modifiedllvm/test/MC/AVR/inst-add.s
The file was modifiedllvm/test/MC/AVR/inst-rol.s
The file was modifiedllvm/test/MC/AVR/inst-or.s
The file was modifiedllvm/test/MC/AVR/inst-and.s
The file was modifiedllvm/test/MC/AVR/inst-ori.s
The file was modifiedllvm/test/MC/AVR/inst-lsl.s
The file was modifiedllvm/test/MC/AVR/inst-sbiw.s
The file was modifiedllvm/test/MC/AVR/inst-bld.s
The file was modifiedllvm/test/MC/AVR/inst-cp.s
The file was modifiedllvm/test/MC/AVR/inst-adiw.s
The file was modifiedllvm/test/MC/AVR/inst-sbci.s
The file was modifiedllvm/test/MC/AVR/inst-ldi.s
The file was modifiedllvm/test/MC/AVR/inst-cbr.s
The file was modifiedllvm/test/MC/AVR/inst-sbr.s
The file was modifiedllvm/test/MC/AVR/inst-cpc.s
The file was modifiedllvm/test/MC/AVR/inst-sub.s
The file was modifiedllvm/test/MC/AVR/inst-andi.s
The file was modifiedllvm/test/MC/AVR/inst-eor.s
The file was modifiedllvm/test/MC/AVR/inst-sbc.s
Commit 00570c2f18872ce0a1f68cc73e7e259ad67aa60d by aykevanlaethem
[bindings/go] Add RemoveFromParentAsInstruction

This allows removing instructions without erasing them. They can then be
added somewhere else in the IR using Builder.Insert().
The file was modifiedllvm/bindings/go/llvm/ir.go
Commit 7b0a5683fa09be4e60bc93526aad7b63bbca687c by francisvm
[MachO] Add cpu(sub)type tests and improve error handling

Add checks for triples that don't use mach-o, and unit tests for
everything.
The file was modifiedllvm/lib/BinaryFormat/MachO.cpp
The file was modifiedllvm/unittests/BinaryFormat/MachOTest.cpp
Commit 53b597cfa2cd350704ac1708b1debd97ef027386 by llvm-dev
[SelectionDAG] Merge constant SDNode arithmetic into foldConstantArithmetic

This is the second patch as part of https://bugs.llvm.org/show_bug.cgi?id=36544

Merging in the ConstantSDNode variant of FoldConstantArithmetic. After this, I will begin merging in FoldConstantVectorArithmetic

I've ensured this patch can build & pass all lit tests in Windows and Linux environments.

Patch by @justice_adams (Justice Adams)

Differential Revision: https://reviews.llvm.org/D74881
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modifiedllvm/include/llvm/CodeGen/SelectionDAG.h
Commit 2a7a989c3edc33ad3042052ed50fee37ab254c7d by aykevanlaethem
[LLVM-C] Add bindings for addCoroutinePassesToExtensionPoints

This patch adds bindings to C and Go for
addCoroutinePassesToExtensionPoints, which is used to add coroutine
passes to the correct locations in PassManagerBuilder.

Differential Revision: https://reviews.llvm.org/D51642
The file was modifiedllvm/include/llvm-c/Transforms/Coroutines.h
The file was modifiedllvm/lib/Transforms/Coroutines/Coroutines.cpp
The file was modifiedllvm/include/llvm/Transforms/IPO/PassManagerBuilder.h
The file was modifiedllvm/lib/Transforms/IPO/PassManagerBuilder.cpp
The file was modifiedllvm/bindings/go/llvm/transforms_pmbuilder.go
Commit 8358ddbe5d32d9aaa371b3de69f4efabf309b450 by antiagainst
[mlir][spirv] NFC: Move test passes to test/lib

Previously C++ test passes for SPIR-V were put under
test/Dialect/SPIRV. Move them to test/lib/Dialect/SPIRV
to create a better structure.

Also fixed one of the test pass to use new
PassRegistration mechanism.

Differential Revision: https://reviews.llvm.org/D75066
The file was addedmlir/test/lib/Dialect/SPIRV/TestAvailability.cpp
The file was removedmlir/test/Dialect/CMakeLists.txt
The file was removedmlir/test/Dialect/SPIRV/CMakeLists.txt
The file was modifiedmlir/test/lib/CMakeLists.txt
The file was modifiedmlir/tools/mlir-opt/mlir-opt.cpp
The file was modifiedmlir/test/CMakeLists.txt
The file was addedmlir/test/lib/Dialect/CMakeLists.txt
The file was addedmlir/test/lib/Dialect/SPIRV/CMakeLists.txt
The file was removedmlir/test/Dialect/SPIRV/TestAvailability.cpp
Commit b61e83eb0e31c1e6006569b43bb98a61ff44ca4c by Raphael Isemann
[libc++] Give headers that require C++14 a cplusplus14 requires in the modulemap

https://reviews.llvm.org/D68480 added those headers and made the std module
only usable with C++14 or later as the submodules were not marked as requiring
C++14 or later. This just adds the missing requires directives.
The file was modifiedlibcxx/include/module.modulemap
Commit 4135077e2694435d675e64ff95f167b4e27ba5c7 by Stanislav.Mekhanoshin
[AMDGPU] use llvm_unreachable instead of default for rp set

GCC 9.2 seems to incorrectly issue warning about out of bounds
access. This situation should not happen in any way.

Differential Revision: https://reviews.llvm.org/D75071
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
Commit 727328433ad61b8c7acdd4d63e73241303a6beb7 by craig.topper
[X86] Add back fmaddsub intrinsics to work towards fixing the strict fp implementation

Previously we emitted an fmadd and a fmadd+fneg and combined them with a shufflevector. But this doesn't follow the correct exception behavior for unselected elements so the backend can't merge them into the fmaddsub/fmsubadd instructions.

This patch restores the the fmaddsub intrinsics so we don't have two arithmetic operations. We lose out on optimization opportunity in the non-strict FP case, but I don't think this is a big loss. If someone gives us a test case we can look into adding instcombine/dagcombine improvements. I'd rather not have the frontend do completely different things for strict and non-strict.

This still has problems because target specific intrinsics don't support strict semantics yet. We also still have all of the problems with masking. But we at least generate the right instruction in constrained mode now.

Differential Revision: https://reviews.llvm.org/D74268
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was modifiedclang/test/CodeGen/fma4-builtins.c
The file was modifiedllvm/lib/IR/AutoUpgrade.cpp
The file was modifiedllvm/lib/Target/X86/X86IntrinsicsInfo.h
The file was modifiedclang/test/CodeGen/fma-builtins.c
The file was modifiedclang/test/CodeGen/avx512vl-builtins.c
The file was modifiedclang/test/CodeGen/fma-builtins-constrained.c
The file was modifiedclang/test/CodeGen/avx512f-builtins.c
The file was modifiedllvm/include/llvm/IR/IntrinsicsX86.td