Started 1 mo 2 days ago
Took 4 hr 50 min on green-dragon-02

Failed Build #14906 (Oct 18, 2019 6:00:07 AM)

Revisions
  • http://llvm.org/svn/llvm-project/llvm/trunk : 375228
  • http://llvm.org/svn/llvm-project/cfe/trunk : 375224
  • http://llvm.org/svn/llvm-project/compiler-rt/trunk : 375220
  • http://llvm.org/svn/llvm-project/zorg/trunk : 375212
  • http://llvm.org/svn/llvm-project/libcxx/trunk : 374854
  • http://llvm.org/svn/llvm-project/clang-tools-extra/trunk : 375226
Changes
  1. [AArch64] Adding support for PMMIR_EL1 register

    Summary:
    The PMMIR_EL1 register is present in Armv8.4 with PMU extension.
    This patch adds support for it.

    Reviewers: t.p.northover, dnsampaio

    Reviewed By: dnsampaio

    Subscribers: kristof.beyls, hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D68940 (detail)
    by vhscampos
  2. [clangd] Report declaration references in findExplicitReferences.

    Reviewers: ilya-biryukov

    Subscribers: MaskRay, jkorous, arphaman, kadircet, usaxena95, cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D68977 (detail)
    by hokein
  3. [ThinLTOCodeGenerator] Add support for index-based WPD

    This is clang part of the patch. It adds -flto-unit flag for thin LTO
    builds on Mac and PS4

    Differential revision: https://reviews.llvm.org/D68950 (detail)
    by evgeny777
  4. [AArch64][SVE] Add SPLAT_VECTOR ISD Node

    Adds a new ISD node to replicate a scalar value across all elements of
    a vector. This is needed for scalable vectors, since BUILD_VECTOR cannot
    be used.

    Fixes up default type legalization for scalable vectors after the
    new MVT type ranges were introduced.

    At present I only use this node for scalable vectors. A DAGCombine has
    been added to transform a BUILD_VECTOR into a SPLAT_VECTOR if all
    elements are the same, but only if the default operation action of
    Expand has been overridden by the target.

    I've only added result promotion legalization for scalable vector
    i8/i16/i32/i64 types in AArch64 for now.

    Reviewers: t.p.northover, javed.absar, greened, cameron.mcinally, jmolloy

    Reviewed By: jmolloy

    Differential Revision: https://reviews.llvm.org/D47775 (detail)
    by huntergr
  5. [Arm][libsanitizer] Fix arm libsanitizer failure with bleeding edge glibc

    Glibc has recently introduced changed to the mode field in ipc_perm in commit
    2f959dfe849e0646e27403f2e4091536496ac0f0. For Arm this means that the mode
    field no longer has the same size.

    This causes an assert failure against libsanitizer's internal copy of ipc_perm.
    Since this change can't be easily detected I am adding arm to the list of
    targets that are excluded from this check.

    Patch by: Tamar Christina

    Differential Revision: https://reviews.llvm.org/D69104 (detail)
    by sjoerdmeijer
  6. [ThinLTOCodeGenerator] Add support for index-based WPD

    Differential revision: https://reviews.llvm.org/D68950 (detail)
    by evgeny777
  7. [AArch64] Don't combine callee-save and local stack adjustment when optimizing for size

    For arm64, D18619 introduced the ability to combine bumping the stack pointer
    upfront in case it needs to be bumped for both the callee-save area as well as
    the local stack area.

    That diff already remarks that "This change can cause an increase in
    instructions", but argues that even when that happens, it should be still be a
    performance benefit because the number of micro-ops is reduced.

    We have observed that this code-size increase can be significant in practice.
    This diff disables combining stack bumping for methods that are marked as
    optimize-for-size.

    Example of a prologue with the behavior before this diff (combining stack bumping when possible):
      sub        sp, sp, #0x40
      stp        d9, d8, [sp, #0x10]
      stp        x20, x19, [sp, #0x20]
      stp        x29, x30, [sp, #0x30]
      add        x29, sp, #0x30
      [... compute x8 somehow ...]
      stp        x0, x8, [sp]

    And after this  diff, if the method is marked as optimize-for-size:
      stp        d9, d8, [sp, #-0x30]!
      stp        x20, x19, [sp, #0x10]
      stp        x29, x30, [sp, #0x20]
      add        x29, sp, #0x20
      [... compute x8 somehow ...]
      stp        x0, x8, [sp, #-0x10]!

    Note that without combining the stack bump there are two auto-decrements,
    nicely folded into the stp instructions, whereas otherwise there is a single
    sub sp, ... instruction, but not folded.

    Patch by Nikolai Tillmann!

    Differential Revision: https://reviews.llvm.org/D68530 (detail)
    by dmgreen
  8. [X86] Regenerate memcmp tests and add X64-AVX512 common prefix

    Should help make the changes in D69157 clearer (detail)
    by rksimon
  9. Fix MSVC "not all control paths return a value" warning. NFCI. (detail)
    by rksimon
  10. Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warnings. NFCI. (detail)
    by rksimon
  11. Remove -DLLVM_USE_LINKER from Windows self host bots.

    LLVM_USE_LINKER sets the -fuse-ld. This is redundant as the linker is set to
    lld-link.

    Differential Revision: https://reviews.llvm.org/D69098 (detail)
    by russell_gallop
  12. [Codegen] Alter the default promotion for saturating adds and subs

    The default promotion for the add_sat/sub_sat nodes currently does:
        ANY_EXTEND iN to iM
        SHL by M-N
        [US][ADD|SUB]SAT
        L/ASHR by M-N

    If the promoted add_sat or sub_sat node is not legal, this can produce code
    that effectively does a lot of shifting (and requiring large constants to be
    materialised) just to use the overflow flag. It is simpler to just do the
    saturation manually, using the higher bitwidth addition and a min/max against
    the saturating bounds. That is what this patch attempts to do.

    Differential Revision: https://reviews.llvm.org/D68926 (detail)
    by dmgreen
  13. [AArch64][SVE] Implement unpack intrinsics

    Summary:
    Implements the following intrinsics:
      - int_aarch64_sve_sunpkhi
      - int_aarch64_sve_sunpklo
      - int_aarch64_sve_uunpkhi
      - int_aarch64_sve_uunpklo

    This patch also adds AArch64ISD nodes for UNPK instead of implementing
    the intrinsics directly, as they are required for a future patch which
    implements the sign/zero extension of legal vectors.

    This patch includes tests for the Subdivide2Argument type added by D67549

    Reviewers: sdesmalen, SjoerdMeijer, greened, rengolin, rovka

    Reviewed By: greened

    Subscribers: tschuett, kristof.beyls, rkruppe, psnobl, cfe-commits, llvm-commits

    Differential Revision: https://reviews.llvm.org/D67550 (detail)
    by kmclaughlin

Started by timer (4 times)

This run spent:

  • 3 hr 49 min waiting;
  • 4 hr 50 min build duration;
  • 8 hr 39 min total from scheduled to completion.

Identified problems

Assertion failure

This build failed because of an assertion failure. Below is a list of all errors in the build log:
Indication 1

Compile Error

This build failed because of a compile error. Below is a list of all errors in the build log:
Indication 2

Regression test failed

This build failed because a regression test in the test suite FAILed. See the test report for details.
Indication 3

Ninja target failed

Below is a link to the first failed ninja target.
Indication 4

Missing test results

The test result file Jenkins is looking for does not exist after the build.
Indication 5