FailedChanges

Summary

  1. [AArch64][GlobalISel] Select uzp1 and uzp2 (details)
  2. [Statepoint] Fix signed vs unsigned in index handling (details)
  3. Fix bug in newly added VersionBase::operator>= (details)
  4. [AArch64][GlobalISel] Add selection support for rev16, rev32, and rev64 (details)
  5. [WebAssembly] Fix ISel crash in SIGN_EXTEND_INREG lowering (details)
Commit 8dd34cce0716e0d83c2f05375e8352b5fb4c680c by Jessica Paquette
[AArch64][GlobalISel] Select uzp1 and uzp2

Porting the mask stuff for uzp1 and uzp2 from AArch64ISelLowering.

Add two custom opcodes: G_UZP1 and G_UZP2.

Produce them in the post-legalizer combiner when the mask checks out.

Tests:

- postlegalizer-combiner-uzp.mir verifies that we create G_UZP1 and G_UZP2.
The testcases that check that we create them come from neon-perm.ll.

- select-uzp.mir verifies that we can select G_UZP1 and G_UZP2.

Differential Revision: https://reviews.llvm.org/D81049
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrGISel.td
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-uzp.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64PostLegalizerCombiner.cpp
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/select-uzp.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64Combine.td
Commit ff529e0f2792e1383a602e4b8a466337fd0c2926 by listmail
[Statepoint] Fix signed vs unsigned in index handling

As noted in a comment on D80937, all of these are specified as unsigned values, but the verifier code was using signed.  Given the practical values involved, the different in range didn't matter, but we might as well clean it up.
The file was modifiedllvm/lib/IR/Verifier.cpp
Commit cab4b3b8e3a4a2822e459e5f103e49fcab16efaf by julian.lettner
Fix bug in newly added VersionBase::operator>=

Fixup for ba6b1b4353e33a7a36bcbad1d1c1157826197fd2.
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_mac.h
Commit 969d2d1ea9466143e7099040f5f0735cc81963b1 by Jessica Paquette
[AArch64][GlobalISel] Add selection support for rev16, rev32, and rev64

This does three things:

1) Adds G_REV16, G_REV32, and G_REV64. These are equivalent to AArch64rev16,
   AArch64rev32, and AArch64rev64 respectively.

2) Adds support for producing G_REV64 in the postlegalizer combiner.
   We don't legalize any of the shuffles which could give us a G_REV32 or
   G_REV16 yet. Since the function for detecting the rev mask is lifted from
   AArch64ISelLowering, it should work for G_REV32 and G_REV16 when we get
   there.

3) Adds a selection test for a good portion of the patterns imported for the rev
   family. The only ones which are not tested are the ones with bitconvert.

This also does a little cleanup, and adds a struct for shuffle vector pseudo
matchdata. This lets us still use `applyShuffleVectorPseudo` rather than adding
a new function.

It should also make it a bit easier to port some of the other masks from
AArch64ISelLowering. (e.g. `isZIP_v_undef_Mask` and friends)

Differential Revision: https://reviews.llvm.org/D81112
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-rev.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64PostLegalizerCombiner.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64Combine.td
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrGISel.td
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/select-rev.mir
Commit 25af2126f93a76f39c3121b3ddccdfd9f1aba4be by tlively
[WebAssembly] Fix ISel crash in SIGN_EXTEND_INREG lowering

Summary:
The code previously assumed that the index of a vector extract was
constant, but this was not always true. This patch fixes the problem
by bailing out of the lowering if the index is nonconstant and also
replaces `static_cast`s in the lowering function with `cast`s because
the latter contain type-checking asserts that would make similar
issues easier to find and debug.

Reviewers: aheejin

Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D81025
The file was addedllvm/test/CodeGen/WebAssembly/simd-nonconst-sext.ll
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp