Commit
3317b38ef86ecee1ae134f419a8ed0f4733444a3
by koraq[NFC][libc++] Update the implementation status.
During the review of https://reviews.llvm.org/D93912 we failed to notice
the implementation status wasn't updated. This rectifies the issue.
|
 | libcxx/docs/Cxx2bStatusPaperStatus.csv |
Commit
01defcc8d74e65f3d304274bc4ede44d838ff22b
by ravishankarm[mlir][Linalg] Extend tile+fuse to work on Linalg operation on tensors.
Differential Revision: https://reviews.llvm.org/D93086
|
| mlir/lib/Dialect/Linalg/Transforms/Fusion.cpp |
| mlir/include/mlir/Dialect/Linalg/Analysis/DependenceAnalysis.h |
| mlir/test/Dialect/Linalg/fusion-sequence.mlir |
| mlir/test/lib/Transforms/TestLinalgFusionTransforms.cpp |
| mlir/lib/Dialect/Linalg/Analysis/DependenceAnalysis.cpp |
Commit
73de3df1d28523dbd67dd54594480d126e27b559
by jpienaarAdd more explicit assert for failures
Differential Revision: https://reviews.llvm.org/D95201
|
| mlir/lib/IR/BuiltinTypes.cpp |
Commit
faa440786ccf0c2846385c882426d207acbab49c
by Louis Dionne[libc++] Bring back mach_absolute_time implementation of steady_clock
This is meant to unblock Chrome, as discussed in https://llvm.org/D74489.
Differential Revision: https://reviews.llvm.org/D95177
|
| libcxx/src/chrono.cpp |
Commit
45b259f99509dda6820e09369d84c21d4ea33bcd
by nikita.ppv[SimplifyLibCalls] Skip unused calls in sincos transform
If the call result is unused, we should let it get DCEd rather
than replacing it. Also, don't try to replace an existing sincos
with another one (unless it's as part of combining sin and cos).
This avoids an infinite combine loop if the calls are not DCEd
as expected, which can happen with D94106 and lack of willreturn
annotation in hand-crafted IR.
|
| llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp |
Commit
975086b10a6f1ce5a9b78783f085c0da454c30bc
by julian.lettnerRemove obsolete TODOs
Remove a few of my own TODOs that I will not have time to fix from lit
code.
|
| llvm/utils/lit/lit/cl_arguments.py |
Commit
29d420e0bf0273cdef35b2d2453f0f574d1e8313
by riddleriver[mlir][OpFormatGen] Add support for anchoring optional groups with types
This revision adds support for using either operand or result types to anchor an optional group. It also removes the arbitrary restriction that type directives must refer to variables in the same group, which is overly limiting for a declarative format syntax.
Fixes PR#48784
Differential Revision: https://reviews.llvm.org/D95109
|
| mlir/test/mlir-tblgen/op-format.mlir |
| mlir/test/mlir-tblgen/op-format-spec.td |
| mlir/tools/mlir-tblgen/OpFormatGen.cpp |
| mlir/docs/OpDefinitions.md |
| mlir/test/lib/Dialect/Test/TestOps.td |
Commit
72f863fd37c3471e7e1b152ac613da00ab6faaba
by bjorn.a.pettersson[CodeGen] Use getCharWidth() more consistently in CGRecordLowering. NFC
When using getByteArrayType the requested size is calculated in
char units, but the type used for the array was hardcoded to the
Int8Ty. This patch is using getCharWIdth a bit more consistently
by using getIntNTy in combination with getCharWidth, instead
of explictly using getInt8Ty.
Reviewed By: rjmccall
Differential Revision: https://reviews.llvm.org/D94977
|
| clang/lib/CodeGen/CGRecordLayoutBuilder.cpp |
Commit
ea2cfda386f1a0f0b8cab06a9400bbf4cf7bfbaa
by bjorn.a.pettersson[CGExpr] Use getCharWidth() more consistently in CCGExprConstant. NFC
Most of CGExprConstant.cpp is using the CharUnits abstraction
and is using getCharWidth() (directly of indirectly) when converting
between size of a char and size in bits. This patch is making that
abstraction more consistent by adding CharTy to the CodeGenTypeCache
(honoring getCharWidth() when mapping from char to LLVM IR types,
instead of using Int8Ty directly).
Reviewed By: rjmccall
Differential Revision: https://reviews.llvm.org/D94979
|
| clang/lib/CodeGen/CodeGenTypeCache.h |
| clang/lib/CodeGen/CGExprConstant.cpp |
| clang/lib/CodeGen/CodeGenModule.cpp |
Commit
b973e2e2f27ede7a70d470ea537f1901759d239d
by schuett[libc++] Introduce __bits
It has the low-level bit fiddling operations from bit. It eliminates a cyclic dependency between __bit_reference, bits, and vector. I want to exploit this in later patches.
Reviewed By: #libc, ldionne
Differential Revision: https://reviews.llvm.org/D94908
|
| libcxx/include/__bit_reference |
 | libcxx/include/__bits |
| libcxx/include/CMakeLists.txt |
| libcxx/include/bit |
| libcxx/include/module.modulemap |
Commit
42d682a217b6e04318d11d374e29d7d94ceaed1f
by aeubanks[NewPM][AMDGPU] Skip adding CGSCCOptimizerLate callbacks at O0
The legacy PM's EP_CGSCCOptimizerLate was only used under not-O0.
Fixes clang/test/CodeGenCXX/cxx0x-initializer-stdinitializerlist.cpp under the new PM.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D95250
|
| llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp |
Commit
9d2796210f71f95d0c62337c130a455694ce99a5
by nikita.ppv[Tests] Add willreturn to libcalls in some tests
Willreturn would be inferred by FuncAttrs for these. Annotate them
to preserve test behavior in the future.
|
| llvm/test/Transforms/InstSimplify/ConstProp/trunc.ll |
| llvm/test/Transforms/Attributor/nonnull.ll |
| llvm/test/Transforms/InstSimplify/ConstProp/calls-math-finite.ll |
| llvm/test/Transforms/InstSimplify/ConstProp/round.ll |
| llvm/test/Transforms/DCE/calls-errno.ll |
| llvm/test/Transforms/InstSimplify/ConstProp/calls.ll |
Commit
6aced6bf396b78b0021a224bf210ffc3598c3047
by craig.topper[RISCV] Rename pcnt->cpop to match 0.93 bitmanip spec.
This is the first of multiple patches to bring our 0.92
implementation up to 0.93.
Reviewed By: asb, frasercrmck
Differential Revision: https://reviews.llvm.org/D94568
|
| llvm/lib/Target/RISCV/RISCVInstrInfoB.td |
| llvm/test/CodeGen/RISCV/rv64Zbb.ll |
| llvm/test/CodeGen/RISCV/rv32Zbb.ll |
| llvm/test/MC/RISCV/rv32zbb-valid.s |
| llvm/test/MC/RISCV/rv64zbb-valid.s |
| llvm/test/MC/RISCV/rv32zbb-invalid.s |
| llvm/test/MC/RISCV/rv64zbb-invalid.s |
Commit
b2f859500f196f98a73d531c2ec847b7f23875af
by craig.topper[RISCV] Remove addiwu, addwu, subwu, subuw, clmulw, clmulrw, clmulhw to match 0.93 bitmanip spec.
Reviewed By: asb, frasercrmck
Differential Revision: https://reviews.llvm.org/D94577
|
 | llvm/test/MC/RISCV/rv64zbc-invalid.s |
| llvm/test/MC/RISCV/rv64zbb-invalid.s |
| llvm/test/MC/RISCV/rv64zbb-valid.s |
| llvm/test/MC/RISCV/rv64zbc-valid.s |
| llvm/test/CodeGen/RISCV/rv64Zbb.ll |
| llvm/lib/Target/RISCV/RISCVInstrInfoB.td |
Commit
d985c7321f0b9cbaf8f8423a7faa645bb5966fc8
by craig.topper[RISCV] Swap encodings of max and minu to match 0.93 bitmanip spec.
Reviewed By: asb, frasercrmck
Differential Revision: https://reviews.llvm.org/D94580
|
| llvm/test/MC/RISCV/rv32zbb-valid.s |
| llvm/lib/Target/RISCV/RISCVInstrInfoB.td |
Commit
b825278364d9551ec3e8eb9f776f722238c9b3d8
by craig.topper[RISCV] Rename mnemonics slliu.w->slli.uw and addu.w->add.uw to match 0.93 bitmanip spec.
Reviewed By: asb, frasercrmck
Differential Revision: https://reviews.llvm.org/D94582
|
| llvm/lib/Target/RISCV/RISCVInstrInfoB.td |
| llvm/test/MC/RISCV/rv64zbb-valid.s |
| llvm/test/MC/RISCV/rv64zbb-invalid.s |
| llvm/test/CodeGen/RISCV/rv64Zbb.ll |
Commit
4e6ad11bc6f29eecfbef7f5d5b7e581dd26e2024
by craig.topper[RISCV] Add Zba feature and move add.uw and slli.uw to it.
Still need to add SH*ADD instructions.
Reviewed By: asb, frasercrmck
Differential Revision: https://reviews.llvm.org/D94617
|
| clang/lib/Driver/ToolChains/Arch/RISCV.cpp |
| llvm/test/MC/RISCV/rv64zba-invalid.s |
| clang/test/Driver/riscv-arch.c |
| llvm/test/MC/RISCV/rv64zbb-invalid.s |
| llvm/test/MC/RISCV/rv64zbb-valid.s |
| llvm/test/CodeGen/RISCV/rv64Zbb.ll |
| llvm/test/CodeGen/RISCV/rv64Zba.ll |
| llvm/test/MC/RISCV/rv64zba-valid.s |
| llvm/lib/Target/RISCV/RISCV.td |
| llvm/lib/Target/RISCV/RISCVInstrInfoB.td |
| llvm/lib/Target/RISCV/RISCVSubtarget.h |
Commit
83a93ae63b1c8cc515a08c7fc4b78813e448c874
by craig.topper[RISCV] Add SH*ADD(.UW) instructions to Zba extension based on 0.93 bitmanip spec.
Reviewed By: asb, frasercrmck
Differential Revision: https://reviews.llvm.org/D94637
|
| llvm/test/MC/RISCV/rv64zba-invalid.s |
| llvm/test/MC/RISCV/rv32zba-invalid.s |
| llvm/test/MC/RISCV/rv64zba-valid.s |
| llvm/test/MC/RISCV/rv32zba-valid.s |
| llvm/lib/Target/RISCV/RISCVInstrInfoB.td |
Commit
1355458ef665b3044e3dfb57acf0c2e7439560fe
by craig.topper[RISCV] Move Shift Ones instructions from Zbb to Zbp to match 0.93 bitmanip spec.
It's not really clear in the spec that these are in Zbp now, but
that's what I've gather from previous commits to the spec. I've
file an issue to get it documented properly.
Reviewed By: asb, frasercrmck
Differential Revision: https://reviews.llvm.org/D94652
|
| llvm/test/MC/RISCV/rv64zbp-invalid.s |
| llvm/lib/Target/RISCV/RISCVInstrInfoB.td |
| llvm/test/MC/RISCV/rv64zbb-invalid.s |
| llvm/test/MC/RISCV/rv32zbp-valid.s |
| llvm/test/MC/RISCV/rv32zbb-invalid.s |
| llvm/test/MC/RISCV/rv32zbb-valid.s |
| llvm/test/MC/RISCV/rv64zbb-valid.s |
| llvm/test/CodeGen/RISCV/rv32Zbb.ll |
| llvm/test/MC/RISCV/rv32zbp-invalid.s |
| llvm/test/CodeGen/RISCV/rv64Zbp.ll |
| llvm/test/MC/RISCV/rv64zbp-valid.s |
| llvm/test/CodeGen/RISCV/rv32Zbp.ll |
| llvm/test/CodeGen/RISCV/rv64Zbb.ll |
Commit
efbcd66861dbfe4bb3c3c2d83515ca38bb7f18e2
by craig.topper[RISCV] Rename Zbs instructions to start with just 'b' instead of 'sb' to match 0.93 bitmanip spec.
Also renamed Zbe instructions to resolve name conflict even though
that change is in the 0.94 draft.
Reviewed By: asb, frasercrmck
Differential Revision: https://reviews.llvm.org/D94653
|
| llvm/test/MC/RISCV/rv32zbe-valid.s |
| llvm/test/CodeGen/RISCV/rv64Zbp.ll |
| llvm/test/CodeGen/RISCV/rv32Zbs.ll |
| llvm/test/CodeGen/RISCV/rv32Zbt.ll |
| llvm/test/MC/RISCV/rv64zbs-valid.s |
| llvm/test/MC/RISCV/rv32zbs-valid.s |
| llvm/test/CodeGen/RISCV/rv64Zbs.ll |
| llvm/test/MC/RISCV/rv64zbs-invalid.s |
| llvm/test/MC/RISCV/rv32zbe-invalid.s |
| llvm/lib/Target/RISCV/RISCVInstrInfoB.td |
| llvm/test/MC/RISCV/rv64zbe-valid.s |
| llvm/test/MC/RISCV/rv64zbe-invalid.s |
| llvm/test/MC/RISCV/rv32zbs-invalid.s |
Commit
9d499e037e6bc3365e6ad1423a388dc7a37627b0
by craig.topper[RISCV] Modify add.uw patterns to put the masked operand in rs1 to match 0.93 bitmanip spec.
The 0.93 spec has this implementation for add.uw
uint_xlen_t adduw(uint_xlen_t rs1, uint_xlen_t rs2) {
uint_xlen_t rs1u = (uint32_t)rs1;
return rs1u + rs2;
}
The 0.92 spec had the usages of rs1 and rs2 swapped.
Reviewed By: frasercrmck, asb
Differential Revision: https://reviews.llvm.org/D95090
|
| llvm/lib/Target/RISCV/RISCVInstrInfoB.td |
| llvm/test/CodeGen/RISCV/rv64Zba.ll |
Commit
5ae92f1e11ab4ee23dee32f5a637abbed7fe2dcc
by craig.topper[RISCV] Change zext.w to be an alias of add.uw rd, rs1, x0 instead of pack.
This didn't make it into the published 0.93 spec, but it was the
intention.
But it is in the tex source as of this commit
https://github.com/riscv/riscv-bitmanip/commit/d172f029c074d47026a0c0d0f12d8b475c86a472
This means zext.w now requires Zba. Not sure if we should still use
pack if Zbp is enabled and Zba isn't. I'll leave that for the future
when pack is closer to being final.
Reviewed By: asb, frasercrmck
Differential Revision: https://reviews.llvm.org/D94736
|
| llvm/lib/Target/RISCV/RISCV.td |
| llvm/lib/Target/RISCV/RISCVInstrInfo.td |
| llvm/lib/Target/RISCV/RISCVInstrInfoB.td |
| llvm/test/CodeGen/RISCV/rv64Zbbp.ll |
| llvm/test/CodeGen/RISCV/rv64Zba.ll |
| llvm/test/MC/RISCV/rv64b-aliases-valid.s |
Commit
83c92fdeda6be9a42739fa699926d41ce8a001fb
by craig.topper[RISCV] Move pack instructions to Zbp extension only.
Zext.h will need to come back to Zbb, but that only uses specific
encodings of pack.
Reviewed By: asb, frasercrmck
Differential Revision: https://reviews.llvm.org/D94742
|
| llvm/test/CodeGen/RISCV/rv64Zbbp.ll |
| llvm/test/CodeGen/RISCV/rv32Zbbp.ll |
| llvm/test/CodeGen/RISCV/rv32Zbp.ll |
| llvm/test/CodeGen/RISCV/rv64Zbp.ll |
| llvm/test/MC/RISCV/rv32zbp-invalid.s |
| llvm/lib/Target/RISCV/RISCVInstrInfoB.td |
| llvm/test/MC/RISCV/rv32zbbp-invalid.s |
| llvm/test/MC/RISCV/rv32zbp-valid.s |
| llvm/test/MC/RISCV/rv64zbbp-valid.s |
| llvm/test/MC/RISCV/rv32zbbp-valid.s |
| llvm/test/MC/RISCV/rv64zbp-valid.s |
Commit
3c94cee63b401ca12457395bb1f4d70e161f9ec4
by craig.topper[RISCV] Add zext.h instruction to Zbb.
zext.h uses the same encoding as pack rd, rs, x0 in rv32 and
packw rd, rs, x0 in rv64. Encodings without x0 as the second source
are not valid in Zbb.
I've added two new instructions with these specific encodings with
predicates that enable them when either Zbb or Zbp is enabled.
The pack spelling will only be accepted with Zbp. The disassembler
will use the zext.h instruction when either feature is enabled.
Using the pack spelling will print as pack when llvm-mc is
emitting text. We could fix this with some custom code in
processInstruction if this is important, but I'm not sure it is.
Reviewed By: asb, frasercrmck
Differential Revision: https://reviews.llvm.org/D94818
|
| llvm/test/CodeGen/RISCV/rv32Zbb.ll |
| llvm/test/CodeGen/RISCV/rv64Zbb.ll |
| llvm/test/MC/RISCV/rv32b-aliases-valid.s |
| llvm/test/MC/RISCV/rv64b-aliases-valid.s |
| llvm/lib/Target/RISCV/RISCV.td |
| llvm/lib/Target/RISCV/RISCVInstrInfoB.td |
| llvm/test/MC/RISCV/rv64zbb-valid.s |
| llvm/test/MC/RISCV/rv32zbb-valid.s |
| llvm/test/MC/RISCV/rv64zbp-valid.s |
| llvm/test/MC/RISCV/rv32zbp-valid.s |
Commit
4d5aa760a7d78b601fcfbda4d6196091a9188ea6
by craig.topper[RISCV] Add support for rev8 and orc.b to Zbb.
These instructions use a portion of the encodings for grevi and
gorci. The full encodings are only supported with Zbp. Note,
rev8 has a different encoding between rv32 and rv64.
Zbb is closer to being finalized that Zbp which has motivated
some decisions in this patch.
I'm treating rev8 and orc.b as separate instructions when
either Zbb or Zbp is enabled. This allows us to print to suggest
that either feature needs to be enabled to support these mnemonics.
I had tried to put HasStdExtZbbAndNotZbp on the Zbb instructions,
but that caused a diagnostic that said Zbp is required if neither
feature is enabled. We should really mention Zbb since its closer
to final.
This does require extra isel patterns for the different cases so
that bswap will always print as rev8 in assembly listing since
we can't use an InstAlias.
llvm-objdump disassembling should always pick the rev8 or orc.b
instructions. llvm-mc parsing and printing text will not convert
the grevi/gorci spellings to rev8/gorc.b. We could probably fix
this with a special case in processInstruction in the assembly
parser if it its important.
Reviewed By: asb, frasercrmck
Differential Revision: https://reviews.llvm.org/D94944
|
| llvm/test/CodeGen/RISCV/rv64Zbb.ll |
| llvm/test/MC/RISCV/rv32zbb-valid.s |
| llvm/test/MC/RISCV/rv64b-aliases-valid.s |
| llvm/test/MC/RISCV/rv32b-aliases-valid.s |
| llvm/lib/Target/RISCV/RISCVISelLowering.cpp |
| llvm/test/MC/RISCV/rv64zbp-valid.s |
| llvm/lib/Target/RISCV/RISCVInstrInfoB.td |
| llvm/test/MC/RISCV/rv64zbb-valid.s |
| llvm/test/MC/RISCV/rv32zbp-valid.s |
| llvm/test/CodeGen/RISCV/rv32Zbb.ll |
Commit
f25f7e8ecd914baf5bcc0f51cb893d5a696d85ff
by craig.topper[RISCV] Add xperm.* instructions to Zbp extension.
Reviewed By: asb, frasercrmck
Differential Revision: https://reviews.llvm.org/D94999
|
| llvm/test/MC/RISCV/rv32zbp-invalid.s |
| llvm/lib/Target/RISCV/RISCVInstrInfoB.td |
| llvm/test/MC/RISCV/rv64zbp-invalid.s |
| llvm/test/MC/RISCV/rv32zbp-valid.s |
| llvm/test/MC/RISCV/rv64zbp-valid.s |
Commit
20f2e32d2c545e6e23dc5c69c42caac7a4bca0fc
by craig.topper[RISCV] Update B extension version to 0.93.
Reviewed By: asb, frasercrmck
Differential Revision: https://reviews.llvm.org/D95002
|
| clang/test/Driver/riscv-arch.c |
| clang/test/Preprocessor/riscv-target-features.c |
| llvm/lib/Target/RISCV/RISCVInstrInfoB.td |
| clang/lib/Driver/ToolChains/Arch/RISCV.cpp |
Commit
430d43e010bdd07d73c4d0d6536206d22d35a2cb
by ravishankarm[mlir][Linalg] Disable fusion of tensor_reshape op by expansion when unit-dims are involved
Fusion of generic/indexed_generic operations with tensor_reshape by
expansion when the latter just adds/removes unit-dimensions is
disabled since it just adds unit-trip count loops.
Differential Revision: https://reviews.llvm.org/D94626
|
| mlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp |
| mlir/lib/Dialect/Linalg/Transforms/FusionOnTensors.cpp |
| mlir/test/Dialect/Linalg/drop-unit-extent-dims.mlir |
| mlir/test/Dialect/Linalg/reshape_fusion.mlir |
| mlir/include/mlir/Dialect/Linalg/Passes.h |
Commit
fdab28edef35dde906678cd3c3008dd116ea8572
by nikita.ppv[InstSimplify] Add willreturn to more libcall tests (NFC)
Annotate more math libcalls with willreturn. The attribute would
have been added by the InferFuncAttrs.
|
| llvm/test/Transforms/InstSimplify/ConstProp/math-1.ll |
| llvm/test/Transforms/InstSimplify/ConstProp/math-2.ll |
Commit
99a0aa07e9f4fa239b7927ede1847cfc78b16803
by froese[Analysis] Support AIX vec_malloc routines
This is to support the memory routines vec_malloc, vec_calloc, vec_realloc, and vec_free. These routines manage memory that is 16-byte aligned. And they are only available on AIX.
Differential Revision: https://reviews.llvm.org/D94710
|
| llvm/include/llvm/Analysis/TargetLibraryInfo.def |
| llvm/lib/Analysis/MemoryBuiltins.cpp |
| llvm/lib/Analysis/TargetLibraryInfo.cpp |
| llvm/unittests/Analysis/TargetLibraryInfoTest.cpp |
| llvm/lib/Transforms/Utils/BuildLibCalls.cpp |
Commit
095e245e164584b5de3c2938452b48d1f8ba4dda
by craig.topper[RISCV] Add isel patterns for SH*ADD(.UW)
This adds an initial set of patterns for these instructions. Its
more complicated that I would like for the sh*add.uw instructions
because there is no guaranteed canonicalization for shl/and with
constants.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D95106
|
| llvm/test/CodeGen/RISCV/rv32Zba.ll |
| llvm/lib/Target/RISCV/RISCVInstrInfoB.td |
| llvm/test/CodeGen/RISCV/rv64Zba.ll |
Commit
d6c763e0985fb69ceec4d2d3cebfc1910f8cc58d
by flo[Inline] Precommit tests for dead calls and willreturn.
precommit tests for D94106.
|
| llvm/test/Transforms/Inline/dead-calls-willreturn.ll |
Commit
083088d136baa93650a36d018d2a50717de0df9d
by llvmgnsyncbot[gn build] Port 622eaa4a4cea
|
| llvm/utils/gn/secondary/llvm/lib/IR/BUILD.gn |
Commit
041f3ee664c925148d1cfe48976ae671a660c949
by jezng[lld-macho] Ignore -lto_library
Just getting rid of some logspew as I test LLD under existing build
systems.
Reviewed By: #lld-macho, smeenai
Differential Revision: https://reviews.llvm.org/D95213
|
| lld/MachO/Options.td |
| lld/test/MachO/silent-ignore.test |
Commit
607e5a5000bddec24061b54a7e7955d51fe0d049
by craig.topper[RISCV] Add B extension tests to make sure RV64 only instructions aren't accepted in RV32.
Add tests to make sure common instructions are accepted in RV64
and not just RV32.
Reviewed By: asb, frasercrmck
Differential Revision: https://reviews.llvm.org/D95150
|
| llvm/test/MC/RISCV/rv32zba-invalid.s |
| llvm/test/MC/RISCV/rv32zbbp-invalid.s |
| llvm/test/MC/RISCV/rv32zbs-invalid.s |
| llvm/test/MC/RISCV/rv32zbb-invalid.s |
| llvm/test/MC/RISCV/rv64zbr-valid.s |
| llvm/test/MC/RISCV/rv64zbb-valid.s |
| llvm/test/MC/RISCV/rv32zbproposedc-invalid.s |
| llvm/test/MC/RISCV/rv64zbc-valid.s |
| llvm/test/MC/RISCV/rv64zbe-valid.s |
| llvm/test/MC/RISCV/rv64zba-valid.s |
| llvm/test/MC/RISCV/rv32zbe-invalid.s |
| llvm/test/MC/RISCV/rv64zbt-valid.s |
| llvm/test/MC/RISCV/rv32zbf-invalid.s |
| llvm/test/MC/RISCV/rv32zbp-invalid.s |
| llvm/test/MC/RISCV/rv64zbs-valid.s |
| llvm/test/MC/RISCV/rv32zbr-invalid.s |
| llvm/test/MC/RISCV/rv64zbproposedc-valid.s |
| llvm/test/MC/RISCV/rv32zbt-invalid.s |
| llvm/test/MC/RISCV/rv64zbbp-valid.s |
| llvm/test/MC/RISCV/rv64zbf-valid.s |
| llvm/test/MC/RISCV/rv64zbp-valid.s |
Commit
2bb92bf451d7eb2c817f3e5403353e7c0c14d350
by Amara Emerson[GlobalISel] LegalizerHelper - Extract widenScalarAddoSubo method
The widenScalar implementation for signed and unsigned overflowing
operations were very similar: both are checked by truncating the result
and then re-sign/zero-extending it and checking that it matches the
computed operation.
Using a truncate + zero-extend for the unsigned case instead of manually
producing the AND instruction like before leads to an extra copy
instruction during legalization, but this should be harmless.
Differential Revision: https://reviews.llvm.org/D95035
|
| llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp |
| llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp |
| llvm/test/CodeGen/AArch64/legalize-uaddo.mir |
| llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h |
| llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir |
| llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir |
| llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir |
| llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir |
Commit
0be9ca7c0f9a733f846bb6bc4e8e36d46b518162
by Jonas Devlieghere[VFS] Fix inconsistencies between relative paths and fallthrough.
This patch addresses inconsistencies in the way fallthrough is handled
in the RedirectingFileSystem. Rather than trying to change the working
directory of the external filesystem, the RedirectingFileSystem will
canonicalize every path before handing it down. This guarantees that
relative paths are resolved relative to the RedirectingFileSystem's
working directory.
This allows us to have a strictly virtual working directory, and still
fallthrough for absolute paths, but not for relative paths that would
get resolved incorrectly at the lower layer (for example, in case of the
RealFileSystem, because the strictly virtual path does not exist).
Differential revision: https://reviews.llvm.org/D95188
|
| llvm/lib/Support/VirtualFileSystem.cpp |
| llvm/include/llvm/Support/VirtualFileSystem.h |
| llvm/unittests/Support/VirtualFileSystemTest.cpp |
Commit
9bd8bcf993f6e829b2417deefbab78c610436a11
by lebedev.ri[NFC][SimplifyCFG] PerformBranchToCommonDestFolding(): fix instruction name preservation
NewBonusInst just took name from BonusInst, so BonusInst has no name,
so BonusInst.getName() makes no sense.
So we need to ask NewBonusInst for the name.
|
| llvm/lib/Transforms/Utils/SimplifyCFG.cpp |
| llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest.ll |
Commit
e8387500059e7f3c261b2127a241b2c4c81ab36b
by lebedev.ri[NFC][SimplifyCFG] fold-branch-to-common-dest.ll: reduce complexity of @pr48450* test
We don't need that many iterations there,
having less iterations helps alive2 verify it.
|
| llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest.ll |
Commit
eae1cc0de5b9c3b97ce1b6f4275b474ab10b83d0
by lebedev.ri[NFC][SimplifyCFG] PerformBranchToCommonDestFolding(): move instruction cloning to after CFG update
This simplifies follow-up patch, and is NFC otherwise.
|
| llvm/lib/Transforms/Utils/SimplifyCFG.cpp |
Commit
17422038442c9e2b572c7324b5a22d32e7fd9b83
by lebedev.ri[SimplifyCFG] FoldBranchToCommonDest(): re-lift restrictions on liveout uses of bonus instructions
I have previously tried doing that in
b33fbbaa34f0fe9fb16789afc72ae424c1825b69 / d38205144febf4dc42c9270c6aa3d978f1ef65e1,
but eventually it was pointed out that the approach taken there
was just broken wrt how the uses of bonus instructions are updated
to account for the fact that they should now use either bonus instruction
or the cloned bonus instruction. In particluar, all that manual handling
of PHI nodes in successors was just wrong.
But, the fix is actually much much simpler than my initial approach:
just tell SSAUpdate about both instances of bonus instruction,
and let it deal with all the PHI handling.
Alive2 confirms that the reproducers from the original bugs (@pr48450*)
are now handled correctly.
This effectively reverts commit 59560e85897afc50090b6c3d920bacfd28b49d06,
effectively relanding b33fbbaa34f0fe9fb16789afc72ae424c1825b69.
|
| llvm/test/Transforms/LoopUnroll/peel-loop-inner.ll |
| llvm/test/CodeGen/Thumb2/mve-float16regloops.ll |
| llvm/lib/Transforms/Utils/SimplifyCFG.cpp |
| llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll |
| llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest.ll |
| llvm/test/CodeGen/Thumb2/mve-float32regloops.ll |
Commit
554b3211fefd09b56b64357b9edd66c78ae200b5
by 31459023+hctimRevert "[GlobalISel] LegalizerHelper - Extract widenScalarAddoSubo method"
This reverts commit 2bb92bf451d7eb2c817f3e5403353e7c0c14d350.
Dependent patch broke UBSan on Android:
3dedad475da45c05bc4f66cd14e9f44581edf0bc
|
| llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h |
| llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp |
| llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp |
| llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir |
| llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir |
| llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir |
| llvm/test/CodeGen/AArch64/legalize-uaddo.mir |
| llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir |
Commit
e3a7532cc95ea0b7f748793db44caa95a92ad6d8
by 31459023+hctimRevert "[AArch64][GlobalISel] Implement widenScalar for signed overflow"
This reverts commit 541d98efa222b00e16c67348810898c2fa11f398.
Reason: Dependent patch 3dedad475da45c05bc4f66cd14e9f44581edf0bc broke
UBSan on Android: http://lab.llvm.org:8011/#/builders/77/builds/3082
|
| llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp |
| llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir |
| llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir |
Commit
19ec559c665e6490480cfdff9982b2c32a432b78
by 31459023+hctimRevert "[AArch64][GlobalISel] Make G_USUBO legal and select it."
This reverts commit 3dedad475da45c05bc4f66cd14e9f44581edf0bc.
Broke UBSan on Android:
http://lab.llvm.org:8011/#/builders/77/builds/3082
More details at: https://reviews.llvm.org/D95032
|
| llvm/test/CodeGen/AArch64/GlobalISel/select-usubo.mir |
| llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp |
| llvm/test/CodeGen/AArch64/GlobalISel/select-saddo.mir |
| llvm/test/CodeGen/AArch64/GlobalISel/select-ssubo.mir |
| llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir |
| llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp |
| llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir |
| llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir |
Commit
0cc38acfc4e1dcdc2a9b6287bc93eef57acfd105
by francisvm[Matrix] Propagate shape information through fneg
Similar to binary operators like fadd/fmul/fsub, propagate shape info
through unary operators (fneg is the only one?).
Differential Revision: https://reviews.llvm.org/D95252
|
| llvm/test/Transforms/LowerMatrixIntrinsics/propagate-forward.ll |
| llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp |
| llvm/test/Transforms/LowerMatrixIntrinsics/propagate-backward.ll |
Commit
6e8ef3b76ab65960edd6ee99f387e75564d8d9db
by ravishankarm[mlir][Linalg] Make Fill operation work on tensors.
Depends on D95109
|
| mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp |
| mlir/test/Dialect/Linalg/roundtrip.mlir |
| mlir/test/Dialect/Linalg/invalid.mlir |
| mlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td |
| mlir/test/Dialect/Linalg/tile-tensors.mlir |
Commit
d65e8ee507f82ddca018267d0ce627518dd07337
by craig.topper[RISCV] Add more cmov isel patterns to handle seteq/ne with a small non-zero immediate.
Similar to our free standing setcc patterns, we can use ADDI to
subtract the immediate from the other operand. Then the cmov
can check if the result is zero or non-zero.
Reviewed By: mundaym
Differential Revision: https://reviews.llvm.org/D95169
|
| llvm/lib/Target/RISCV/RISCVInstrInfoB.td |
| llvm/test/CodeGen/RISCV/select-optimize-multiple.ll |
Commit
6ef95056b9dce1aa64d975b70f059673484bed87
by paul.robinson[RGT][ADT] Remove test assertion that will not be executed
Found by the Rotten Green Tests project.
Differential Revision: https://reviews.llvm.org/D95255
|
| llvm/unittests/ADT/ImmutableSetTest.cpp |
Commit
3a50ed84f4823fb0e7b385cc22fef12435dfd376
by Jonas Devlieghere[lldb] FixFileSystem::GetExternalPath for VFS API change
|
| lldb/source/Host/common/FileSystem.cpp |
Commit
6ea7ecbb72aa139ebb1a343a6d544b84b99f1f3a
by paul.robinson[RGT] Don't use EXPECT* macros in a subprocess that exits by signalling
Found by the Rotten Green Tests project.
Differential Revision: https://reviews.llvm.org/D95256
|
| llvm/unittests/Support/CrashRecoveryTest.cpp |
Commit
25fefa5a098e958888496735f793fd01f3e82874
by paul.robinson[RGT][TextAPI] Remove a zero-trip loop and the assertions within it
Found by the Rotten Green Tests project.
Differential Revision: https://reviews.llvm.org/D95259
|
| llvm/unittests/TextAPI/TextStubV4Tests.cpp |
Commit
d18c3c7b18e9e78145d701c4687682848071ab98
by n.james93[CodeComplete] Add ranged for loops code pattern.
Add code pattersn for c++ `range for` loops and objective c `for...in` loops.
Reviewed By: kadircet
Differential Revision: https://reviews.llvm.org/D95131
|
| clang/lib/Sema/SemaCodeComplete.cpp |
Commit
e92be7cd9f03ab3eb8c4a21e686743c2575a169a
by richardPR47682: Merge the DeclContext of a merged FunctionDecl before we inherit
default arguments.
When a function is declared with a qualified name, its eventual semantic
DeclContext may differ from the scope specified by the qualifier if it
redeclares a function in an inline namespace. In this case, we need to
update the DeclContext to be that of the previous declaration, and we
need to do so before we decide whether to inherit default arguments from
that previous declaration, because we only inherit default arguments
from declarations in the same scope.
|
| clang/test/SemaCXX/default1.cpp |
| clang/lib/Sema/SemaDecl.cpp |
Commit
607bec0bb9f787acca95f53dabe6a5c227f6b6b2
by Stanislav.MekhanoshinChange materializeFrameBaseRegister() to return register
The only caller of this function is in the LocalStackSlotAllocation
and it creates base register of class returned by the target's
getPointerRegClass(). AMDGPU wants to use a different reg class
here so let materializeFrameBaseRegister to just create and return
whatever it wants.
Differential Revision: https://reviews.llvm.org/D95268
|
| llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp |
| llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp |
| llvm/lib/Target/AArch64/AArch64RegisterInfo.h |
| llvm/lib/Target/PowerPC/PPCRegisterInfo.h |
| llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp |
| llvm/lib/CodeGen/LocalStackSlotAllocation.cpp |
| llvm/lib/Target/AMDGPU/SIRegisterInfo.h |
| llvm/include/llvm/CodeGen/TargetRegisterInfo.h |
| llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp |
| llvm/lib/Target/ARM/ARMBaseRegisterInfo.h |
Commit
ca904b81e6488b45cbfe846dc86f1406b8e9c03d
by Stanislav.Mekhanoshin[AMDGPU] Fix FP materialization/resolve with flat scratch
Differential Revision: https://reviews.llvm.org/D95266
|
| llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp |
| llvm/test/CodeGen/AMDGPU/flat-scratch.ll |
| llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll |
Commit
ad25bdcb8e4e9459886062d3855a5971af758731
by Jason MolendaChange static buffer to be BSS instead of DATA in HandlePacket_qSpeedTest
Having this 4MB buffer with a compile-time initialized string forced it
into the DATA section and it took up 4MB of space in the binary, which
accounts for like 80% of debugserver's footprint on disk. Change it to
BSS and strcpy in the initial value at runtime instead.
<rdar://problem/73503892>
|
| lldb/tools/debugserver/source/RNBRemote.cpp |
Commit
47e95e87a3e4f738635ff965616d4e2d96bf838a
by jonathanchesterfield[libomptarget] Build cuda plugin without cuda installed locally
[libomptarget] Build cuda plugin without cuda installed locally
Compiles a new file, `plugins/cuda/dynamic_cuda/cuda.cpp`, to an object file that exposes the same symbols that the plugin presently uses from libcuda. The object file contains dlopen of libcuda and cached dlsym calls. Also provides a cuda.h containing the subset that is used.
This lets the cmake file choose between the system cuda and a dlopen shim, with no changes to rtl.cpp.
The corresponding change to amdgpu is postponed until after a refactor of the plugin to reduce the size of the hsa.h stub required
Reviewed By: jdoerfert
Differential Revision: https://reviews.llvm.org/D95155
|
| openmp/libomptarget/plugins/cuda/dynamic_cuda/cuda.cpp |
| openmp/libomptarget/include/dlwrap.h |
| openmp/libomptarget/plugins/cuda/CMakeLists.txt |
| openmp/libomptarget/plugins/cuda/dynamic_cuda/cuda.h |
Commit
ba5628f2c2a9de049b80b3e276f7e05f481c49e7
by Duncan P. N. Exon SmithADT: Use 'using' to inherit assign and append in SmallString
Rather than reimplement, use a `using` declaration to bring in
`SmallVectorImpl<char>`'s assign and append implementations in
`SmallString`.
The `SmallString` versions were missing reference invalidation
assertions from `SmallVector`. This patch also fixes a bug in
`llvm::FileCollector::addFileImpl`, which was a copy/paste from
`clang::ModuleDependencyCollector::copyToRoot`, both caught by the
no-longer-skipped assertions.
As a drive-by, this also sinks the `const SmallVectorImpl&` versions of
these methods down into `SmallVectorImpl`, since I imagine they'd be
useful elsewhere.
Differential Revision: https://reviews.llvm.org/D95202
|
| llvm/lib/Support/FileCollector.cpp |
| clang/lib/Frontend/ModuleDependencyCollector.cpp |
| llvm/include/llvm/ADT/SmallString.h |
| llvm/unittests/ADT/SmallVectorTest.cpp |
| llvm/include/llvm/ADT/SmallVector.h |
Commit
ef51eed37b7ed67b3c0e5f70fa61d681ba21787d
by listmail[LoopDeletion] Handle inner loops w/untaken backedges
This builds on the restricted after initial revert form of D93906, and adds back support for breaking backedges of inner loops. It turns out the original invalidation logic wasn't quite right, specifically around the handling of LCSSA.
When breaking the backedge of an inner loop, we can cause blocks which were in the outer loop only because they were also included in a sub-loop to be removed from both loops. This results in the exit block set for our original parent loop changing, and thus a need for new LCSSA phi nodes.
This case happens when the inner loop has an exit block which is also an exit block of the parent, and there's a block in the child which reaches an exit to said block without also reaching an exit to the parent loop.
(I'm describing this in terms of the immediate parent, but the problem is general for any transitive parent in the nest.)
The approach implemented here involves a potentially expensive LCSSA rebuild. Perf testing during review didn't show anything concerning, but we may end up needing to revert this if anyone encounters a practical compile time issue.
Differential Revision: https://reviews.llvm.org/D94378
|
| llvm/test/Transforms/LoopDeletion/zero-btc.ll |
| llvm/lib/Transforms/Scalar/LoopDeletion.cpp |
| llvm/test/Transforms/IndVarSimplify/X86/pr45360.ll |
| llvm/lib/Transforms/Utils/LoopUtils.cpp |
Commit
97e33feb08aa9c042408862e555423f037753e12
by kai.wang[RISCV] Implement vloxseg/vluxseg intrinsics.
Define vloxseg/vluxseg intrinsics and pseudo instructions.
Lower vloxseg/vluxseg intrinsics to pseudo instructions in RISCVDAGToDAGISel.
Differential Revision: https://reviews.llvm.org/D94903
|
| llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp |
| llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td |
| llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h |
| llvm/include/llvm/IR/IntrinsicsRISCV.td |
| llvm/lib/Target/RISCV/RISCVISelLowering.h |
Commit
a41cb92eb81b3c1446b563f1483fbe71feecc1ee
by kai.wang[RISCV] Add RV32 test cases for vluxseg.
Differential Revision: https://reviews.llvm.org/D95193
|
| llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll |
Commit
b23fe6ff6ff736a5d319598bc818defc09968200
by kai.wang[RISCV] Add RV64 test cases for vluxseg.
Differential Revision: https://reviews.llvm.org/D95190
|
| llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll |
Commit
9e5beadf1805a5906c2ea0d04eb615ce5f92508b
by kai.wang[RISCV] Add RV32 test cases for vloxseg.
Differential Revision: https://reviews.llvm.org/D95191
|
| llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll |
Commit
c28bbd97a15d1942ba63998e7ba8609cc87b38ae
by kai.wang[RISCV] Add RV64 test cases for vloxseg.
Differential Revision: https://reviews.llvm.org/D95192
|
| llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll |
Commit
66a49aef690cb2980152d3cfa867e797bbda54be
by kai.wang[RISCV] Implement vsoxseg/vsuxseg intrinsics.
Define vsoxseg/vsuxseg intrinsics and pseudo instructions.
Lower vsoxseg/vsuxseg intrinsics to pseudo instructions in RISCVDAGToDAGISel.
Differential Revision: https://reviews.llvm.org/D94940
|
| llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h |
| llvm/include/llvm/IR/IntrinsicsRISCV.td |
| llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp |
| llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td |
Commit
a28755003782b97062b19867cfab201816d8dd5f
by kai.wang[RISCV] Add RV32 test cases for vsuxseg.
Differential Revision: https://reviews.llvm.org/D95196
|
| llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll |
Commit
438e118c29a0610dbd44569aff54b5d87684b333
by kai.wang[RISCV] Add RV64 test cases for vsuxseg.
Differential Revision: https://reviews.llvm.org/D95197
|
| llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll |
Commit
408ed11c85d9e70131b77a9125775ace3643663c
by kai.wang[RISCV] Add RV32 test cases for vsoxseg.
Differential Revision: https://reviews.llvm.org/D95194
|
| llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll |
Commit
dc94cecac036b151cb4cababf5b0d986df39ac23
by kai.wang[RISCV] Add RV64 test cases for vsoxseg.
Differential Revision: https://reviews.llvm.org/D95195
|
| llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll |
Commit
480cbed31e74b0db3d31d78789b639af250ce9fe
by hansang.bae[OpenMP] Remove unnecessary pointer checks in a few locations
Also, return NULL from unsuccessful OMPT function lookup.
Differential Revision: https://reviews.llvm.org/D95277
|
| openmp/runtime/src/kmp_taskdeps.cpp |
| openmp/runtime/src/ompt-general.cpp |
Commit
867bdfeff1786f9f910c7cd4689fe56d9dcdf162
by zequanwu[InstCombine] remove incompatible attribute when simplifying some lib calls
Like D95088, remove incompatible attribute in more lib calls.
Differential Revision: https://reviews.llvm.org/D95278
|
| llvm/test/Transforms/InstCombine/memcpy_chk-1.ll |
| llvm/test/Transforms/InstCombine/memmove_chk-1.ll |
| llvm/test/Transforms/InstCombine/memmove-1.ll |
| llvm/test/Transforms/InstCombine/strncpy-1.ll |
| llvm/test/Transforms/InstCombine/memcpy-1.ll |
| llvm/test/Transforms/InstCombine/stpcpy-1.ll |
| llvm/test/Transforms/InstCombine/memset-1.ll |
| llvm/test/Transforms/InstCombine/strcpy-1.ll |
| llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp |
| llvm/test/Transforms/InstCombine/memset_chk-1.ll |
Commit
bd64ad3fe17506933ac2971dcc900271d6ae5969
by Amara EmersonRecommit "[AArch64][GlobalISel] Make G_USUBO legal and select it."
The expansion for wide subtractions includes G_USUBO.
Differential Revision: https://reviews.llvm.org/D95032
This was miscompiling on ubsan bots.
|
| llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp |
| llvm/test/CodeGen/AArch64/GlobalISel/select-usubo.mir |
| llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir |
| llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp |
| llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir |
| llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir |
| llvm/test/CodeGen/AArch64/GlobalISel/select-saddo.mir |
| llvm/test/CodeGen/AArch64/GlobalISel/select-ssubo.mir |
Commit
eda973bbc7ae5327ee8451ba798dec63c550843e
by i[ELF][test] Add a test about --exclude-libs applying to version symbols
D94280 also fixed PR48702.
|
| lld/test/ELF/exclude-libs-versym.s |
| lld/ELF/Driver.cpp |
Commit
6fe193bf271521c5dd1a50949e83b246a9820ce2
by i[test] Add -mtriple
|
| lld/test/ELF/exclude-libs-versym.s |
Commit
dd922bc2a62163cef442646974324943c551725e
by Dan Liew[LSan] Introduce a callback mechanism to allow adding data reachable from ThreadContexts to the frontier.
This mechanism is intended to provide a way to treat the `arg` pointer
of a created (but not yet started) thread as reachable. In future
patches this will be implemented in `GetAdditionalThreadContextPtrs`.
A separate implementation of `GetAdditionalThreadContextPtrs` exists
for ASan and LSan runtimes because they need to be implemented
differently in future patches.
rdar://problem/63537240
Differential Revision: https://reviews.llvm.org/D95183
|
| compiler-rt/lib/lsan/lsan_common.cpp |
| compiler-rt/lib/lsan/lsan_allocator.cpp |
| compiler-rt/lib/asan/asan_allocator.cpp |
| compiler-rt/lib/lsan/lsan_common.h |
Commit
147c0c263d88a9702aba17fbeac62ff83e6c1319
by craig.topper[TargetLowering] Use isOneConstant to simplify some code. NFC
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| llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp |
Commit
6c43564530365ac2c074d7515d4eada294d4ca0c
by lxfind[Coroutine] Improve coro-elide-musttail.ll test
The test wasn't sensitive to alias analysis. As you can seen from D95117 when AA is added by default this is affected.
Updating the test so that it coveres both cases for AA analysis.
Note that this patch depends on D95117 to land first.
Differential Revision: https://reviews.llvm.org/D95247
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| llvm/test/Transforms/Coroutines/coro-elide-musttail.ll |
Commit
018984ae6833fae107aa9c502ab5536efceca88e
by brad[PowerPC] Fix va_arg in C++, Objective-C on 32-bit ELF targets
In the PPC32 SVR4 ABI, a va_list has copies of registers from the function call.
va_arg looked in the wrong registers for (the pointer representation of) an
object in Objective-C, and for some types in C++. Fix va_arg to look in the
general-purpose registers, not the floating-point registers. Also fix va_arg
for some C++ types, like a member function pointer, that are aggregates for
the ABI.
Anthony Richardby found the problem in Objective-C. Eli Friedman suggested
part of this fix.
Fixes https://bugs.llvm.org/show_bug.cgi?id=47921
Reviewed By: efriedma, nemanjai
Differential Revision: https://reviews.llvm.org/D90329
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| clang/lib/CodeGen/TargetInfo.cpp |
| clang/test/CodeGenObjC/ppc32-varargs-id.m |
| clang/test/CodeGenCXX/ppc32-varargs-method.cpp |
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