FailedChanges

Summary

  1. [llvm-objdump] Simplify reportError() and prepend outs().flush() (details)
  2. [llvm-objdump] Move llvm:: to llvm::objdump:: and qualifying definitions with objdump:: (details)
  3. [llvm-objdump] Delete unneeeded namespace llvm {} (details)
  4. [ELF][docs] Update supported targets (details)
  5. [X86] Move MMX_SET0 pattern into the instruction definition. NFC (details)
  6. [X86] Autogenerate complete checks. NFC (details)
  7. [X86] Fix a place where we created MOVQ2DQ with a DstVT other than v2i64. (details)
  8. [X86] Teach computeKnownBitsForTargetNode that the upper half of X86ISD::MOVQ2DQ is all zero. (details)
  9. [DAGCombiner] Move debug message and statistic update into CommitTargetLoweringOpt. (details)
  10. [X86] Add DAG combine to turn (v2i64 (scalar_to_vector (i64 (bitconvert (mmx))))) to MOVQ2DQ. Remove unneeded isel patterns. (details)
  11. [X86] Remove unneeded bitconverts from isel patterns. NFC (details)
  12. AMDGPU: Add setTruncStoreAction for vector i64 types made legal recently (details)
  13. [AMDGPU] Precommit tests for D80813 (details)
  14. [AMDGPU] Propagate fast-math flags when lowering FSIN and FCOS (details)
Commit a23d1e9aff4d8cb752e227b3e16f887cf49c15d4 by maskray
[llvm-objdump] Simplify reportError() and prepend outs().flush()

As noticed by dblaikie.

I don't know what code paths using reportError can cause stdout output
to be interleaved with stderr, so no test is added now.

Also drop an unneeded use of errs().fflush() in reportWarning().
I requested this in D64165.
The file was modifiedllvm/tools/llvm-objdump/llvm-objdump.cpp
Commit 439d27d79f58282b618881142244bbdcb1f28345 by maskray
[llvm-objdump] Move llvm:: to llvm::objdump:: and qualifying definitions with objdump::

Or adding `static`.

Qualifying definitions with `objdump::` comforms to the coding standards
https://llvm.org/docs/CodingStandards.html#use-namespace-qualifiers-to-implement-previously-declared-functions
The file was modifiedllvm/tools/llvm-objdump/COFFDump.cpp
The file was modifiedllvm/tools/llvm-objdump/llvm-objdump.cpp
The file was modifiedllvm/tools/llvm-objdump/llvm-objdump.h
Commit d04eb253c710aec30707e404cfc9dc672082d3a2 by maskray
[llvm-objdump] Delete unneeeded namespace llvm {}
The file was modifiedllvm/tools/llvm-objdump/llvm-objdump.cpp
Commit ce1fadca608ffaf214732b843e084a75e55fcb50 by maskray
[ELF][docs] Update supported targets

PowerPC, PowerPC64 and x86-32 have production quality.
Mention Hexagon, RISC-V and SPARC V9.
The file was modifiedlld/docs/index.rst
Commit 8857822452c758805e8bb33ecc877d8d0cce1660 by craig.topper
[X86] Move MMX_SET0 pattern into the instruction definition. NFC
The file was modifiedllvm/lib/Target/X86/X86InstrMMX.td
Commit efc5857b0b121ffd0b74fcd7aa8c48419a3fe4fc by craig.topper
[X86] Autogenerate complete checks. NFC
The file was modifiedllvm/test/CodeGen/X86/pr23246.ll
Commit 1ecf39d607acdb04c2bb5155e5f7265db2484511 by craig.topper
[X86] Fix a place where we created MOVQ2DQ with a DstVT other than v2i64.

The type profile and isel pattern have this type declared as
being MVT::v2i64. But isel skips the explicit type check due to
the type profile.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit af1accdd860d4e1768a1f56a8651ae4d13445e14 by craig.topper
[X86] Teach computeKnownBitsForTargetNode that the upper half of X86ISD::MOVQ2DQ is all zero.
The file was modifiedllvm/test/CodeGen/X86/vec_insert-7.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/mmx-cvt.ll
Commit a4dd45b7d09d8c12b87eaa0e6d1a92ce2b0defe0 by craig.topper
[DAGCombiner] Move debug message and statistic update into CommitTargetLoweringOpt.

This code was repeated in two callers of CommitTargetLoweringOpt.
But CommitTargetLoweringOpt is also called from TargetLowering.
We should print a message for those calls to. So sink the
repeated code into CommitTargetLoweringOpt to catch those calls.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit 7c3b8077cc3feed2de3de6f3efb0627d619d1434 by craig.topper
[X86] Add DAG combine to turn (v2i64 (scalar_to_vector (i64 (bitconvert (mmx))))) to MOVQ2DQ. Remove unneeded isel patterns.

We already had a DAG combine for (mmx (bitconvert (i64 (extractelement v2i64))))
to MOVDQ2Q.

Remove patterns for MMX_MOVQ2DQrr/MMX_MOVDQ2Qrr that use
scalar_to_vector/extractelement involving i64 scalar type with
v2i64 and x86mmx.
The file was modifiedllvm/lib/Target/X86/X86InstrMMX.td
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit dbda87186ec1b28a98d7a91a651b5a47c6f06d40 by craig.topper
[X86] Remove unneeded bitconverts from isel patterns. NFC

The types already match so TableGen is removing the bitconvert.
The file was modifiedllvm/lib/Target/X86/X86InstrMMX.td
Commit 234eba90f4f346a4b0d260cdd61a9aae647b2b48 by changpeng.fang
AMDGPU: Add setTruncStoreAction for vector i64 types made legal recently

Reviewers:
  rampitec, arsenm

Differential Revision:
  https://reviews.llvm.org/D80853
The file was addedllvm/test/CodeGen/AMDGPU/trunc-store-i64.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
Commit d4751f35560321dfb38cd77b924e715b9ebf9203 by jay.foad
[AMDGPU] Precommit tests for D80813
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.sin.ll
Commit 2768edfff19a170faca35a8c63163c8bb1b67382 by jay.foad
[AMDGPU] Propagate fast-math flags when lowering FSIN and FCOS

Differential Revision: https://reviews.llvm.org/D80813
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.sin.ll