Coverage Report

Created: 2022-05-14 11:35

/Users/buildslave/jenkins/workspace/coverage/llvm-project/clang/lib/Basic/Targets/AArch64.cpp
Line
Count
Source (jump to first uncovered line)
1
//===--- AArch64.cpp - Implement AArch64 target feature support -----------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file implements AArch64 TargetInfo objects.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "AArch64.h"
14
#include "clang/Basic/LangOptions.h"
15
#include "clang/Basic/TargetBuiltins.h"
16
#include "clang/Basic/TargetInfo.h"
17
#include "llvm/ADT/ArrayRef.h"
18
#include "llvm/ADT/StringExtras.h"
19
#include "llvm/ADT/StringSwitch.h"
20
#include "llvm/Support/AArch64TargetParser.h"
21
22
using namespace clang;
23
using namespace clang::targets;
24
25
const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
26
#define BUILTIN(ID, TYPE, ATTRS)                                               \
27
   {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
28
#include "clang/Basic/BuiltinsNEON.def"
29
30
#define BUILTIN(ID, TYPE, ATTRS)                                               \
31
   {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
32
#include "clang/Basic/BuiltinsSVE.def"
33
34
#define BUILTIN(ID, TYPE, ATTRS)                                               \
35
   {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
36
#define LANGBUILTIN(ID, TYPE, ATTRS, LANG)                                     \
37
  {#ID, TYPE, ATTRS, nullptr, LANG, nullptr},
38
#define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE)         \
39
  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
40
#include "clang/Basic/BuiltinsAArch64.def"
41
};
42
43
2.94k
static StringRef getArchVersionString(llvm::AArch64::ArchKind Kind) {
44
2.94k
  switch (Kind) {
45
7
  case llvm::AArch64::ArchKind::ARMV9A:
46
8
  case llvm::AArch64::ArchKind::ARMV9_1A:
47
11
  case llvm::AArch64::ArchKind::ARMV9_2A:
48
15
  case llvm::AArch64::ArchKind::ARMV9_3A:
49
15
    return "9";
50
2.93k
  default:
51
2.93k
    return "8";
52
2.94k
  }
53
2.94k
}
54
55
2.94k
StringRef AArch64TargetInfo::getArchProfile() const {
56
2.94k
  switch (ArchKind) {
57
2
  case llvm::AArch64::ArchKind::ARMV8R:
58
2
    return "R";
59
2.94k
  default:
60
2.94k
    return "A";
61
2.94k
  }
62
2.94k
}
63
64
AArch64TargetInfo::AArch64TargetInfo(const llvm::Triple &Triple,
65
                                     const TargetOptions &Opts)
66
2.95k
    : TargetInfo(Triple), ABI("aapcs") {
67
2.95k
  if (getTriple().isOSOpenBSD()) {
68
4
    Int64Type = SignedLongLong;
69
4
    IntMaxType = SignedLongLong;
70
2.95k
  } else {
71
2.95k
    if (!getTriple().isOSDarwin() && 
!getTriple().isOSNetBSD()2.75k
)
72
2.74k
      WCharType = UnsignedInt;
73
74
2.95k
    Int64Type = SignedLong;
75
2.95k
    IntMaxType = SignedLong;
76
2.95k
  }
77
78
  // All AArch64 implementations support ARMv8 FP, which makes half a legal type.
79
2.95k
  HasLegalHalfType = true;
80
2.95k
  HasFloat16 = true;
81
82
2.95k
  if (Triple.isArch64Bit())
83
2.94k
    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
84
16
  else
85
16
    LongWidth = LongAlign = PointerWidth = PointerAlign = 32;
86
87
2.95k
  MaxVectorAlign = 128;
88
2.95k
  MaxAtomicInlineWidth = 128;
89
2.95k
  MaxAtomicPromoteWidth = 128;
90
91
2.95k
  LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128;
92
2.95k
  LongDoubleFormat = &llvm::APFloat::IEEEquad();
93
94
2.95k
  BFloat16Width = BFloat16Align = 16;
95
2.95k
  BFloat16Format = &llvm::APFloat::BFloat();
96
97
  // Make __builtin_ms_va_list available.
98
2.95k
  HasBuiltinMSVaList = true;
99
100
  // Make the SVE types available.  Note that this deliberately doesn't
101
  // depend on SveMode, since in principle it should be possible to turn
102
  // SVE on and off within a translation unit.  It should also be possible
103
  // to compile the global declaration:
104
  //
105
  // __SVInt8_t *ptr;
106
  //
107
  // even without SVE.
108
2.95k
  HasAArch64SVETypes = true;
109
110
  // {} in inline assembly are neon specifiers, not assembly variant
111
  // specifiers.
112
2.95k
  NoAsmVariants = true;
113
114
  // AAPCS gives rules for bitfields. 7.1.7 says: "The container type
115
  // contributes to the alignment of the containing aggregate in the same way
116
  // a plain (non bit-field) member of that type would, without exception for
117
  // zero-sized or anonymous bit-fields."
118
2.95k
  assert(UseBitFieldTypeAlignment && "bitfields affect type alignment");
119
0
  UseZeroLengthBitfieldAlignment = true;
120
121
  // AArch64 targets default to using the ARM C++ ABI.
122
2.95k
  TheCXXABI.set(TargetCXXABI::GenericAArch64);
123
124
2.95k
  if (Triple.getOS() == llvm::Triple::Linux)
125
2.36k
    this->MCountName = "\01_mcount";
126
596
  else if (Triple.getOS() == llvm::Triple::UnknownOS)
127
293
    this->MCountName =
128
293
        Opts.EABIVersion == llvm::EABI::GNU ? 
"\01_mcount"1
:
"mcount"292
;
129
2.95k
}
130
131
4.14k
StringRef AArch64TargetInfo::getABI() const { return ABI; }
132
133
302
bool AArch64TargetInfo::setABI(const std::string &Name) {
134
302
  if (Name != "aapcs" && 
Name != "darwinpcs"39
)
135
0
    return false;
136
137
302
  ABI = Name;
138
302
  return true;
139
302
}
140
141
bool AArch64TargetInfo::validateBranchProtection(StringRef Spec, StringRef,
142
                                                 BranchProtectionInfo &BPI,
143
40
                                                 StringRef &Err) const {
144
40
  llvm::ARM::ParsedBranchProtection PBP;
145
40
  if (!llvm::ARM::parseBranchProtection(Spec, PBP, Err))
146
7
    return false;
147
148
33
  BPI.SignReturnAddr =
149
33
      llvm::StringSwitch<LangOptions::SignReturnAddressScopeKind>(PBP.Scope)
150
33
          .Case("non-leaf", LangOptions::SignReturnAddressScopeKind::NonLeaf)
151
33
          .Case("all", LangOptions::SignReturnAddressScopeKind::All)
152
33
          .Default(LangOptions::SignReturnAddressScopeKind::None);
153
154
33
  if (PBP.Key == "a_key")
155
24
    BPI.SignKey = LangOptions::SignReturnAddressKeyKind::AKey;
156
9
  else
157
9
    BPI.SignKey = LangOptions::SignReturnAddressKeyKind::BKey;
158
159
33
  BPI.BranchTargetEnforcement = PBP.BranchTargetEnforcement;
160
33
  return true;
161
40
}
162
163
322
bool AArch64TargetInfo::isValidCPUName(StringRef Name) const {
164
322
  return Name == "generic" ||
165
322
         
llvm::AArch64::parseCPUArch(Name) != llvm::AArch64::ArchKind::INVALID60
;
166
322
}
167
168
321
bool AArch64TargetInfo::setCPU(const std::string &Name) {
169
321
  return isValidCPUName(Name);
170
321
}
171
172
void AArch64TargetInfo::fillValidCPUList(
173
2
    SmallVectorImpl<StringRef> &Values) const {
174
2
  llvm::AArch64::fillValidCPUArchList(Values);
175
2
}
176
177
void AArch64TargetInfo::getTargetDefinesARMV81A(const LangOptions &Opts,
178
132
                                                MacroBuilder &Builder) const {
179
132
  Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
180
132
  Builder.defineMacro("__ARM_FEATURE_ATOMICS", "1");
181
132
  Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
182
132
}
183
184
void AArch64TargetInfo::getTargetDefinesARMV82A(const LangOptions &Opts,
185
123
                                                MacroBuilder &Builder) const {
186
  // Also include the ARMv8.1 defines
187
123
  getTargetDefinesARMV81A(Opts, Builder);
188
123
}
189
190
void AArch64TargetInfo::getTargetDefinesARMV83A(const LangOptions &Opts,
191
77
                                                MacroBuilder &Builder) const {
192
77
  Builder.defineMacro("__ARM_FEATURE_COMPLEX", "1");
193
77
  Builder.defineMacro("__ARM_FEATURE_JCVT", "1");
194
  // Also include the Armv8.2 defines
195
77
  getTargetDefinesARMV82A(Opts, Builder);
196
77
}
197
198
void AArch64TargetInfo::getTargetDefinesARMV84A(const LangOptions &Opts,
199
73
                                                MacroBuilder &Builder) const {
200
  // Also include the Armv8.3 defines
201
73
  getTargetDefinesARMV83A(Opts, Builder);
202
73
}
203
204
void AArch64TargetInfo::getTargetDefinesARMV85A(const LangOptions &Opts,
205
58
                                                MacroBuilder &Builder) const {
206
58
  Builder.defineMacro("__ARM_FEATURE_FRINT", "1");
207
  // Also include the Armv8.4 defines
208
58
  getTargetDefinesARMV84A(Opts, Builder);
209
58
}
210
211
void AArch64TargetInfo::getTargetDefinesARMV86A(const LangOptions &Opts,
212
24
                                                MacroBuilder &Builder) const {
213
  // Also include the Armv8.5 defines
214
  // FIXME: Armv8.6 makes the following extensions mandatory:
215
  // - __ARM_FEATURE_BF16
216
  // - __ARM_FEATURE_MATMUL_INT8
217
  // Handle them here.
218
24
  getTargetDefinesARMV85A(Opts, Builder);
219
24
}
220
221
void AArch64TargetInfo::getTargetDefinesARMV87A(const LangOptions &Opts,
222
18
                                                MacroBuilder &Builder) const {
223
  // Also include the Armv8.6 defines
224
18
  getTargetDefinesARMV86A(Opts, Builder);
225
18
}
226
227
void AArch64TargetInfo::getTargetDefinesARMV88A(const LangOptions &Opts,
228
10
                                                MacroBuilder &Builder) const {
229
  // Also include the Armv8.7 defines
230
10
  getTargetDefinesARMV87A(Opts, Builder);
231
10
}
232
233
void AArch64TargetInfo::getTargetDefinesARMV9A(const LangOptions &Opts,
234
7
                                               MacroBuilder &Builder) const {
235
  // Armv9-A maps to Armv8.5-A
236
7
  getTargetDefinesARMV85A(Opts, Builder);
237
7
}
238
239
void AArch64TargetInfo::getTargetDefinesARMV91A(const LangOptions &Opts,
240
1
                                                MacroBuilder &Builder) const {
241
  // Armv9.1-A maps to Armv8.6-A
242
1
  getTargetDefinesARMV86A(Opts, Builder);
243
1
}
244
245
void AArch64TargetInfo::getTargetDefinesARMV92A(const LangOptions &Opts,
246
3
                                                MacroBuilder &Builder) const {
247
  // Armv9.2-A maps to Armv8.7-A
248
3
  getTargetDefinesARMV87A(Opts, Builder);
249
3
}
250
251
void AArch64TargetInfo::getTargetDefinesARMV93A(const LangOptions &Opts,
252
4
                                                MacroBuilder &Builder) const {
253
  // Armv9.3-A maps to Armv8.8-A
254
4
  getTargetDefinesARMV88A(Opts, Builder);
255
4
}
256
257
void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts,
258
2.94k
                                         MacroBuilder &Builder) const {
259
  // Target identification.
260
2.94k
  Builder.defineMacro("__aarch64__");
261
  // For bare-metal.
262
2.94k
  if (getTriple().getOS() == llvm::Triple::UnknownOS &&
263
2.94k
      
getTriple().isOSBinFormatELF()288
)
264
287
    Builder.defineMacro("__ELF__");
265
266
  // Target properties.
267
2.94k
  if (!getTriple().isOSWindows() && 
getTriple().isArch64Bit()2.88k
) {
268
2.87k
    Builder.defineMacro("_LP64");
269
2.87k
    Builder.defineMacro("__LP64__");
270
2.87k
  }
271
272
2.94k
  std::string CodeModel = getTargetOpts().CodeModel;
273
2.94k
  if (CodeModel == "default")
274
2.94k
    CodeModel = "small";
275
2.94k
  for (char &c : CodeModel)
276
14.7k
    c = toupper(c);
277
2.94k
  Builder.defineMacro("__AARCH64_CMODEL_" + CodeModel + "__");
278
279
  // ACLE predefines. Many can only have one possible value on v8 AArch64.
280
2.94k
  Builder.defineMacro("__ARM_ACLE", "200");
281
2.94k
  Builder.defineMacro("__ARM_ARCH", getArchVersionString(ArchKind));
282
2.94k
  Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + getArchProfile() + "'");
283
284
2.94k
  Builder.defineMacro("__ARM_64BIT_STATE", "1");
285
2.94k
  Builder.defineMacro("__ARM_PCS_AAPCS64", "1");
286
2.94k
  Builder.defineMacro("__ARM_ARCH_ISA_A64", "1");
287
288
2.94k
  Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
289
2.94k
  Builder.defineMacro("__ARM_FEATURE_FMA", "1");
290
2.94k
  Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF");
291
2.94k
  Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE
292
2.94k
  Builder.defineMacro("__ARM_FEATURE_DIV");       // For backwards compatibility
293
2.94k
  Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
294
2.94k
  Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
295
296
2.94k
  Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
297
298
  // 0xe implies support for half, single and double precision operations.
299
2.94k
  Builder.defineMacro("__ARM_FP", "0xE");
300
301
  // PCS specifies this for SysV variants, which is all we support. Other ABIs
302
  // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
303
2.94k
  Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
304
2.94k
  Builder.defineMacro("__ARM_FP16_ARGS", "1");
305
306
2.94k
  if (Opts.UnsafeFPMath)
307
4
    Builder.defineMacro("__ARM_FP_FAST", "1");
308
309
2.94k
  Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
310
2.94k
                      Twine(Opts.WCharSize ? 
Opts.WCharSize5
:
42.94k
));
311
312
2.94k
  Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", Opts.ShortEnums ? 
"1"2
:
"4"2.94k
);
313
314
2.94k
  if (FPU & NeonMode) {
315
422
    Builder.defineMacro("__ARM_NEON", "1");
316
    // 64-bit NEON supports half, single and double precision operations.
317
422
    Builder.defineMacro("__ARM_NEON_FP", "0xE");
318
422
  }
319
320
2.94k
  if (FPU & SveMode)
321
2.04k
    Builder.defineMacro("__ARM_FEATURE_SVE", "1");
322
323
2.94k
  if ((FPU & NeonMode) && 
(FPU & SveMode)422
)
324
49
    Builder.defineMacro("__ARM_NEON_SVE_BRIDGE", "1");
325
326
2.94k
  if (HasSVE2)
327
647
    Builder.defineMacro("__ARM_FEATURE_SVE2", "1");
328
329
2.94k
  if (HasSVE2 && 
HasSVE2AES647
)
330
25
    Builder.defineMacro("__ARM_FEATURE_SVE2_AES", "1");
331
332
2.94k
  if (HasSVE2 && 
HasSVE2BitPerm647
)
333
13
    Builder.defineMacro("__ARM_FEATURE_SVE2_BITPERM", "1");
334
335
2.94k
  if (HasSVE2 && 
HasSVE2SHA3647
)
336
5
    Builder.defineMacro("__ARM_FEATURE_SVE2_SHA3", "1");
337
338
2.94k
  if (HasSVE2 && 
HasSVE2SM4647
)
339
9
    Builder.defineMacro("__ARM_FEATURE_SVE2_SM4", "1");
340
341
2.94k
  if (HasCRC)
342
20
    Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
343
344
  // The __ARM_FEATURE_CRYPTO is deprecated in favor of finer grained feature
345
  // macros for AES, SHA2, SHA3 and SM4
346
2.94k
  if (HasAES && 
HasSHA234
)
347
33
    Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
348
349
2.94k
  if (HasAES)
350
34
    Builder.defineMacro("__ARM_FEATURE_AES", "1");
351
352
2.94k
  if (HasSHA2)
353
37
    Builder.defineMacro("__ARM_FEATURE_SHA2", "1");
354
355
2.94k
  if (HasSHA3) {
356
20
    Builder.defineMacro("__ARM_FEATURE_SHA3", "1");
357
20
    Builder.defineMacro("__ARM_FEATURE_SHA512", "1");
358
20
  }
359
360
2.94k
  if (HasSM4) {
361
20
    Builder.defineMacro("__ARM_FEATURE_SM3", "1");
362
20
    Builder.defineMacro("__ARM_FEATURE_SM4", "1");
363
20
  }
364
365
2.94k
  if (HasUnaligned)
366
2.94k
    Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
367
368
2.94k
  if ((FPU & NeonMode) && 
HasFullFP16422
)
369
114
    Builder.defineMacro("__ARM_FEATURE_FP16_VECTOR_ARITHMETIC", "1");
370
2.94k
  if (HasFullFP16)
371
2.11k
   Builder.defineMacro("__ARM_FEATURE_FP16_SCALAR_ARITHMETIC", "1");
372
373
2.94k
  if (HasDotProd)
374
20
    Builder.defineMacro("__ARM_FEATURE_DOTPROD", "1");
375
376
2.94k
  if (HasMTE)
377
18
    Builder.defineMacro("__ARM_FEATURE_MEMORY_TAGGING", "1");
378
379
2.94k
  if (HasTME)
380
4
    Builder.defineMacro("__ARM_FEATURE_TME", "1");
381
382
2.94k
  if (HasMatMul)
383
37
    Builder.defineMacro("__ARM_FEATURE_MATMUL_INT8", "1");
384
385
2.94k
  if (HasLSE)
386
17
    Builder.defineMacro("__ARM_FEATURE_ATOMICS", "1");
387
388
2.94k
  if (HasBFloat16) {
389
344
    Builder.defineMacro("__ARM_FEATURE_BF16", "1");
390
344
    Builder.defineMacro("__ARM_FEATURE_BF16_VECTOR_ARITHMETIC", "1");
391
344
    Builder.defineMacro("__ARM_BF16_FORMAT_ALTERNATIVE", "1");
392
344
    Builder.defineMacro("__ARM_FEATURE_BF16_SCALAR_ARITHMETIC", "1");
393
344
  }
394
395
2.94k
  if ((FPU & SveMode) && 
HasBFloat162.04k
) {
396
312
    Builder.defineMacro("__ARM_FEATURE_SVE_BF16", "1");
397
312
  }
398
399
2.94k
  if ((FPU & SveMode) && 
HasMatmulFP642.04k
)
400
61
    Builder.defineMacro("__ARM_FEATURE_SVE_MATMUL_FP64", "1");
401
402
2.94k
  if ((FPU & SveMode) && 
HasMatmulFP322.04k
)
403
6
    Builder.defineMacro("__ARM_FEATURE_SVE_MATMUL_FP32", "1");
404
405
2.94k
  if ((FPU & SveMode) && 
HasMatMul2.04k
)
406
18
    Builder.defineMacro("__ARM_FEATURE_SVE_MATMUL_INT8", "1");
407
408
2.94k
  if ((FPU & NeonMode) && 
HasFP16FML422
)
409
24
    Builder.defineMacro("__ARM_FEATURE_FP16_FML", "1");
410
411
2.94k
  if (Opts.hasSignReturnAddress()) {
412
    // Bitmask:
413
    // 0: Protection using the A key
414
    // 1: Protection using the B key
415
    // 2: Protection including leaf functions
416
15
    unsigned Value = 0;
417
418
15
    if (Opts.isSignReturnAddressWithAKey())
419
10
      Value |= (1 << 0);
420
5
    else
421
5
      Value |= (1 << 1);
422
423
15
    if (Opts.isSignReturnAddressScopeAll())
424
6
      Value |= (1 << 2);
425
426
15
    Builder.defineMacro("__ARM_FEATURE_PAC_DEFAULT", std::to_string(Value));
427
15
  }
428
429
2.94k
  if (Opts.BranchTargetEnforcement)
430
6
    Builder.defineMacro("__ARM_FEATURE_BTI_DEFAULT", "1");
431
432
2.94k
  if (HasLS64)
433
6
    Builder.defineMacro("__ARM_FEATURE_LS64", "1");
434
435
2.94k
  if (HasRandGen)
436
2
    Builder.defineMacro("__ARM_FEATURE_RNG", "1");
437
438
2.94k
  if (HasMOPS)
439
11
    Builder.defineMacro("__ARM_FEATURE_MOPS", "1");
440
441
2.94k
  switch (ArchKind) {
442
2.81k
  default:
443
2.81k
    break;
444
2.81k
  case llvm::AArch64::ArchKind::ARMV8_1A:
445
9
    getTargetDefinesARMV81A(Opts, Builder);
446
9
    break;
447
46
  case llvm::AArch64::ArchKind::ARMV8_2A:
448
46
    getTargetDefinesARMV82A(Opts, Builder);
449
46
    break;
450
4
  case llvm::AArch64::ArchKind::ARMV8_3A:
451
4
    getTargetDefinesARMV83A(Opts, Builder);
452
4
    break;
453
15
  case llvm::AArch64::ArchKind::ARMV8_4A:
454
15
    getTargetDefinesARMV84A(Opts, Builder);
455
15
    break;
456
27
  case llvm::AArch64::ArchKind::ARMV8_5A:
457
27
    getTargetDefinesARMV85A(Opts, Builder);
458
27
    break;
459
5
  case llvm::AArch64::ArchKind::ARMV8_6A:
460
5
    getTargetDefinesARMV86A(Opts, Builder);
461
5
    break;
462
5
  case llvm::AArch64::ArchKind::ARMV8_7A:
463
5
    getTargetDefinesARMV87A(Opts, Builder);
464
5
    break;
465
6
  case llvm::AArch64::ArchKind::ARMV8_8A:
466
6
    getTargetDefinesARMV88A(Opts, Builder);
467
6
    break;
468
7
  case llvm::AArch64::ArchKind::ARMV9A:
469
7
    getTargetDefinesARMV9A(Opts, Builder);
470
7
    break;
471
1
  case llvm::AArch64::ArchKind::ARMV9_1A:
472
1
    getTargetDefinesARMV91A(Opts, Builder);
473
1
    break;
474
3
  case llvm::AArch64::ArchKind::ARMV9_2A:
475
3
    getTargetDefinesARMV92A(Opts, Builder);
476
3
    break;
477
4
  case llvm::AArch64::ArchKind::ARMV9_3A:
478
4
    getTargetDefinesARMV93A(Opts, Builder);
479
4
    break;
480
2.94k
  }
481
482
  // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
483
2.94k
  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
484
2.94k
  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
485
2.94k
  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
486
2.94k
  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
487
488
2.94k
  if (Opts.VScaleMin && 
Opts.VScaleMin == Opts.VScaleMax82
) {
489
73
    Builder.defineMacro("__ARM_FEATURE_SVE_BITS", Twine(Opts.VScaleMin * 128));
490
73
    Builder.defineMacro("__ARM_FEATURE_SVE_VECTOR_OPERATORS");
491
73
  }
492
2.94k
}
493
494
2.94k
ArrayRef<Builtin::Info> AArch64TargetInfo::getTargetBuiltins() const {
495
2.94k
  return llvm::makeArrayRef(BuiltinInfo, clang::AArch64::LastTSBuiltin -
496
2.94k
                                             Builtin::FirstTSBuiltin);
497
2.94k
}
498
499
Optional<std::pair<unsigned, unsigned>>
500
42.5k
AArch64TargetInfo::getVScaleRange(const LangOptions &LangOpts) const {
501
42.5k
  if (LangOpts.VScaleMin || 
LangOpts.VScaleMax42.3k
)
502
184
    return std::pair<unsigned, unsigned>(
503
184
        LangOpts.VScaleMin ? LangOpts.VScaleMin : 
10
, LangOpts.VScaleMax);
504
505
42.3k
  if (hasFeature("sve"))
506
30.0k
    return std::pair<unsigned, unsigned>(1, 16);
507
508
12.3k
  return None;
509
42.3k
}
510
511
49.6k
bool AArch64TargetInfo::hasFeature(StringRef Feature) const {
512
49.6k
  return llvm::StringSwitch<bool>(Feature)
513
49.6k
    .Cases("aarch64", "arm64", "arm", true)
514
49.6k
    .Case("neon", FPU & NeonMode)
515
49.6k
    .Cases("sve", "sve2", "sve2-bitperm", "sve2-aes", "sve2-sha3", "sve2-sm4", "f64mm", "f32mm", "i8mm", "bf16", FPU & SveMode)
516
49.6k
    .Case("ls64", HasLS64)
517
49.6k
    .Default(false);
518
49.6k
}
519
520
bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
521
2.95k
                                             DiagnosticsEngine &Diags) {
522
2.95k
  FPU = FPUMode;
523
2.95k
  HasCRC = false;
524
2.95k
  HasAES = false;
525
2.95k
  HasSHA2 = false;
526
2.95k
  HasSHA3 = false;
527
2.95k
  HasSM4 = false;
528
2.95k
  HasUnaligned = true;
529
2.95k
  HasFullFP16 = false;
530
2.95k
  HasDotProd = false;
531
2.95k
  HasFP16FML = false;
532
2.95k
  HasMTE = false;
533
2.95k
  HasTME = false;
534
2.95k
  HasLS64 = false;
535
2.95k
  HasRandGen = false;
536
2.95k
  HasMatMul = false;
537
2.95k
  HasBFloat16 = false;
538
2.95k
  HasSVE2 = false;
539
2.95k
  HasSVE2AES = false;
540
2.95k
  HasSVE2SHA3 = false;
541
2.95k
  HasSVE2SM4 = false;
542
2.95k
  HasSVE2BitPerm = false;
543
2.95k
  HasMatmulFP64 = false;
544
2.95k
  HasMatmulFP32 = false;
545
2.95k
  HasLSE = false;
546
2.95k
  HasMOPS = false;
547
548
2.95k
  ArchKind = llvm::AArch64::ArchKind::INVALID;
549
550
3.74k
  for (const auto &Feature : Features) {
551
3.74k
    if (Feature == "+neon")
552
422
      FPU |= NeonMode;
553
3.74k
    if (Feature == "+sve") {
554
1.40k
      FPU |= SveMode;
555
1.40k
      HasFullFP16 = true;
556
1.40k
    }
557
3.74k
    if (Feature == "+sve2") {
558
599
      FPU |= SveMode;
559
599
      HasFullFP16 = true;
560
599
      HasSVE2 = true;
561
599
    }
562
3.74k
    if (Feature == "+sve2-aes") {
563
25
      FPU |= SveMode;
564
25
      HasFullFP16 = true;
565
25
      HasSVE2 = true;
566
25
      HasSVE2AES = true;
567
25
    }
568
3.74k
    if (Feature == "+sve2-sha3") {
569
5
      FPU |= SveMode;
570
5
      HasFullFP16 = true;
571
5
      HasSVE2 = true;
572
5
      HasSVE2SHA3 = true;
573
5
    }
574
3.74k
    if (Feature == "+sve2-sm4") {
575
9
      FPU |= SveMode;
576
9
      HasFullFP16 = true;
577
9
      HasSVE2 = true;
578
9
      HasSVE2SM4 = true;
579
9
    }
580
3.74k
    if (Feature == "+sve2-bitperm") {
581
13
      FPU |= SveMode;
582
13
      HasFullFP16 = true;
583
13
      HasSVE2 = true;
584
13
      HasSVE2BitPerm = true;
585
13
    }
586
3.74k
    if (Feature == "+f32mm") {
587
6
      FPU |= SveMode;
588
6
      HasMatmulFP32 = true;
589
6
    }
590
3.74k
    if (Feature == "+f64mm") {
591
61
      FPU |= SveMode;
592
61
      HasMatmulFP64 = true;
593
61
    }
594
3.74k
    if (Feature == "+crc")
595
20
      HasCRC = true;
596
3.74k
    if (Feature == "+aes")
597
34
      HasAES = true;
598
3.74k
    if (Feature == "+sha2")
599
34
      HasSHA2 = true;
600
3.74k
    if (Feature == "+sha3") {
601
20
      HasSHA2 = true;
602
20
      HasSHA3 = true;
603
20
    }
604
3.74k
    if (Feature == "+sm4")
605
20
      HasSM4 = true;
606
3.74k
    if (Feature == "+strict-align")
607
2
      HasUnaligned = false;
608
3.74k
    if (Feature == "+v8a")
609
168
      ArchKind = llvm::AArch64::ArchKind::ARMV8A;
610
3.74k
    if (Feature == "+v8.1a")
611
9
      ArchKind = llvm::AArch64::ArchKind::ARMV8_1A;
612
3.74k
    if (Feature == "+v8.2a")
613
46
      ArchKind = llvm::AArch64::ArchKind::ARMV8_2A;
614
3.74k
    if (Feature == "+v8.3a")
615
4
      ArchKind = llvm::AArch64::ArchKind::ARMV8_3A;
616
3.74k
    if (Feature == "+v8.4a")
617
15
      ArchKind = llvm::AArch64::ArchKind::ARMV8_4A;
618
3.74k
    if (Feature == "+v8.5a")
619
27
      ArchKind = llvm::AArch64::ArchKind::ARMV8_5A;
620
3.74k
    if (Feature == "+v8.6a")
621
5
      ArchKind = llvm::AArch64::ArchKind::ARMV8_6A;
622
3.74k
    if (Feature == "+v8.7a")
623
5
      ArchKind = llvm::AArch64::ArchKind::ARMV8_7A;
624
3.74k
    if (Feature == "+v8.8a")
625
6
      ArchKind = llvm::AArch64::ArchKind::ARMV8_8A;
626
3.74k
    if (Feature == "+v9a")
627
7
      ArchKind = llvm::AArch64::ArchKind::ARMV9A;
628
3.74k
    if (Feature == "+v9.1a")
629
1
      ArchKind = llvm::AArch64::ArchKind::ARMV9_1A;
630
3.74k
    if (Feature == "+v9.2a")
631
3
      ArchKind = llvm::AArch64::ArchKind::ARMV9_2A;
632
3.74k
    if (Feature == "+v9.3a")
633
4
      ArchKind = llvm::AArch64::ArchKind::ARMV9_3A;
634
3.74k
    if (Feature == "+v8r")
635
2
      ArchKind = llvm::AArch64::ArchKind::ARMV8R;
636
3.74k
    if (Feature == "+fullfp16")
637
72
      HasFullFP16 = true;
638
3.74k
    if (Feature == "+dotprod")
639
20
      HasDotProd = true;
640
3.74k
    if (Feature == "+fp16fml")
641
27
      HasFP16FML = true;
642
3.74k
    if (Feature == "+mte")
643
18
      HasMTE = true;
644
3.74k
    if (Feature == "+tme")
645
4
      HasTME = true;
646
3.74k
    if (Feature == "+pauth")
647
0
      HasPAuth = true;
648
3.74k
    if (Feature == "+i8mm")
649
37
      HasMatMul = true;
650
3.74k
    if (Feature == "+bf16")
651
344
      HasBFloat16 = true;
652
3.74k
    if (Feature == "+lse")
653
17
      HasLSE = true;
654
3.74k
    if (Feature == "+ls64")
655
6
      HasLS64 = true;
656
3.74k
    if (Feature == "+rand")
657
2
      HasRandGen = true;
658
3.74k
    if (Feature == "+flagm")
659
0
      HasFlagM = true;
660
3.74k
    if (Feature == "+mops")
661
11
      HasMOPS = true;
662
3.74k
  }
663
664
2.95k
  setDataLayout();
665
666
2.95k
  return true;
667
2.95k
}
668
669
TargetInfo::CallingConvCheckResult
670
490
AArch64TargetInfo::checkCallingConvention(CallingConv CC) const {
671
490
  switch (CC) {
672
4
  case CC_C:
673
324
  case CC_Swift:
674
455
  case CC_SwiftAsync:
675
460
  case CC_PreserveMost:
676
467
  case CC_PreserveAll:
677
467
  case CC_OpenCLKernel:
678
475
  case CC_AArch64VectorCall:
679
483
  case CC_AArch64SVEPCS:
680
490
  case CC_Win64:
681
490
    return CCCR_OK;
682
0
  default:
683
0
    return CCCR_Warning;
684
490
  }
685
490
}
686
687
33
bool AArch64TargetInfo::isCLZForZeroUndef() const { return false; }
688
689
2.62k
TargetInfo::BuiltinVaListKind AArch64TargetInfo::getBuiltinVaListKind() const {
690
2.62k
  return TargetInfo::AArch64ABIBuiltinVaList;
691
2.62k
}
692
693
const char *const AArch64TargetInfo::GCCRegNames[] = {
694
    // 32-bit Integer registers
695
    "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", "w11",
696
    "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", "w22",
697
    "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
698
699
    // 64-bit Integer registers
700
    "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11",
701
    "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22",
702
    "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp",
703
704
    // 32-bit floating point regsisters
705
    "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11",
706
    "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", "s22",
707
    "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
708
709
    // 64-bit floating point regsisters
710
    "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", "d11",
711
    "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", "d22",
712
    "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
713
714
    // Neon vector registers
715
    "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11",
716
    "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22",
717
    "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
718
719
    // SVE vector registers
720
    "z0",  "z1",  "z2",  "z3",  "z4",  "z5",  "z6",  "z7",  "z8",  "z9",  "z10",
721
    "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21",
722
    "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31",
723
724
    // SVE predicate registers
725
    "p0",  "p1",  "p2",  "p3",  "p4",  "p5",  "p6",  "p7",  "p8",  "p9",  "p10",
726
    "p11", "p12", "p13", "p14", "p15"
727
};
728
729
2.00k
ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const {
730
2.00k
  return llvm::makeArrayRef(GCCRegNames);
731
2.00k
}
732
733
const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
734
    {{"w31"}, "wsp"},
735
    {{"x31"}, "sp"},
736
    // GCC rN registers are aliases of xN registers.
737
    {{"r0"}, "x0"},
738
    {{"r1"}, "x1"},
739
    {{"r2"}, "x2"},
740
    {{"r3"}, "x3"},
741
    {{"r4"}, "x4"},
742
    {{"r5"}, "x5"},
743
    {{"r6"}, "x6"},
744
    {{"r7"}, "x7"},
745
    {{"r8"}, "x8"},
746
    {{"r9"}, "x9"},
747
    {{"r10"}, "x10"},
748
    {{"r11"}, "x11"},
749
    {{"r12"}, "x12"},
750
    {{"r13"}, "x13"},
751
    {{"r14"}, "x14"},
752
    {{"r15"}, "x15"},
753
    {{"r16"}, "x16"},
754
    {{"r17"}, "x17"},
755
    {{"r18"}, "x18"},
756
    {{"r19"}, "x19"},
757
    {{"r20"}, "x20"},
758
    {{"r21"}, "x21"},
759
    {{"r22"}, "x22"},
760
    {{"r23"}, "x23"},
761
    {{"r24"}, "x24"},
762
    {{"r25"}, "x25"},
763
    {{"r26"}, "x26"},
764
    {{"r27"}, "x27"},
765
    {{"r28"}, "x28"},
766
    {{"r29", "x29"}, "fp"},
767
    {{"r30", "x30"}, "lr"},
768
    // The S/D/Q and W/X registers overlap, but aren't really aliases; we
769
    // don't want to substitute one of these for a different-sized one.
770
};
771
772
828
ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const {
773
828
  return llvm::makeArrayRef(GCCRegAliases);
774
828
}
775
776
bool AArch64TargetInfo::validateAsmConstraint(
777
338
    const char *&Name, TargetInfo::ConstraintInfo &Info) const {
778
338
  switch (*Name) {
779
0
  default:
780
0
    return false;
781
284
  case 'w': // Floating point and SIMD registers (V0-V31)
782
284
    Info.setAllowsRegister();
783
284
    return true;
784
2
  case 'I': // Constant that can be used with an ADD instruction
785
2
  case 'J': // Constant that can be used with a SUB instruction
786
4
  case 'K': // Constant that can be used with a 32-bit logical instruction
787
6
  case 'L': // Constant that can be used with a 64-bit logical instruction
788
6
  case 'M': // Constant that can be used as a 32-bit MOV immediate
789
6
  case 'N': // Constant that can be used as a 64-bit MOV immediate
790
6
  case 'Y': // Floating point constant zero
791
6
  case 'Z': // Integer constant zero
792
6
    return true;
793
4
  case 'Q': // A memory reference with base register and no offset
794
4
    Info.setAllowsMemory();
795
4
    return true;
796
2
  case 'S': // A symbolic address
797
2
    Info.setAllowsRegister();
798
2
    return true;
799
32
  case 'U':
800
32
    if (Name[1] == 'p' && (Name[2] == 'l' || 
Name[2] == 'a'24
)) {
801
      // SVE predicate registers ("Upa"=P0-15, "Upl"=P0-P7)
802
32
      Info.setAllowsRegister();
803
32
      Name += 2;
804
32
      return true;
805
32
    }
806
    // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
807
    // Utf: A memory address suitable for ldp/stp in TF mode.
808
    // Usa: An absolute symbolic address.
809
    // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
810
811
    // Better to return an error saying that it's an unrecognised constraint
812
    // even if this is a valid constraint in gcc.
813
0
    return false;
814
4
  case 'z': // Zero register, wzr or xzr
815
4
    Info.setAllowsRegister();
816
4
    return true;
817
0
  case 'x': // Floating point and SIMD registers (V0-V15)
818
0
    Info.setAllowsRegister();
819
0
    return true;
820
6
  case 'y': // SVE registers (V0-V7)
821
6
    Info.setAllowsRegister();
822
6
    return true;
823
338
  }
824
0
  return false;
825
338
}
826
827
bool AArch64TargetInfo::validateConstraintModifier(
828
    StringRef Constraint, char Modifier, unsigned Size,
829
242
    std::string &SuggestedModifier) const {
830
  // Strip off constraint modifiers.
831
356
  while (Constraint[0] == '=' || 
Constraint[0] == '+'250
||
Constraint[0] == '&'243
)
832
114
    Constraint = Constraint.substr(1);
833
834
242
  switch (Constraint[0]) {
835
185
  default:
836
185
    return true;
837
4
  case 'z':
838
57
  case 'r': {
839
57
    switch (Modifier) {
840
1
    case 'x':
841
7
    case 'w':
842
      // For now assume that the person knows what they're
843
      // doing with the modifier.
844
7
      return true;
845
50
    default:
846
      // By default an 'r' constraint will be in the 'x'
847
      // registers.
848
50
      if (Size == 64)
849
26
        return true;
850
851
24
      if (Size == 512)
852
3
        return HasLS64;
853
854
21
      SuggestedModifier = "w";
855
21
      return false;
856
57
    }
857
57
  }
858
242
  }
859
242
}
860
861
103
const char *AArch64TargetInfo::getClobbers() const { return ""; }
862
863
0
int AArch64TargetInfo::getEHDataRegisterNumber(unsigned RegNo) const {
864
0
  if (RegNo == 0)
865
0
    return 0;
866
0
  if (RegNo == 1)
867
0
    return 1;
868
0
  return -1;
869
0
}
870
871
8.71k
bool AArch64TargetInfo::hasInt128Type() const { return true; }
872
873
AArch64leTargetInfo::AArch64leTargetInfo(const llvm::Triple &Triple,
874
                                         const TargetOptions &Opts)
875
2.92k
    : AArch64TargetInfo(Triple, Opts) {}
clang::targets::AArch64leTargetInfo::AArch64leTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
875
2.65k
    : AArch64TargetInfo(Triple, Opts) {}
clang::targets::AArch64leTargetInfo::AArch64leTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
875
272
    : AArch64TargetInfo(Triple, Opts) {}
876
877
2.86k
void AArch64leTargetInfo::setDataLayout() {
878
2.86k
  if (getTriple().isOSBinFormatMachO()) {
879
201
    if(getTriple().isArch32Bit())
880
16
      resetDataLayout("e-m:o-p:32:32-i64:64-i128:128-n32:64-S128", "_");
881
185
    else
882
185
      resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128", "_");
883
201
  } else
884
2.66k
    resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
885
2.86k
}
886
887
void AArch64leTargetInfo::getTargetDefines(const LangOptions &Opts,
888
2.91k
                                           MacroBuilder &Builder) const {
889
2.91k
  Builder.defineMacro("__AARCH64EL__");
890
2.91k
  AArch64TargetInfo::getTargetDefines(Opts, Builder);
891
2.91k
}
892
893
AArch64beTargetInfo::AArch64beTargetInfo(const llvm::Triple &Triple,
894
                                         const TargetOptions &Opts)
895
33
    : AArch64TargetInfo(Triple, Opts) {}
clang::targets::AArch64beTargetInfo::AArch64beTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
895
10
    : AArch64TargetInfo(Triple, Opts) {}
clang::targets::AArch64beTargetInfo::AArch64beTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
895
23
    : AArch64TargetInfo(Triple, Opts) {}
896
897
void AArch64beTargetInfo::getTargetDefines(const LangOptions &Opts,
898
33
                                           MacroBuilder &Builder) const {
899
33
  Builder.defineMacro("__AARCH64EB__");
900
33
  Builder.defineMacro("__AARCH_BIG_ENDIAN");
901
33
  Builder.defineMacro("__ARM_BIG_ENDIAN");
902
33
  AArch64TargetInfo::getTargetDefines(Opts, Builder);
903
33
}
904
905
33
void AArch64beTargetInfo::setDataLayout() {
906
33
  assert(!getTriple().isOSBinFormatMachO());
907
0
  resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
908
33
}
909
910
WindowsARM64TargetInfo::WindowsARM64TargetInfo(const llvm::Triple &Triple,
911
                                               const TargetOptions &Opts)
912
59
    : WindowsTargetInfo<AArch64leTargetInfo>(Triple, Opts), Triple(Triple) {
913
914
  // This is an LLP64 platform.
915
  // int:4, long:4, long long:8, long double:8.
916
59
  IntWidth = IntAlign = 32;
917
59
  LongWidth = LongAlign = 32;
918
59
  DoubleAlign = LongLongAlign = 64;
919
59
  LongDoubleWidth = LongDoubleAlign = 64;
920
59
  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
921
59
  IntMaxType = SignedLongLong;
922
59
  Int64Type = SignedLongLong;
923
59
  SizeType = UnsignedLongLong;
924
59
  PtrDiffType = SignedLongLong;
925
59
  IntPtrType = SignedLongLong;
926
59
}
clang::targets::WindowsARM64TargetInfo::WindowsARM64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
912
59
    : WindowsTargetInfo<AArch64leTargetInfo>(Triple, Opts), Triple(Triple) {
913
914
  // This is an LLP64 platform.
915
  // int:4, long:4, long long:8, long double:8.
916
59
  IntWidth = IntAlign = 32;
917
59
  LongWidth = LongAlign = 32;
918
59
  DoubleAlign = LongLongAlign = 64;
919
59
  LongDoubleWidth = LongDoubleAlign = 64;
920
59
  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
921
59
  IntMaxType = SignedLongLong;
922
59
  Int64Type = SignedLongLong;
923
59
  SizeType = UnsignedLongLong;
924
59
  PtrDiffType = SignedLongLong;
925
59
  IntPtrType = SignedLongLong;
926
59
}
Unexecuted instantiation: clang::targets::WindowsARM64TargetInfo::WindowsARM64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
927
928
59
void WindowsARM64TargetInfo::setDataLayout() {
929
59
  resetDataLayout(Triple.isOSBinFormatMachO()
930
59
                      ? 
"e-m:o-i64:64-i128:128-n32:64-S128"1
931
59
                      : 
"e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128"58
,
932
59
                  Triple.isOSBinFormatMachO() ? 
"_"1
:
""58
);
933
59
}
934
935
TargetInfo::BuiltinVaListKind
936
61
WindowsARM64TargetInfo::getBuiltinVaListKind() const {
937
61
  return TargetInfo::CharPtrBuiltinVaList;
938
61
}
939
940
TargetInfo::CallingConvCheckResult
941
63
WindowsARM64TargetInfo::checkCallingConvention(CallingConv CC) const {
942
63
  switch (CC) {
943
3
  case CC_X86StdCall:
944
5
  case CC_X86ThisCall:
945
6
  case CC_X86FastCall:
946
7
  case CC_X86VectorCall:
947
7
    return CCCR_Ignore;
948
43
  case CC_C:
949
43
  case CC_OpenCLKernel:
950
48
  case CC_PreserveMost:
951
53
  case CC_PreserveAll:
952
55
  case CC_Swift:
953
56
  case CC_SwiftAsync:
954
56
  case CC_Win64:
955
56
    return CCCR_OK;
956
0
  default:
957
0
    return CCCR_Warning;
958
63
  }
959
63
}
960
961
MicrosoftARM64TargetInfo::MicrosoftARM64TargetInfo(const llvm::Triple &Triple,
962
                                                   const TargetOptions &Opts)
963
56
    : WindowsARM64TargetInfo(Triple, Opts) {
964
56
  TheCXXABI.set(TargetCXXABI::Microsoft);
965
56
}
Unexecuted instantiation: clang::targets::MicrosoftARM64TargetInfo::MicrosoftARM64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::MicrosoftARM64TargetInfo::MicrosoftARM64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
963
56
    : WindowsARM64TargetInfo(Triple, Opts) {
964
56
  TheCXXABI.set(TargetCXXABI::Microsoft);
965
56
}
966
967
void MicrosoftARM64TargetInfo::getTargetDefines(const LangOptions &Opts,
968
56
                                                MacroBuilder &Builder) const {
969
56
  WindowsARM64TargetInfo::getTargetDefines(Opts, Builder);
970
56
  Builder.defineMacro("_M_ARM64", "1");
971
56
}
972
973
TargetInfo::CallingConvKind
974
110
MicrosoftARM64TargetInfo::getCallingConvKind(bool ClangABICompat4) const {
975
110
  return CCK_MicrosoftWin64;
976
110
}
977
978
163
unsigned MicrosoftARM64TargetInfo::getMinGlobalAlign(uint64_t TypeSize) const {
979
163
  unsigned Align = WindowsARM64TargetInfo::getMinGlobalAlign(TypeSize);
980
981
  // MSVC does size based alignment for arm64 based on alignment section in
982
  // below document, replicate that to keep alignment consistent with object
983
  // files compiled by MSVC.
984
  // https://docs.microsoft.com/en-us/cpp/build/arm64-windows-abi-conventions
985
163
  if (TypeSize >= 512) {              // TypeSize >= 64 bytes
986
10
    Align = std::max(Align, 128u);    // align type at least 16 bytes
987
153
  } else if (TypeSize >= 64) {        // TypeSize >= 8 bytes
988
57
    Align = std::max(Align, 64u);     // align type at least 8 butes
989
96
  } else if (TypeSize >= 16) {        // TypeSize >= 2 bytes
990
45
    Align = std::max(Align, 32u);     // align type at least 4 bytes
991
45
  }
992
163
  return Align;
993
163
}
994
995
MinGWARM64TargetInfo::MinGWARM64TargetInfo(const llvm::Triple &Triple,
996
                                           const TargetOptions &Opts)
997
3
    : WindowsARM64TargetInfo(Triple, Opts) {
998
3
  TheCXXABI.set(TargetCXXABI::GenericAArch64);
999
3
}
Unexecuted instantiation: clang::targets::MinGWARM64TargetInfo::MinGWARM64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::MinGWARM64TargetInfo::MinGWARM64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
997
3
    : WindowsARM64TargetInfo(Triple, Opts) {
998
3
  TheCXXABI.set(TargetCXXABI::GenericAArch64);
999
3
}
1000
1001
DarwinAArch64TargetInfo::DarwinAArch64TargetInfo(const llvm::Triple &Triple,
1002
                                                 const TargetOptions &Opts)
1003
200
    : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) {
1004
200
  Int64Type = SignedLongLong;
1005
200
  if (getTriple().isArch32Bit())
1006
16
    IntMaxType = SignedLongLong;
1007
1008
200
  WCharType = SignedInt;
1009
200
  UseSignedCharForObjCBool = false;
1010
1011
200
  LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
1012
200
  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
1013
1014
200
  UseZeroLengthBitfieldAlignment = false;
1015
1016
200
  if (getTriple().isArch32Bit()) {
1017
16
    UseBitFieldTypeAlignment = false;
1018
16
    ZeroLengthBitfieldBoundary = 32;
1019
16
    UseZeroLengthBitfieldAlignment = true;
1020
16
    TheCXXABI.set(TargetCXXABI::WatchOS);
1021
16
  } else
1022
184
    TheCXXABI.set(TargetCXXABI::AppleARM64);
1023
200
}
Unexecuted instantiation: clang::targets::DarwinAArch64TargetInfo::DarwinAArch64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::DarwinAArch64TargetInfo::DarwinAArch64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1003
200
    : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) {
1004
200
  Int64Type = SignedLongLong;
1005
200
  if (getTriple().isArch32Bit())
1006
16
    IntMaxType = SignedLongLong;
1007
1008
200
  WCharType = SignedInt;
1009
200
  UseSignedCharForObjCBool = false;
1010
1011
200
  LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
1012
200
  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
1013
1014
200
  UseZeroLengthBitfieldAlignment = false;
1015
1016
200
  if (getTriple().isArch32Bit()) {
1017
16
    UseBitFieldTypeAlignment = false;
1018
16
    ZeroLengthBitfieldBoundary = 32;
1019
16
    UseZeroLengthBitfieldAlignment = true;
1020
16
    TheCXXABI.set(TargetCXXABI::WatchOS);
1021
16
  } else
1022
184
    TheCXXABI.set(TargetCXXABI::AppleARM64);
1023
200
}
1024
1025
void DarwinAArch64TargetInfo::getOSDefines(const LangOptions &Opts,
1026
                                           const llvm::Triple &Triple,
1027
200
                                           MacroBuilder &Builder) const {
1028
200
  Builder.defineMacro("__AARCH64_SIMD__");
1029
200
  if (Triple.isArch32Bit())
1030
16
    Builder.defineMacro("__ARM64_ARCH_8_32__");
1031
184
  else
1032
184
    Builder.defineMacro("__ARM64_ARCH_8__");
1033
200
  Builder.defineMacro("__ARM_NEON__");
1034
200
  Builder.defineMacro("__LITTLE_ENDIAN__");
1035
200
  Builder.defineMacro("__REGISTER_PREFIX__", "");
1036
200
  Builder.defineMacro("__arm64", "1");
1037
200
  Builder.defineMacro("__arm64__", "1");
1038
1039
200
  if (Triple.isArm64e())
1040
5
    Builder.defineMacro("__arm64e__", "1");
1041
1042
200
  getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
1043
200
}
1044
1045
TargetInfo::BuiltinVaListKind
1046
212
DarwinAArch64TargetInfo::getBuiltinVaListKind() const {
1047
212
  return TargetInfo::CharPtrBuiltinVaList;
1048
212
}
1049
1050
// 64-bit RenderScript is aarch64
1051
RenderScript64TargetInfo::RenderScript64TargetInfo(const llvm::Triple &Triple,
1052
                                                   const TargetOptions &Opts)
1053
    : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(),
1054
                                       Triple.getOSName(),
1055
                                       Triple.getEnvironmentName()),
1056
1
                          Opts) {
1057
1
  IsRenderScriptTarget = true;
1058
1
}
clang::targets::RenderScript64TargetInfo::RenderScript64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1056
1
                          Opts) {
1057
1
  IsRenderScriptTarget = true;
1058
1
}
Unexecuted instantiation: clang::targets::RenderScript64TargetInfo::RenderScript64TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
1059
1060
void RenderScript64TargetInfo::getTargetDefines(const LangOptions &Opts,
1061
1
                                                MacroBuilder &Builder) const {
1062
1
  Builder.defineMacro("__RENDERSCRIPT__");
1063
1
  AArch64leTargetInfo::getTargetDefines(Opts, Builder);
1064
1
}