Coverage Report

Created: 2022-05-14 11:35

/Users/buildslave/jenkins/workspace/coverage/llvm-project/clang/lib/Basic/Targets/ARM.cpp
Line
Count
Source (jump to first uncovered line)
1
//===--- ARM.cpp - Implement ARM target feature support -------------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file implements ARM TargetInfo objects.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "ARM.h"
14
#include "clang/Basic/Builtins.h"
15
#include "clang/Basic/Diagnostic.h"
16
#include "clang/Basic/TargetBuiltins.h"
17
#include "llvm/ADT/StringExtras.h"
18
#include "llvm/ADT/StringRef.h"
19
#include "llvm/ADT/StringSwitch.h"
20
21
using namespace clang;
22
using namespace clang::targets;
23
24
1.61k
void ARMTargetInfo::setABIAAPCS() {
25
1.61k
  IsAAPCS = true;
26
27
1.61k
  DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
28
1.61k
  BFloat16Width = BFloat16Align = 16;
29
1.61k
  BFloat16Format = &llvm::APFloat::BFloat();
30
31
1.61k
  const llvm::Triple &T = getTriple();
32
33
1.61k
  bool IsNetBSD = T.isOSNetBSD();
34
1.61k
  bool IsOpenBSD = T.isOSOpenBSD();
35
1.61k
  if (!T.isOSWindows() && 
!IsNetBSD1.46k
&&
!IsOpenBSD1.45k
)
36
1.45k
    WCharType = UnsignedInt;
37
38
1.61k
  UseBitFieldTypeAlignment = true;
39
40
1.61k
  ZeroLengthBitfieldBoundary = 0;
41
42
  // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
43
  // so set preferred for small types to 32.
44
1.61k
  if (T.isOSBinFormatMachO()) {
45
32
    resetDataLayout(BigEndian
46
32
                        ? 
"E-m:o-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"0
47
32
                        : "e-m:o-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64",
48
32
                    "_");
49
1.57k
  } else if (T.isOSWindows()) {
50
142
    assert(!BigEndian && "Windows on ARM does not support big endian");
51
0
    resetDataLayout("e"
52
142
                    "-m:w"
53
142
                    "-p:32:32"
54
142
                    "-Fi8"
55
142
                    "-i64:64"
56
142
                    "-v128:64:128"
57
142
                    "-a:0:32"
58
142
                    "-n32"
59
142
                    "-S64");
60
1.43k
  } else if (T.isOSNaCl()) {
61
2
    assert(!BigEndian && "NaCl on ARM does not support big endian");
62
0
    resetDataLayout("e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S128");
63
1.43k
  } else {
64
1.43k
    resetDataLayout(BigEndian
65
1.43k
                        ? 
"E-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"42
66
1.43k
                        : 
"e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"1.39k
);
67
1.43k
  }
68
69
  // FIXME: Enumerated types are variable width in straight AAPCS.
70
1.61k
}
71
72
283
void ARMTargetInfo::setABIAPCS(bool IsAAPCS16) {
73
283
  const llvm::Triple &T = getTriple();
74
75
283
  IsAAPCS = false;
76
77
283
  if (IsAAPCS16)
78
37
    DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
79
246
  else
80
246
    DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
81
283
  BFloat16Width = BFloat16Align = 16;
82
283
  BFloat16Format = &llvm::APFloat::BFloat();
83
84
283
  WCharType = SignedInt;
85
86
  // Do not respect the alignment of bit-field types when laying out
87
  // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
88
283
  UseBitFieldTypeAlignment = false;
89
90
  /// gcc forces the alignment to 4 bytes, regardless of the type of the
91
  /// zero length bitfield.  This corresponds to EMPTY_FIELD_BOUNDARY in
92
  /// gcc.
93
283
  ZeroLengthBitfieldBoundary = 32;
94
95
283
  if (T.isOSBinFormatMachO() && 
IsAAPCS16236
) {
96
37
    assert(!BigEndian && "AAPCS16 does not support big-endian");
97
0
    resetDataLayout("e-m:o-p:32:32-Fi8-i64:64-a:0:32-n32-S128", "_");
98
246
  } else if (T.isOSBinFormatMachO())
99
199
    resetDataLayout(
100
199
        BigEndian
101
199
            ? 
"E-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"0
102
199
            : "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32",
103
199
        "_");
104
47
  else
105
47
    resetDataLayout(
106
47
        BigEndian
107
47
            ? 
"E-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"0
108
47
            : "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32");
109
110
  // FIXME: Override "preferred align" for double and long long.
111
283
}
112
113
1.32k
void ARMTargetInfo::setArchInfo() {
114
1.32k
  StringRef ArchName = getTriple().getArchName();
115
116
1.32k
  ArchISA = llvm::ARM::parseArchISA(ArchName);
117
1.32k
  CPU = std::string(llvm::ARM::getDefaultCPU(ArchName));
118
1.32k
  llvm::ARM::ArchKind AK = llvm::ARM::parseArch(ArchName);
119
1.32k
  if (AK != llvm::ARM::ArchKind::INVALID)
120
1.18k
    ArchKind = AK;
121
1.32k
  setArchInfo(ArchKind);
122
1.32k
}
123
124
1.71k
void ARMTargetInfo::setArchInfo(llvm::ARM::ArchKind Kind) {
125
1.71k
  StringRef SubArch;
126
127
  // cache TargetParser info
128
1.71k
  ArchKind = Kind;
129
1.71k
  SubArch = llvm::ARM::getSubArch(ArchKind);
130
1.71k
  ArchProfile = llvm::ARM::parseArchProfile(SubArch);
131
1.71k
  ArchVersion = llvm::ARM::parseArchVersion(SubArch);
132
133
  // cache CPU related strings
134
1.71k
  CPUAttr = getCPUAttr();
135
1.71k
  CPUProfile = getCPUProfile();
136
1.71k
}
137
138
1.90k
void ARMTargetInfo::setAtomic() {
139
  // when triple does not specify a sub arch,
140
  // then we are not using inline atomics
141
1.90k
  bool ShouldUseInlineAtomic =
142
1.90k
      (ArchISA == llvm::ARM::ISAKind::ARM && 
ArchVersion >= 61.00k
) ||
143
1.90k
      
(1.14k
ArchISA == llvm::ARM::ISAKind::THUMB1.14k
&&
ArchVersion >= 7898
);
144
  // Cortex M does not support 8 byte atomics, while general Thumb2 does.
145
1.90k
  if (ArchProfile == llvm::ARM::ProfileKind::M) {
146
416
    MaxAtomicPromoteWidth = 32;
147
416
    if (ShouldUseInlineAtomic)
148
386
      MaxAtomicInlineWidth = 32;
149
1.48k
  } else {
150
1.48k
    MaxAtomicPromoteWidth = 64;
151
1.48k
    if (ShouldUseInlineAtomic)
152
1.21k
      MaxAtomicInlineWidth = 64;
153
1.48k
  }
154
1.90k
}
155
156
6.98k
bool ARMTargetInfo::hasMVE() const {
157
6.98k
  return ArchKind == llvm::ARM::ArchKind::ARMV8_1MMainline && 
MVE != 03.67k
;
158
6.98k
}
159
160
164
bool ARMTargetInfo::hasMVEFloat() const {
161
164
  return hasMVE() && (MVE & MVE_FP);
162
164
}
163
164
1.31k
bool ARMTargetInfo::hasCDE() const { return getARMCDECoprocMask() != 0; }
165
166
8.83k
bool ARMTargetInfo::isThumb() const {
167
8.83k
  return ArchISA == llvm::ARM::ISAKind::THUMB;
168
8.83k
}
169
170
277
bool ARMTargetInfo::supportsThumb() const {
171
277
  return CPUAttr.count('T') || 
ArchVersion >= 692
;
172
277
}
173
174
1.98k
bool ARMTargetInfo::supportsThumb2() const {
175
1.98k
  return CPUAttr.equals("6T2") ||
176
1.98k
         
(1.98k
ArchVersion >= 71.98k
&&
!CPUAttr.equals("8M_BASE")1.67k
);
177
1.98k
}
178
179
1.71k
StringRef ARMTargetInfo::getCPUAttr() const {
180
  // For most sub-arches, the build attribute CPU name is enough.
181
  // For Cortex variants, it's slightly different.
182
1.71k
  switch (ArchKind) {
183
356
  default:
184
356
    return llvm::ARM::getCPUAttr(ArchKind);
185
31
  case llvm::ARM::ArchKind::ARMV6M:
186
31
    return "6M";
187
26
  case llvm::ARM::ArchKind::ARMV7S:
188
26
    return "7S";
189
630
  case llvm::ARM::ArchKind::ARMV7A:
190
630
    return "7A";
191
57
  case llvm::ARM::ArchKind::ARMV7R:
192
57
    return "7R";
193
47
  case llvm::ARM::ArchKind::ARMV7M:
194
47
    return "7M";
195
31
  case llvm::ARM::ArchKind::ARMV7EM:
196
31
    return "7EM";
197
7
  case llvm::ARM::ArchKind::ARMV7VE:
198
7
    return "7VE";
199
172
  case llvm::ARM::ArchKind::ARMV8A:
200
172
    return "8A";
201
5
  case llvm::ARM::ArchKind::ARMV8_1A:
202
5
    return "8_1A";
203
33
  case llvm::ARM::ArchKind::ARMV8_2A:
204
33
    return "8_2A";
205
3
  case llvm::ARM::ArchKind::ARMV8_3A:
206
3
    return "8_3A";
207
17
  case llvm::ARM::ArchKind::ARMV8_4A:
208
17
    return "8_4A";
209
2
  case llvm::ARM::ArchKind::ARMV8_5A:
210
2
    return "8_5A";
211
11
  case llvm::ARM::ArchKind::ARMV8_6A:
212
11
    return "8_6A";
213
2
  case llvm::ARM::ArchKind::ARMV8_7A:
214
2
    return "8_7A";
215
2
  case llvm::ARM::ArchKind::ARMV8_8A:
216
2
    return "8_8A";
217
2
  case llvm::ARM::ArchKind::ARMV9A:
218
2
    return "9A";
219
2
  case llvm::ARM::ArchKind::ARMV9_1A:
220
2
    return "9_1A";
221
2
  case llvm::ARM::ArchKind::ARMV9_2A:
222
2
    return "9_2A";
223
2
  case llvm::ARM::ArchKind::ARMV9_3A:
224
2
    return "9_3A";
225
32
  case llvm::ARM::ArchKind::ARMV8MBaseline:
226
32
    return "8M_BASE";
227
39
  case llvm::ARM::ArchKind::ARMV8MMainline:
228
39
    return "8M_MAIN";
229
10
  case llvm::ARM::ArchKind::ARMV8R:
230
10
    return "8R";
231
195
  case llvm::ARM::ArchKind::ARMV8_1MMainline:
232
195
    return "8_1M_MAIN";
233
1.71k
  }
234
1.71k
}
235
236
1.71k
StringRef ARMTargetInfo::getCPUProfile() const {
237
1.71k
  switch (ArchProfile) {
238
921
  case llvm::ARM::ProfileKind::A:
239
921
    return "A";
240
67
  case llvm::ARM::ProfileKind::R:
241
67
    return "R";
242
375
  case llvm::ARM::ProfileKind::M:
243
375
    return "M";
244
353
  default:
245
353
    return "";
246
1.71k
  }
247
1.71k
}
248
249
ARMTargetInfo::ARMTargetInfo(const llvm::Triple &Triple,
250
                             const TargetOptions &Opts)
251
    : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0),
252
1.32k
      HW_FP(0) {
253
1.32k
  bool IsOpenBSD = Triple.isOSOpenBSD();
254
1.32k
  bool IsNetBSD = Triple.isOSNetBSD();
255
256
  // FIXME: the isOSBinFormatMachO is a workaround for identifying a Darwin-like
257
  // environment where size_t is `unsigned long` rather than `unsigned int`
258
259
1.32k
  PtrDiffType = IntPtrType =
260
1.32k
      (Triple.isOSDarwin() || 
Triple.isOSBinFormatMachO()1.12k
||
IsOpenBSD1.11k
||
261
1.32k
       
IsNetBSD1.10k
)
262
1.32k
          ? 
SignedLong227
263
1.32k
          : 
SignedInt1.10k
;
264
265
1.32k
  SizeType = (Triple.isOSDarwin() || 
Triple.isOSBinFormatMachO()1.12k
||
IsOpenBSD1.11k
||
266
1.32k
              
IsNetBSD1.10k
)
267
1.32k
                 ? 
UnsignedLong227
268
1.32k
                 : 
UnsignedInt1.10k
;
269
270
  // ptrdiff_t is inconsistent on Darwin
271
1.32k
  if ((Triple.isOSDarwin() || 
Triple.isOSBinFormatMachO()1.12k
) &&
272
1.32k
      
!Triple.isWatchABI()214
)
273
185
    PtrDiffType = SignedInt;
274
275
  // Cache arch related info.
276
1.32k
  setArchInfo();
277
278
  // {} in inline assembly are neon specifiers, not assembly variant
279
  // specifiers.
280
1.32k
  NoAsmVariants = true;
281
282
  // FIXME: This duplicates code from the driver that sets the -target-abi
283
  // option - this code is used if -target-abi isn't passed and should
284
  // be unified in some way.
285
1.32k
  if (Triple.isOSBinFormatMachO()) {
286
    // The backend is hardwired to assume AAPCS for M-class processors, ensure
287
    // the frontend matches that.
288
214
    if (Triple.getEnvironment() == llvm::Triple::EABI ||
289
214
        
Triple.getOS() == llvm::Triple::UnknownOS213
||
290
214
        
ArchProfile == llvm::ARM::ProfileKind::M198
) {
291
16
      setABI("aapcs");
292
198
    } else if (Triple.isWatchABI()) {
293
29
      setABI("aapcs16");
294
169
    } else {
295
169
      setABI("apcs-gnu");
296
169
    }
297
1.11k
  } else if (Triple.isOSWindows()) {
298
    // FIXME: this is invalid for WindowsCE
299
119
    setABI("aapcs");
300
995
  } else {
301
    // Select the default based on the platform.
302
995
    switch (Triple.getEnvironment()) {
303
14
    case llvm::Triple::Android:
304
163
    case llvm::Triple::GNUEABI:
305
226
    case llvm::Triple::GNUEABIHF:
306
230
    case llvm::Triple::MuslEABI:
307
232
    case llvm::Triple::MuslEABIHF:
308
232
      setABI("aapcs-linux");
309
232
      break;
310
16
    case llvm::Triple::EABIHF:
311
525
    case llvm::Triple::EABI:
312
525
      setABI("aapcs");
313
525
      break;
314
31
    case llvm::Triple::GNU:
315
31
      setABI("apcs-gnu");
316
31
      break;
317
207
    default:
318
207
      if (IsNetBSD)
319
0
        setABI("apcs-gnu");
320
207
      else if (IsOpenBSD)
321
3
        setABI("aapcs-linux");
322
204
      else
323
204
        setABI("aapcs");
324
207
      break;
325
995
    }
326
995
  }
327
328
  // ARM targets default to using the ARM C++ ABI.
329
1.32k
  TheCXXABI.set(TargetCXXABI::GenericARM);
330
331
  // ARM has atomics up to 8 bytes
332
1.32k
  setAtomic();
333
334
  // Maximum alignment for ARM NEON data types should be 64-bits (AAPCS)
335
  // as well the default alignment
336
1.32k
  if (IsAAPCS && 
!Triple.isAndroid()1.09k
)
337
1.08k
    DefaultAlignForAttributeAligned = MaxVectorAlign = 64;
338
339
  // Do force alignment of members that follow zero length bitfields.  If
340
  // the alignment of the zero-length bitfield is greater than the member
341
  // that follows it, `bar', `bar' will be aligned as the  type of the
342
  // zero length bitfield.
343
1.32k
  UseZeroLengthBitfieldAlignment = true;
344
345
1.32k
  if (Triple.getOS() == llvm::Triple::Linux ||
346
1.32k
      
Triple.getOS() == llvm::Triple::UnknownOS1.03k
)
347
984
    this->MCountName = Opts.EABIVersion == llvm::EABI::GNU
348
984
                           ? 
"llvm.arm.gnu.eabi.mcount"9
349
984
                           : 
"\01mcount"975
;
350
351
1.32k
  SoftFloatABI = llvm::is_contained(Opts.FeaturesAsWritten, "+soft-float-abi");
352
1.32k
}
clang::targets::ARMTargetInfo::ARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
252
1.32k
      HW_FP(0) {
253
1.32k
  bool IsOpenBSD = Triple.isOSOpenBSD();
254
1.32k
  bool IsNetBSD = Triple.isOSNetBSD();
255
256
  // FIXME: the isOSBinFormatMachO is a workaround for identifying a Darwin-like
257
  // environment where size_t is `unsigned long` rather than `unsigned int`
258
259
1.32k
  PtrDiffType = IntPtrType =
260
1.32k
      (Triple.isOSDarwin() || 
Triple.isOSBinFormatMachO()1.12k
||
IsOpenBSD1.11k
||
261
1.32k
       
IsNetBSD1.10k
)
262
1.32k
          ? 
SignedLong227
263
1.32k
          : 
SignedInt1.10k
;
264
265
1.32k
  SizeType = (Triple.isOSDarwin() || 
Triple.isOSBinFormatMachO()1.12k
||
IsOpenBSD1.11k
||
266
1.32k
              
IsNetBSD1.10k
)
267
1.32k
                 ? 
UnsignedLong227
268
1.32k
                 : 
UnsignedInt1.10k
;
269
270
  // ptrdiff_t is inconsistent on Darwin
271
1.32k
  if ((Triple.isOSDarwin() || 
Triple.isOSBinFormatMachO()1.12k
) &&
272
1.32k
      
!Triple.isWatchABI()214
)
273
185
    PtrDiffType = SignedInt;
274
275
  // Cache arch related info.
276
1.32k
  setArchInfo();
277
278
  // {} in inline assembly are neon specifiers, not assembly variant
279
  // specifiers.
280
1.32k
  NoAsmVariants = true;
281
282
  // FIXME: This duplicates code from the driver that sets the -target-abi
283
  // option - this code is used if -target-abi isn't passed and should
284
  // be unified in some way.
285
1.32k
  if (Triple.isOSBinFormatMachO()) {
286
    // The backend is hardwired to assume AAPCS for M-class processors, ensure
287
    // the frontend matches that.
288
214
    if (Triple.getEnvironment() == llvm::Triple::EABI ||
289
214
        
Triple.getOS() == llvm::Triple::UnknownOS213
||
290
214
        
ArchProfile == llvm::ARM::ProfileKind::M198
) {
291
16
      setABI("aapcs");
292
198
    } else if (Triple.isWatchABI()) {
293
29
      setABI("aapcs16");
294
169
    } else {
295
169
      setABI("apcs-gnu");
296
169
    }
297
1.11k
  } else if (Triple.isOSWindows()) {
298
    // FIXME: this is invalid for WindowsCE
299
119
    setABI("aapcs");
300
995
  } else {
301
    // Select the default based on the platform.
302
995
    switch (Triple.getEnvironment()) {
303
14
    case llvm::Triple::Android:
304
163
    case llvm::Triple::GNUEABI:
305
226
    case llvm::Triple::GNUEABIHF:
306
230
    case llvm::Triple::MuslEABI:
307
232
    case llvm::Triple::MuslEABIHF:
308
232
      setABI("aapcs-linux");
309
232
      break;
310
16
    case llvm::Triple::EABIHF:
311
525
    case llvm::Triple::EABI:
312
525
      setABI("aapcs");
313
525
      break;
314
31
    case llvm::Triple::GNU:
315
31
      setABI("apcs-gnu");
316
31
      break;
317
207
    default:
318
207
      if (IsNetBSD)
319
0
        setABI("apcs-gnu");
320
207
      else if (IsOpenBSD)
321
3
        setABI("aapcs-linux");
322
204
      else
323
204
        setABI("aapcs");
324
207
      break;
325
995
    }
326
995
  }
327
328
  // ARM targets default to using the ARM C++ ABI.
329
1.32k
  TheCXXABI.set(TargetCXXABI::GenericARM);
330
331
  // ARM has atomics up to 8 bytes
332
1.32k
  setAtomic();
333
334
  // Maximum alignment for ARM NEON data types should be 64-bits (AAPCS)
335
  // as well the default alignment
336
1.32k
  if (IsAAPCS && 
!Triple.isAndroid()1.09k
)
337
1.08k
    DefaultAlignForAttributeAligned = MaxVectorAlign = 64;
338
339
  // Do force alignment of members that follow zero length bitfields.  If
340
  // the alignment of the zero-length bitfield is greater than the member
341
  // that follows it, `bar', `bar' will be aligned as the  type of the
342
  // zero length bitfield.
343
1.32k
  UseZeroLengthBitfieldAlignment = true;
344
345
1.32k
  if (Triple.getOS() == llvm::Triple::Linux ||
346
1.32k
      
Triple.getOS() == llvm::Triple::UnknownOS1.03k
)
347
984
    this->MCountName = Opts.EABIVersion == llvm::EABI::GNU
348
984
                           ? 
"llvm.arm.gnu.eabi.mcount"9
349
984
                           : 
"\01mcount"975
;
350
351
1.32k
  SoftFloatABI = llvm::is_contained(Opts.FeaturesAsWritten, "+soft-float-abi");
352
1.32k
}
Unexecuted instantiation: clang::targets::ARMTargetInfo::ARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
353
354
2.81k
StringRef ARMTargetInfo::getABI() const { return ABI; }
355
356
1.89k
bool ARMTargetInfo::setABI(const std::string &Name) {
357
1.89k
  ABI = Name;
358
359
  // The defaults (above) are for AAPCS, check if we need to change them.
360
  //
361
  // FIXME: We need support for -meabi... we could just mangle it into the
362
  // name.
363
1.89k
  if (Name == "apcs-gnu" || 
Name == "aapcs16"1.64k
) {
364
283
    setABIAPCS(Name == "aapcs16");
365
283
    return true;
366
283
  }
367
1.61k
  if (Name == "aapcs" || 
Name == "aapcs-vfp"329
||
Name == "aapcs-linux"328
) {
368
1.61k
    setABIAAPCS();
369
1.61k
    return true;
370
1.61k
  }
371
0
  return false;
372
1.61k
}
373
374
45
bool ARMTargetInfo::isBranchProtectionSupportedArch(StringRef Arch) const {
375
45
  llvm::ARM::ArchKind CPUArch = llvm::ARM::parseCPUArch(Arch);
376
45
  if (CPUArch == llvm::ARM::ArchKind::INVALID)
377
23
    CPUArch = llvm::ARM::parseArch(getTriple().getArchName());
378
379
45
  if (CPUArch == llvm::ARM::ArchKind::INVALID)
380
0
    return false;
381
382
45
  StringRef ArchFeature = llvm::ARM::getArchName(CPUArch);
383
45
  auto a =
384
45
      llvm::Triple(ArchFeature, getTriple().getVendorName(),
385
45
                   getTriple().getOSName(), getTriple().getEnvironmentName());
386
387
45
  StringRef SubArch = llvm::ARM::getSubArch(CPUArch);
388
45
  llvm::ARM::ProfileKind Profile = llvm::ARM::parseArchProfile(SubArch);
389
45
  return a.isArmT32() && 
(Profile == llvm::ARM::ProfileKind::M)36
;
390
45
}
391
392
bool ARMTargetInfo::validateBranchProtection(StringRef Spec, StringRef Arch,
393
                                             BranchProtectionInfo &BPI,
394
51
                                             StringRef &Err) const {
395
51
  llvm::ARM::ParsedBranchProtection PBP;
396
51
  if (!llvm::ARM::parseBranchProtection(Spec, PBP, Err))
397
7
    return false;
398
399
44
  if (!isBranchProtectionSupportedArch(Arch))
400
9
    return false;
401
402
35
  BPI.SignReturnAddr =
403
35
      llvm::StringSwitch<LangOptions::SignReturnAddressScopeKind>(PBP.Scope)
404
35
          .Case("non-leaf", LangOptions::SignReturnAddressScopeKind::NonLeaf)
405
35
          .Case("all", LangOptions::SignReturnAddressScopeKind::All)
406
35
          .Default(LangOptions::SignReturnAddressScopeKind::None);
407
408
  // Don't care for the sign key, beyond issuing a warning.
409
35
  if (PBP.Key == "b_key")
410
3
    Err = "b-key";
411
35
  BPI.SignKey = LangOptions::SignReturnAddressKeyKind::AKey;
412
413
35
  BPI.BranchTargetEnforcement = PBP.BranchTargetEnforcement;
414
35
  return true;
415
44
}
416
417
// FIXME: This should be based on Arch attributes, not CPU names.
418
bool ARMTargetInfo::initFeatureMap(
419
    llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
420
1.38k
    const std::vector<std::string> &FeaturesVec) const {
421
422
1.38k
  std::string ArchFeature;
423
1.38k
  std::vector<StringRef> TargetFeatures;
424
1.38k
  llvm::ARM::ArchKind Arch = llvm::ARM::parseArch(getTriple().getArchName());
425
426
  // Map the base architecture to an appropriate target feature, so we don't
427
  // rely on the target triple.
428
1.38k
  llvm::ARM::ArchKind CPUArch = llvm::ARM::parseCPUArch(CPU);
429
1.38k
  if (CPUArch == llvm::ARM::ArchKind::INVALID)
430
996
    CPUArch = Arch;
431
1.38k
  if (CPUArch != llvm::ARM::ArchKind::INVALID) {
432
1.24k
    ArchFeature = ("+" + llvm::ARM::getArchName(CPUArch)).str();
433
1.24k
    TargetFeatures.push_back(ArchFeature);
434
1.24k
  }
435
436
  // get default FPU features
437
1.38k
  unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch);
438
1.38k
  llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures);
439
440
  // get default Extension features
441
1.38k
  uint64_t Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch);
442
1.38k
  llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures);
443
444
1.38k
  for (auto Feature : TargetFeatures)
445
28.6k
    if (Feature[0] == '+')
446
8.83k
      Features[Feature.drop_front(1)] = true;
447
448
  // Enable or disable thumb-mode explicitly per function to enable mixed
449
  // ARM and Thumb code generation.
450
1.38k
  if (isThumb())
451
677
    Features["thumb-mode"] = true;
452
707
  else
453
707
    Features["thumb-mode"] = false;
454
455
  // Convert user-provided arm and thumb GNU target attributes to
456
  // [-|+]thumb-mode target features respectively.
457
1.38k
  std::vector<std::string> UpdatedFeaturesVec;
458
16.4k
  for (const auto &Feature : FeaturesVec) {
459
    // Skip soft-float-abi; it's something we only use to initialize a bit of
460
    // class state, and is otherwise unrecognized.
461
16.4k
    if (Feature == "+soft-float-abi")
462
438
      continue;
463
464
15.9k
    StringRef FixedFeature;
465
15.9k
    if (Feature == "+arm")
466
8
      FixedFeature = "-thumb-mode";
467
15.9k
    else if (Feature == "+thumb")
468
8
      FixedFeature = "+thumb-mode";
469
15.9k
    else
470
15.9k
      FixedFeature = Feature;
471
15.9k
    UpdatedFeaturesVec.push_back(FixedFeature.str());
472
15.9k
  }
473
474
1.38k
  return TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec);
475
1.38k
}
476
477
478
bool ARMTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
479
1.32k
                                         DiagnosticsEngine &Diags) {
480
1.32k
  FPU = 0;
481
1.32k
  MVE = 0;
482
1.32k
  CRC = 0;
483
1.32k
  Crypto = 0;
484
1.32k
  SHA2 = 0;
485
1.32k
  AES = 0;
486
1.32k
  DSP = 0;
487
1.32k
  Unaligned = 1;
488
1.32k
  SoftFloat = false;
489
  // Note that SoftFloatABI is initialized in our constructor.
490
1.32k
  HWDiv = 0;
491
1.32k
  DotProd = 0;
492
1.32k
  HasMatMul = 0;
493
1.32k
  HasPAC = 0;
494
1.32k
  HasBTI = 0;
495
1.32k
  HasFloat16 = true;
496
1.32k
  ARMCDECoprocMask = 0;
497
1.32k
  HasBFloat16 = false;
498
1.32k
  FPRegsDisabled = false;
499
500
  // This does not diagnose illegal cases like having both
501
  // "+vfpv2" and "+vfpv3" or having "+neon" and "-fp64".
502
20.2k
  for (const auto &Feature : Features) {
503
20.2k
    if (Feature == "+soft-float") {
504
124
      SoftFloat = true;
505
20.0k
    } else if (Feature == "+vfp2sp" || 
Feature == "+vfp2"19.7k
) {
506
721
      FPU |= VFP2FPU;
507
721
      HW_FP |= HW_FP_SP;
508
721
      if (Feature == "+vfp2")
509
337
          HW_FP |= HW_FP_DP;
510
19.3k
    } else if (Feature == "+vfp3sp" || 
Feature == "+vfp3d16sp"19.0k
||
511
19.3k
               
Feature == "+vfp3"18.7k
||
Feature == "+vfp3d16"18.4k
) {
512
1.27k
      FPU |= VFP3FPU;
513
1.27k
      HW_FP |= HW_FP_SP;
514
1.27k
      if (Feature == "+vfp3" || 
Feature == "+vfp3d16"986
)
515
615
          HW_FP |= HW_FP_DP;
516
18.0k
    } else if (Feature == "+vfp4sp" || 
Feature == "+vfp4d16sp"17.9k
||
517
18.0k
               
Feature == "+vfp4"17.6k
||
Feature == "+vfp4d16"17.4k
) {
518
826
      FPU |= VFP4FPU;
519
826
      HW_FP |= HW_FP_SP | HW_FP_HP;
520
826
      if (Feature == "+vfp4" || 
Feature == "+vfp4d16"638
)
521
391
          HW_FP |= HW_FP_DP;
522
17.2k
    } else if (Feature == "+fp-armv8sp" || 
Feature == "+fp-armv8d16sp"17.1k
||
523
17.2k
               
Feature == "+fp-armv8"16.9k
||
Feature == "+fp-armv8d16"16.8k
) {
524
550
      FPU |= FPARMV8;
525
550
      HW_FP |= HW_FP_SP | HW_FP_HP;
526
550
      if (Feature == "+fp-armv8" || 
Feature == "+fp-armv8d16"428
)
527
257
          HW_FP |= HW_FP_DP;
528
16.7k
    } else if (Feature == "+neon") {
529
321
      FPU |= NeonFPU;
530
321
      HW_FP |= HW_FP_SP;
531
16.3k
    } else if (Feature == "+hwdiv") {
532
365
      HWDiv |= HWDivThumb;
533
16.0k
    } else if (Feature == "+hwdiv-arm") {
534
257
      HWDiv |= HWDivARM;
535
15.7k
    } else if (Feature == "+crc") {
536
165
      CRC = 1;
537
15.6k
    } else if (Feature == "+crypto") {
538
19
      Crypto = 1;
539
15.5k
    } else if (Feature == "+sha2") {
540
105
      SHA2 = 1;
541
15.4k
    } else if (Feature == "+aes") {
542
105
      AES = 1;
543
15.3k
    } else if (Feature == "+dsp") {
544
447
      DSP = 1;
545
14.9k
    } else if (Feature == "+fp64") {
546
336
      HW_FP |= HW_FP_DP;
547
14.5k
    } else if (Feature == "+8msecext") {
548
6
      if (CPUProfile != "M" || ArchVersion != 8) {
549
1
        Diags.Report(diag::err_target_unsupported_mcmse) << CPU;
550
1
        return false;
551
1
      }
552
14.5k
    } else if (Feature == "+strict-align") {
553
350
      Unaligned = 0;
554
14.2k
    } else if (Feature == "+fp16") {
555
292
      HW_FP |= HW_FP_HP;
556
13.9k
    } else if (Feature == "+fullfp16") {
557
52
      HasLegalHalfType = true;
558
13.8k
    } else if (Feature == "+dotprod") {
559
39
      DotProd = true;
560
13.8k
    } else if (Feature == "+mve") {
561
27
      MVE |= MVE_INT;
562
13.8k
    } else if (Feature == "+mve.fp") {
563
140
      HasLegalHalfType = true;
564
140
      FPU |= FPARMV8;
565
140
      MVE |= MVE_INT | MVE_FP;
566
140
      HW_FP |= HW_FP_SP | HW_FP_HP;
567
13.6k
    } else if (Feature == "+i8mm") {
568
14
      HasMatMul = 1;
569
13.6k
    } else if (Feature.size() == strlen("+cdecp0") && 
Feature >= "+cdecp0"3.01k
&&
570
13.6k
               
Feature <= "+cdecp7"2.91k
) {
571
26
      unsigned Coproc = Feature.back() - '0';
572
26
      ARMCDECoprocMask |= (1U << Coproc);
573
13.6k
    } else if (Feature == "+bf16") {
574
28
      HasBFloat16 = true;
575
13.6k
    } else if (Feature == "-fpregs") {
576
176
      FPRegsDisabled = true;
577
13.4k
    } else if (Feature == "+pacbti") {
578
1
      HasPAC = 1;
579
1
      HasBTI = 1;
580
1
    }
581
20.2k
  }
582
583
1.32k
  switch (ArchVersion) {
584
61
  case 6:
585
61
    if (ArchProfile == llvm::ARM::ProfileKind::M)
586
18
      LDREX = 0;
587
43
    else if (ArchKind == llvm::ARM::ArchKind::ARMV6K)
588
3
      LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B;
589
40
    else
590
40
      LDREX = LDREX_W;
591
61
    break;
592
612
  case 7:
593
612
    if (ArchProfile == llvm::ARM::ProfileKind::M)
594
44
      LDREX = LDREX_W | LDREX_H | LDREX_B;
595
568
    else
596
568
      LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B;
597
612
    break;
598
452
  case 8:
599
460
  case 9:
600
460
    LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B;
601
1.32k
  }
602
603
1.32k
  if (!(FPU & NeonFPU) && 
FPMath == FP_Neon1.00k
) {
604
2
    Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
605
2
    return false;
606
2
  }
607
608
1.32k
  if (FPMath == FP_Neon)
609
1
    Features.push_back("+neonfp");
610
1.32k
  else if (FPMath == FP_VFP)
611
5
    Features.push_back("-neonfp");
612
613
1.32k
  return true;
614
1.32k
}
615
616
5.50k
bool ARMTargetInfo::hasFeature(StringRef Feature) const {
617
5.50k
  return llvm::StringSwitch<bool>(Feature)
618
5.50k
      .Case("arm", true)
619
5.50k
      .Case("aarch32", true)
620
5.50k
      .Case("softfloat", SoftFloat)
621
5.50k
      .Case("thumb", isThumb())
622
5.50k
      .Case("neon", (FPU & NeonFPU) && 
!SoftFloat1.77k
)
623
5.50k
      .Case("vfp", FPU && 
!SoftFloat4.74k
)
624
5.50k
      .Case("hwdiv", HWDiv & HWDivThumb)
625
5.50k
      .Case("hwdiv-arm", HWDiv & HWDivARM)
626
5.50k
      .Case("mve", hasMVE())
627
5.50k
      .Default(false);
628
5.50k
}
629
630
1.78k
bool ARMTargetInfo::hasBFloat16Type() const {
631
1.78k
  return HasBFloat16 && 
!SoftFloat202
;
632
1.78k
}
633
634
26
bool ARMTargetInfo::isValidCPUName(StringRef Name) const {
635
26
  return Name == "generic" ||
636
26
         llvm::ARM::parseCPUArch(Name) != llvm::ARM::ArchKind::INVALID;
637
26
}
638
639
2
void ARMTargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
640
2
  llvm::ARM::fillValidCPUArchList(Values);
641
2
}
642
643
579
bool ARMTargetInfo::setCPU(const std::string &Name) {
644
579
  if (Name != "generic")
645
388
    setArchInfo(llvm::ARM::parseCPUArch(Name));
646
647
579
  if (ArchKind == llvm::ARM::ArchKind::INVALID)
648
2
    return false;
649
577
  setAtomic();
650
577
  CPU = Name;
651
577
  return true;
652
579
}
653
654
8
bool ARMTargetInfo::setFPMath(StringRef Name) {
655
8
  if (Name == "neon") {
656
3
    FPMath = FP_Neon;
657
3
    return true;
658
5
  } else if (Name == "vfp" || 
Name == "vfp2"3
||
Name == "vfp3"2
||
659
5
             
Name == "vfp4"1
) {
660
5
    FPMath = FP_VFP;
661
5
    return true;
662
5
  }
663
0
  return false;
664
8
}
665
666
void ARMTargetInfo::getTargetDefinesARMV81A(const LangOptions &Opts,
667
75
                                            MacroBuilder &Builder) const {
668
75
  Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
669
75
}
670
671
void ARMTargetInfo::getTargetDefinesARMV82A(const LangOptions &Opts,
672
70
                                            MacroBuilder &Builder) const {
673
  // Also include the ARMv8.1-A defines
674
70
  getTargetDefinesARMV81A(Opts, Builder);
675
70
}
676
677
void ARMTargetInfo::getTargetDefinesARMV83A(const LangOptions &Opts,
678
45
                                            MacroBuilder &Builder) const {
679
  // Also include the ARMv8.2-A defines
680
45
  Builder.defineMacro("__ARM_FEATURE_COMPLEX", "1");
681
45
  getTargetDefinesARMV82A(Opts, Builder);
682
45
}
683
684
void ARMTargetInfo::getTargetDefines(const LangOptions &Opts,
685
1.31k
                                     MacroBuilder &Builder) const {
686
  // Target identification.
687
1.31k
  Builder.defineMacro("__arm");
688
1.31k
  Builder.defineMacro("__arm__");
689
  // For bare-metal none-eabi.
690
1.31k
  if (getTriple().getOS() == llvm::Triple::UnknownOS &&
691
1.31k
      
(690
getTriple().getEnvironment() == llvm::Triple::EABI690
||
692
690
       
getTriple().getEnvironment() == llvm::Triple::EABIHF220
))
693
484
    Builder.defineMacro("__ELF__");
694
695
  // Target properties.
696
1.31k
  Builder.defineMacro("__REGISTER_PREFIX__", "");
697
698
  // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU
699
  // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__.
700
1.31k
  if (getTriple().isWatchABI())
701
29
    Builder.defineMacro("__ARM_ARCH_7K__", "2");
702
703
1.31k
  if (!CPUAttr.empty())
704
1.31k
    Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__");
705
706
  // ACLE 6.4.1 ARM/Thumb instruction set architecture
707
  // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
708
1.31k
  Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion));
709
710
1.31k
  if (ArchVersion >= 8) {
711
    // ACLE 6.5.7 Crypto Extension
712
    // The __ARM_FEATURE_CRYPTO is deprecated in favor of finer grained
713
    // feature macros for AES and SHA2
714
460
    if (SHA2 && 
AES105
)
715
104
      Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
716
460
    if (SHA2)
717
105
      Builder.defineMacro("__ARM_FEATURE_SHA2", "1");
718
460
    if (AES)
719
105
      Builder.defineMacro("__ARM_FEATURE_AES", "1");
720
    // ACLE 6.5.8 CRC32 Extension
721
460
    if (CRC)
722
165
      Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
723
    // ACLE 6.5.10 Numeric Maximum and Minimum
724
460
    Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
725
    // ACLE 6.5.9 Directed Rounding
726
460
    Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
727
460
  }
728
729
  // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA.  It
730
  // is not defined for the M-profile.
731
  // NOTE that the default profile is assumed to be 'A'
732
1.31k
  if (CPUProfile.empty() || 
ArchProfile != llvm::ARM::ProfileKind::M1.06k
)
733
998
    Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
734
735
  // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original
736
  // Thumb ISA (including v6-M and v8-M Baseline).  It is set to 2 if the
737
  // core supports the Thumb-2 ISA as found in the v6T2 architecture and all
738
  // v7 and v8 architectures excluding v8-M Baseline.
739
1.31k
  if (supportsThumb2())
740
1.03k
    Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
741
277
  else if (supportsThumb())
742
271
    Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
743
744
  // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
745
  // instruction set such as ARM or Thumb.
746
1.31k
  Builder.defineMacro("__ARM_32BIT_STATE", "1");
747
748
  // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
749
750
  // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
751
1.31k
  if (!CPUProfile.empty())
752
1.06k
    Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
753
754
  // ACLE 6.4.3 Unaligned access supported in hardware
755
1.31k
  if (Unaligned)
756
963
    Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
757
758
  // ACLE 6.4.4 LDREX/STREX
759
1.31k
  if (LDREX)
760
1.10k
    Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + Twine::utohexstr(LDREX));
761
762
  // ACLE 6.4.5 CLZ
763
1.31k
  if (ArchVersion == 5 || 
(1.29k
ArchVersion == 61.29k
&&
CPUProfile != "M"60
) ||
764
1.31k
      
ArchVersion > 61.25k
)
765
1.11k
    Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
766
767
  // ACLE 6.5.1 Hardware Floating Point
768
1.31k
  if (HW_FP)
769
571
    Builder.defineMacro("__ARM_FP", "0x" + Twine::utohexstr(HW_FP));
770
771
  // ACLE predefines.
772
1.31k
  Builder.defineMacro("__ARM_ACLE", "200");
773
774
  // FP16 support (we currently only support IEEE format).
775
1.31k
  Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
776
1.31k
  Builder.defineMacro("__ARM_FP16_ARGS", "1");
777
778
  // ACLE 6.5.3 Fused multiply-accumulate (FMA)
779
1.31k
  if (ArchVersion >= 7 && 
(FPU & VFP4FPU)1.06k
)
780
241
    Builder.defineMacro("__ARM_FEATURE_FMA", "1");
781
782
  // Subtarget options.
783
784
  // FIXME: It's more complicated than this and we don't really support
785
  // interworking.
786
  // Windows on ARM does not "support" interworking
787
1.31k
  if (5 <= ArchVersion && 
ArchVersion <= 81.13k
&&
!getTriple().isOSWindows()1.12k
)
788
1.01k
    Builder.defineMacro("__THUMB_INTERWORK__");
789
790
1.31k
  if (ABI == "aapcs" || 
ABI == "aapcs-linux"430
||
ABI == "aapcs-vfp"203
) {
791
    // Embedded targets on Darwin follow AAPCS, but not EABI.
792
    // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
793
1.11k
    if (!getTriple().isOSBinFormatMachO() && 
!getTriple().isOSWindows()1.08k
)
794
966
      Builder.defineMacro("__ARM_EABI__");
795
1.11k
    Builder.defineMacro("__ARM_PCS", "1");
796
1.11k
  }
797
798
1.31k
  if ((!SoftFloat && 
!SoftFloatABI1.18k
) ||
ABI == "aapcs-vfp"436
||
ABI == "aapcs16"436
)
799
876
    Builder.defineMacro("__ARM_PCS_VFP", "1");
800
801
1.31k
  if (SoftFloat)
802
124
    Builder.defineMacro("__SOFTFP__");
803
804
  // ACLE position independent code macros.
805
1.31k
  if (Opts.ROPI)
806
2
    Builder.defineMacro("__ARM_ROPI", "1");
807
1.31k
  if (Opts.RWPI)
808
2
    Builder.defineMacro("__ARM_RWPI", "1");
809
810
1.31k
  if (ArchKind == llvm::ARM::ArchKind::XSCALE)
811
0
    Builder.defineMacro("__XSCALE__");
812
813
1.31k
  if (isThumb()) {
814
627
    Builder.defineMacro("__THUMBEL__");
815
627
    Builder.defineMacro("__thumb__");
816
627
    if (supportsThumb2())
817
562
      Builder.defineMacro("__thumb2__");
818
627
  }
819
820
  // ACLE 6.4.9 32-bit SIMD instructions
821
1.31k
  if ((CPUProfile != "M" && 
ArchVersion >= 6998
) ||
(505
CPUProfile == "M"505
&&
DSP314
))
822
844
    Builder.defineMacro("__ARM_FEATURE_SIMD32", "1");
823
824
  // ACLE 6.4.10 Hardware Integer Divide
825
1.31k
  if (((HWDiv & HWDivThumb) && 
isThumb()365
) ||
826
1.31k
      
(1.12k
(HWDiv & HWDivARM)1.12k
&&
!isThumb()171
)) {
827
354
    Builder.defineMacro("__ARM_FEATURE_IDIV", "1");
828
354
    Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
829
354
  }
830
831
  // Note, this is always on in gcc, even though it doesn't make sense.
832
1.31k
  Builder.defineMacro("__APCS_32__");
833
834
  // __VFP_FP__ means that the floating-point format is VFP, not that a hardware
835
  // FPU is present. Moreover, the VFP format is the only one supported by
836
  // clang. For these reasons, this macro is always defined.
837
1.31k
  Builder.defineMacro("__VFP_FP__");
838
839
1.31k
  if (FPUModeIsVFP((FPUMode)FPU)) {
840
571
    if (FPU & VFP2FPU)
841
384
      Builder.defineMacro("__ARM_VFPV2__");
842
571
    if (FPU & VFP3FPU)
843
372
      Builder.defineMacro("__ARM_VFPV3__");
844
571
    if (FPU & VFP4FPU)
845
251
      Builder.defineMacro("__ARM_VFPV4__");
846
571
    if (FPU & FPARMV8)
847
308
      Builder.defineMacro("__ARM_FPV5__");
848
571
  }
849
850
  // This only gets set when Neon instructions are actually available, unlike
851
  // the VFP define, hence the soft float and arch check. This is subtly
852
  // different from gcc, we follow the intent which was that it should be set
853
  // when Neon instructions are actually available.
854
1.31k
  if ((FPU & NeonFPU) && 
!SoftFloat321
&&
ArchVersion >= 7320
) {
855
311
    Builder.defineMacro("__ARM_NEON", "1");
856
311
    Builder.defineMacro("__ARM_NEON__");
857
    // current AArch32 NEON implementations do not support double-precision
858
    // floating-point even when it is present in VFP.
859
311
    Builder.defineMacro("__ARM_NEON_FP",
860
311
                        "0x" + Twine::utohexstr(HW_FP & ~HW_FP_DP));
861
311
  }
862
863
1.31k
  if (hasMVE()) {
864
164
    Builder.defineMacro("__ARM_FEATURE_MVE", hasMVEFloat() ? 
"3"140
:
"1"24
);
865
164
  }
866
867
1.31k
  if (hasCDE()) {
868
14
    Builder.defineMacro("__ARM_FEATURE_CDE", "1");
869
14
    Builder.defineMacro("__ARM_FEATURE_CDE_COPROC",
870
14
                        "0x" + Twine::utohexstr(getARMCDECoprocMask()));
871
14
  }
872
873
1.31k
  Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
874
1.31k
                      Twine(Opts.WCharSize ? 
Opts.WCharSize5
:
41.30k
));
875
876
1.31k
  Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", Opts.ShortEnums ? 
"1"2
:
"4"1.31k
);
877
878
  // CMSE
879
1.31k
  if (ArchVersion == 8 && 
ArchProfile == llvm::ARM::ProfileKind::M452
)
880
252
    Builder.defineMacro("__ARM_FEATURE_CMSE", Opts.Cmse ? 
"3"30
:
"1"222
);
881
882
1.31k
  if (ArchVersion >= 6 && 
CPUAttr != "6M"1.12k
&&
CPUAttr != "8M_BASE"1.10k
) {
883
1.07k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
884
1.07k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
885
1.07k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
886
1.07k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
887
1.07k
  }
888
889
  // ACLE 6.4.7 DSP instructions
890
1.31k
  if (DSP) {
891
445
    Builder.defineMacro("__ARM_FEATURE_DSP", "1");
892
445
  }
893
894
  // ACLE 6.4.8 Saturation instructions
895
1.31k
  bool SAT = false;
896
1.31k
  if ((ArchVersion == 6 && 
CPUProfile != "M"60
) ||
ArchVersion > 61.27k
) {
897
1.10k
    Builder.defineMacro("__ARM_FEATURE_SAT", "1");
898
1.10k
    SAT = true;
899
1.10k
  }
900
901
  // ACLE 6.4.6 Q (saturation) flag
902
1.31k
  if (DSP || 
SAT867
)
903
1.10k
    Builder.defineMacro("__ARM_FEATURE_QBIT", "1");
904
905
1.31k
  if (Opts.UnsafeFPMath)
906
2
    Builder.defineMacro("__ARM_FP_FAST", "1");
907
908
  // Armv8.2-A FP16 vector intrinsic
909
1.31k
  if ((FPU & NeonFPU) && 
HasLegalHalfType321
)
910
19
    Builder.defineMacro("__ARM_FEATURE_FP16_VECTOR_ARITHMETIC", "1");
911
912
  // Armv8.2-A FP16 scalar intrinsics
913
1.31k
  if (HasLegalHalfType)
914
189
    Builder.defineMacro("__ARM_FEATURE_FP16_SCALAR_ARITHMETIC", "1");
915
916
  // Armv8.2-A dot product intrinsics
917
1.31k
  if (DotProd)
918
39
    Builder.defineMacro("__ARM_FEATURE_DOTPROD", "1");
919
920
1.31k
  if (HasMatMul)
921
14
    Builder.defineMacro("__ARM_FEATURE_MATMUL_INT8", "1");
922
923
1.31k
  if (HasPAC)
924
1
    Builder.defineMacro("__ARM_FEATURE_PAUTH", "1");
925
926
1.31k
  if (HasBTI)
927
1
    Builder.defineMacro("__ARM_FEATURE_BTI", "1");
928
929
1.31k
  if (HasBFloat16) {
930
28
    Builder.defineMacro("__ARM_FEATURE_BF16", "1");
931
28
    Builder.defineMacro("__ARM_FEATURE_BF16_VECTOR_ARITHMETIC", "1");
932
28
    Builder.defineMacro("__ARM_BF16_FORMAT_ALTERNATIVE", "1");
933
28
  }
934
935
1.31k
  if (Opts.BranchTargetEnforcement)
936
9
    Builder.defineMacro("__ARM_FEATURE_BTI_DEFAULT", "1");
937
938
1.31k
  if (Opts.hasSignReturnAddress()) {
939
15
    unsigned Value = 1;
940
15
    if (Opts.isSignReturnAddressScopeAll())
941
7
      Value |= 1 << 2;
942
15
    Builder.defineMacro("__ARM_FEATURE_PAC_DEFAULT", Twine(Value));
943
15
  }
944
945
1.31k
  switch (ArchKind) {
946
1.23k
  default:
947
1.23k
    break;
948
1.23k
  case llvm::ARM::ArchKind::ARMV8_1A:
949
5
    getTargetDefinesARMV81A(Opts, Builder);
950
5
    break;
951
25
  case llvm::ARM::ArchKind::ARMV8_2A:
952
25
    getTargetDefinesARMV82A(Opts, Builder);
953
25
    break;
954
3
  case llvm::ARM::ArchKind::ARMV8_3A:
955
20
  case llvm::ARM::ArchKind::ARMV8_4A:
956
22
  case llvm::ARM::ArchKind::ARMV8_5A:
957
33
  case llvm::ARM::ArchKind::ARMV8_6A:
958
35
  case llvm::ARM::ArchKind::ARMV8_7A:
959
37
  case llvm::ARM::ArchKind::ARMV8_8A:
960
39
  case llvm::ARM::ArchKind::ARMV9A:
961
41
  case llvm::ARM::ArchKind::ARMV9_1A:
962
43
  case llvm::ARM::ArchKind::ARMV9_2A:
963
45
  case llvm::ARM::ArchKind::ARMV9_3A:
964
45
    getTargetDefinesARMV83A(Opts, Builder);
965
45
    break;
966
1.31k
  }
967
1.31k
}
968
969
const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
970
#define BUILTIN(ID, TYPE, ATTRS)                                               \
971
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
972
#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER)                                    \
973
  {#ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr},
974
#include "clang/Basic/BuiltinsNEON.def"
975
976
#define BUILTIN(ID, TYPE, ATTRS)                                               \
977
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
978
#define LANGBUILTIN(ID, TYPE, ATTRS, LANG)                                     \
979
  {#ID, TYPE, ATTRS, nullptr, LANG, nullptr},
980
#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER)                                    \
981
  {#ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr},
982
#define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE)         \
983
  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
984
#include "clang/Basic/BuiltinsARM.def"
985
};
986
987
1.31k
ArrayRef<Builtin::Info> ARMTargetInfo::getTargetBuiltins() const {
988
1.31k
  return llvm::makeArrayRef(BuiltinInfo, clang::ARM::LastTSBuiltin -
989
1.31k
                                             Builtin::FirstTSBuiltin);
990
1.31k
}
991
992
17
bool ARMTargetInfo::isCLZForZeroUndef() const { return false; }
993
743
TargetInfo::BuiltinVaListKind ARMTargetInfo::getBuiltinVaListKind() const {
994
743
  return IsAAPCS
995
743
             ? 
AAPCSABIBuiltinVaList567
996
743
             : 
(176
getTriple().isWatchABI()176
?
TargetInfo::CharPtrBuiltinVaList24
997
176
                                         : 
TargetInfo::VoidPtrBuiltinVaList152
);
998
743
}
999
1000
const char *const ARMTargetInfo::GCCRegNames[] = {
1001
    // Integer registers
1002
    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11",
1003
    "r12", "sp", "lr", "pc",
1004
1005
    // Float registers
1006
    "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11",
1007
    "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", "s22",
1008
    "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
1009
1010
    // Double registers
1011
    "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", "d11",
1012
    "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", "d22",
1013
    "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
1014
1015
    // Quad registers
1016
    "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", "q8", "q9", "q10", "q11",
1017
    "q12", "q13", "q14", "q15"};
1018
1019
352
ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const {
1020
352
  return llvm::makeArrayRef(GCCRegNames);
1021
352
}
1022
1023
const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
1024
    {{"a1"}, "r0"},  {{"a2"}, "r1"},        {{"a3"}, "r2"},  {{"a4"}, "r3"},
1025
    {{"v1"}, "r4"},  {{"v2"}, "r5"},        {{"v3"}, "r6"},  {{"v4"}, "r7"},
1026
    {{"v5"}, "r8"},  {{"v6", "rfp"}, "r9"}, {{"sl"}, "r10"}, {{"fp"}, "r11"},
1027
    {{"ip"}, "r12"}, {{"r13"}, "sp"},       {{"r14"}, "lr"}, {{"r15"}, "pc"},
1028
    // The S, D and Q registers overlap, but aren't really aliases; we
1029
    // don't want to substitute one of these for a different-sized one.
1030
};
1031
1032
179
ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const {
1033
179
  return llvm::makeArrayRef(GCCRegAliases);
1034
179
}
1035
1036
bool ARMTargetInfo::validateAsmConstraint(
1037
187
    const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1038
187
  switch (*Name) {
1039
1
  default:
1040
1
    break;
1041
9
  case 'l': // r0-r7 if thumb, r0-r15 if ARM
1042
9
    Info.setAllowsRegister();
1043
9
    return true;
1044
6
  case 'h': // r8-r15, thumb only
1045
6
    if (isThumb()) {
1046
4
      Info.setAllowsRegister();
1047
4
      return true;
1048
4
    }
1049
2
    break;
1050
4
  case 's': // An integer constant, but allowing only relocatable values.
1051
4
    return true;
1052
17
  case 't': // s0-s31, d0-d31, or q0-q15
1053
38
  case 'w': // s0-s15, d0-d7, or q0-q3
1054
47
  case 'x': // s0-s31, d0-d15, or q0-q7
1055
47
    if (FPRegsDisabled)
1056
3
      return false;
1057
44
    Info.setAllowsRegister();
1058
44
    return true;
1059
16
  case 'j': // An immediate integer between 0 and 65535 (valid for MOVW)
1060
    // only available in ARMv6T2 and above
1061
16
    if (CPUAttr.equals("6T2") || ArchVersion >= 7) {
1062
8
      Info.setRequiresImmediate(0, 65535);
1063
8
      return true;
1064
8
    }
1065
8
    break;
1066
16
  case 'I':
1067
16
    if (isThumb()) {
1068
8
      if (!supportsThumb2())
1069
4
        Info.setRequiresImmediate(0, 255);
1070
4
      else
1071
        // FIXME: should check if immediate value would be valid for a Thumb2
1072
        // data-processing instruction
1073
4
        Info.setRequiresImmediate();
1074
8
    } else
1075
      // FIXME: should check if immediate value would be valid for an ARM
1076
      // data-processing instruction
1077
8
      Info.setRequiresImmediate();
1078
16
    return true;
1079
32
  case 'J':
1080
32
    if (isThumb() && 
!supportsThumb2()16
)
1081
8
      Info.setRequiresImmediate(-255, -1);
1082
24
    else
1083
24
      Info.setRequiresImmediate(-4095, 4095);
1084
32
    return true;
1085
4
  case 'K':
1086
4
    if (isThumb()) {
1087
2
      if (!supportsThumb2())
1088
        // FIXME: should check if immediate value can be obtained from shifting
1089
        // a value between 0 and 255 left by any amount
1090
1
        Info.setRequiresImmediate();
1091
1
      else
1092
        // FIXME: should check if immediate value would be valid for a Thumb2
1093
        // data-processing instruction when inverted
1094
1
        Info.setRequiresImmediate();
1095
2
    } else
1096
      // FIXME: should check if immediate value would be valid for an ARM
1097
      // data-processing instruction when inverted
1098
2
      Info.setRequiresImmediate();
1099
4
    return true;
1100
16
  case 'L':
1101
16
    if (isThumb()) {
1102
8
      if (!supportsThumb2())
1103
4
        Info.setRequiresImmediate(-7, 7);
1104
4
      else
1105
        // FIXME: should check if immediate value would be valid for a Thumb2
1106
        // data-processing instruction when negated
1107
4
        Info.setRequiresImmediate();
1108
8
    } else
1109
      // FIXME: should check if immediate value  would be valid for an ARM
1110
      // data-processing instruction when negated
1111
8
      Info.setRequiresImmediate();
1112
16
    return true;
1113
4
  case 'M':
1114
4
    if (isThumb() && 
!supportsThumb2()2
)
1115
      // FIXME: should check if immediate value is a multiple of 4 between 0 and
1116
      // 1020
1117
1
      Info.setRequiresImmediate();
1118
3
    else
1119
      // FIXME: should check if immediate value is a power of two or a integer
1120
      // between 0 and 32
1121
3
      Info.setRequiresImmediate();
1122
4
    return true;
1123
16
  case 'N':
1124
    // Thumb1 only
1125
16
    if (isThumb() && 
!supportsThumb2()8
) {
1126
4
      Info.setRequiresImmediate(0, 31);
1127
4
      return true;
1128
4
    }
1129
12
    break;
1130
12
  case 'O':
1131
    // Thumb1 only
1132
4
    if (isThumb() && 
!supportsThumb2()2
) {
1133
      // FIXME: should check if immediate value is a multiple of 4 between -508
1134
      // and 508
1135
1
      Info.setRequiresImmediate();
1136
1
      return true;
1137
1
    }
1138
3
    break;
1139
4
  case 'Q': // A memory address that is a single base register.
1140
4
    Info.setAllowsMemory();
1141
4
    return true;
1142
6
  case 'T':
1143
6
    switch (Name[1]) {
1144
0
    default:
1145
0
      break;
1146
4
    case 'e': // Even general-purpose register
1147
6
    case 'o': // Odd general-purpose register
1148
6
      Info.setAllowsRegister();
1149
6
      Name++;
1150
6
      return true;
1151
6
    }
1152
0
    break;
1153
2
  case 'U': // a memory reference...
1154
2
    switch (Name[1]) {
1155
0
    case 'q': // ...ARMV4 ldrsb
1156
2
    case 'v': // ...VFP load/store (reg+constant offset)
1157
2
    case 'y': // ...iWMMXt load/store
1158
2
    case 't': // address valid for load/store opaque types wider
1159
              // than 128-bits
1160
2
    case 'n': // valid address for Neon doubleword vector load/store
1161
2
    case 'm': // valid address for Neon element and structure load/store
1162
2
    case 's': // valid address for non-offset loads/stores of quad-word
1163
              // values in four ARM registers
1164
2
      Info.setAllowsMemory();
1165
2
      Name++;
1166
2
      return true;
1167
2
    }
1168
0
    break;
1169
187
  }
1170
26
  return false;
1171
187
}
1172
1173
306
std::string ARMTargetInfo::convertConstraint(const char *&Constraint) const {
1174
306
  std::string R;
1175
306
  switch (*Constraint) {
1176
1
  case 'U': // Two-character constraint; add "^" hint for later parsing.
1177
4
  case 'T':
1178
4
    R = std::string("^") + std::string(Constraint, 2);
1179
4
    Constraint++;
1180
4
    break;
1181
5
  case 'p': // 'p' should be translated to 'r' by default.
1182
5
    R = std::string("r");
1183
5
    break;
1184
297
  default:
1185
297
    return std::string(1, *Constraint);
1186
306
  }
1187
9
  return R;
1188
306
}
1189
1190
bool ARMTargetInfo::validateConstraintModifier(
1191
    StringRef Constraint, char Modifier, unsigned Size,
1192
396
    std::string &SuggestedModifier) const {
1193
396
  bool isOutput = (Constraint[0] == '=');
1194
396
  bool isInOut = (Constraint[0] == '+');
1195
1196
  // Strip off constraint modifiers.
1197
601
  while (Constraint[0] == '=' || 
Constraint[0] == '+'403
||
Constraint[0] == '&'398
)
1198
205
    Constraint = Constraint.substr(1);
1199
1200
396
  switch (Constraint[0]) {
1201
161
  default:
1202
161
    break;
1203
235
  case 'r': {
1204
235
    switch (Modifier) {
1205
227
    default:
1206
227
      return (isInOut || 
isOutput225
||
Size <= 6466
);
1207
8
    case 'q':
1208
      // A register of size 32 cannot fit a vector type.
1209
8
      return false;
1210
235
    }
1211
235
  }
1212
396
  }
1213
1214
161
  return true;
1215
396
}
1216
118
const char *ARMTargetInfo::getClobbers() const {
1217
  // FIXME: Is this really right?
1218
118
  return "";
1219
118
}
1220
1221
TargetInfo::CallingConvCheckResult
1222
700
ARMTargetInfo::checkCallingConvention(CallingConv CC) const {
1223
700
  switch (CC) {
1224
14
  case CC_AAPCS:
1225
25
  case CC_AAPCS_VFP:
1226
485
  case CC_Swift:
1227
700
  case CC_SwiftAsync:
1228
700
  case CC_OpenCLKernel:
1229
700
    return CCCR_OK;
1230
0
  default:
1231
0
    return CCCR_Warning;
1232
700
  }
1233
700
}
1234
1235
4
int ARMTargetInfo::getEHDataRegisterNumber(unsigned RegNo) const {
1236
4
  if (RegNo == 0)
1237
2
    return 0;
1238
2
  if (RegNo == 1)
1239
2
    return 1;
1240
0
  return -1;
1241
2
}
1242
1243
0
bool ARMTargetInfo::hasSjLjLowering() const { return true; }
1244
1245
ARMleTargetInfo::ARMleTargetInfo(const llvm::Triple &Triple,
1246
                                 const TargetOptions &Opts)
1247
1.28k
    : ARMTargetInfo(Triple, Opts) {}
clang::targets::ARMleTargetInfo::ARMleTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1247
637
    : ARMTargetInfo(Triple, Opts) {}
clang::targets::ARMleTargetInfo::ARMleTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1247
651
    : ARMTargetInfo(Triple, Opts) {}
1248
1249
void ARMleTargetInfo::getTargetDefines(const LangOptions &Opts,
1250
1.27k
                                       MacroBuilder &Builder) const {
1251
1.27k
  Builder.defineMacro("__ARMEL__");
1252
1.27k
  ARMTargetInfo::getTargetDefines(Opts, Builder);
1253
1.27k
}
1254
1255
ARMbeTargetInfo::ARMbeTargetInfo(const llvm::Triple &Triple,
1256
                                 const TargetOptions &Opts)
1257
40
    : ARMTargetInfo(Triple, Opts) {}
clang::targets::ARMbeTargetInfo::ARMbeTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1257
12
    : ARMTargetInfo(Triple, Opts) {}
clang::targets::ARMbeTargetInfo::ARMbeTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1257
28
    : ARMTargetInfo(Triple, Opts) {}
1258
1259
void ARMbeTargetInfo::getTargetDefines(const LangOptions &Opts,
1260
40
                                       MacroBuilder &Builder) const {
1261
40
  Builder.defineMacro("__ARMEB__");
1262
40
  Builder.defineMacro("__ARM_BIG_ENDIAN");
1263
40
  ARMTargetInfo::getTargetDefines(Opts, Builder);
1264
40
}
1265
1266
WindowsARMTargetInfo::WindowsARMTargetInfo(const llvm::Triple &Triple,
1267
                                           const TargetOptions &Opts)
1268
118
    : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) {
1269
118
}
clang::targets::WindowsARMTargetInfo::WindowsARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1268
118
    : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) {
1269
118
}
Unexecuted instantiation: clang::targets::WindowsARMTargetInfo::WindowsARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
1270
1271
void WindowsARMTargetInfo::getVisualStudioDefines(const LangOptions &Opts,
1272
105
                                                  MacroBuilder &Builder) const {
1273
  // FIXME: this is invalid for WindowsCE
1274
105
  Builder.defineMacro("_M_ARM_NT", "1");
1275
105
  Builder.defineMacro("_M_ARMT", "_M_ARM");
1276
105
  Builder.defineMacro("_M_THUMB", "_M_ARM");
1277
1278
105
  assert((Triple.getArch() == llvm::Triple::arm ||
1279
105
          Triple.getArch() == llvm::Triple::thumb) &&
1280
105
         "invalid architecture for Windows ARM target info");
1281
105
  unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 
48
:
697
;
1282
105
  Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
1283
1284
  // TODO map the complete set of values
1285
  // 31: VFPv3 40: VFPv4
1286
105
  Builder.defineMacro("_M_ARM_FP", "31");
1287
105
}
1288
1289
TargetInfo::BuiltinVaListKind
1290
108
WindowsARMTargetInfo::getBuiltinVaListKind() const {
1291
108
  return TargetInfo::CharPtrBuiltinVaList;
1292
108
}
1293
1294
TargetInfo::CallingConvCheckResult
1295
33
WindowsARMTargetInfo::checkCallingConvention(CallingConv CC) const {
1296
33
  switch (CC) {
1297
1
  case CC_X86StdCall:
1298
1
  case CC_X86ThisCall:
1299
1
  case CC_X86FastCall:
1300
1
  case CC_X86VectorCall:
1301
1
    return CCCR_Ignore;
1302
21
  case CC_C:
1303
21
  case CC_OpenCLKernel:
1304
26
  case CC_PreserveMost:
1305
31
  case CC_PreserveAll:
1306
32
  case CC_Swift:
1307
32
  case CC_SwiftAsync:
1308
32
    return CCCR_OK;
1309
0
  default:
1310
0
    return CCCR_Warning;
1311
33
  }
1312
33
}
1313
1314
// Windows ARM + Itanium C++ ABI Target
1315
ItaniumWindowsARMleTargetInfo::ItaniumWindowsARMleTargetInfo(
1316
    const llvm::Triple &Triple, const TargetOptions &Opts)
1317
10
    : WindowsARMTargetInfo(Triple, Opts) {
1318
10
  TheCXXABI.set(TargetCXXABI::GenericARM);
1319
10
}
Unexecuted instantiation: clang::targets::ItaniumWindowsARMleTargetInfo::ItaniumWindowsARMleTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::ItaniumWindowsARMleTargetInfo::ItaniumWindowsARMleTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1317
10
    : WindowsARMTargetInfo(Triple, Opts) {
1318
10
  TheCXXABI.set(TargetCXXABI::GenericARM);
1319
10
}
1320
1321
void ItaniumWindowsARMleTargetInfo::getTargetDefines(
1322
10
    const LangOptions &Opts, MacroBuilder &Builder) const {
1323
10
  WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
1324
1325
10
  if (Opts.MSVCCompat)
1326
1
    WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
1327
10
}
1328
1329
// Windows ARM, MS (C++) ABI
1330
MicrosoftARMleTargetInfo::MicrosoftARMleTargetInfo(const llvm::Triple &Triple,
1331
                                                   const TargetOptions &Opts)
1332
104
    : WindowsARMTargetInfo(Triple, Opts) {
1333
104
  TheCXXABI.set(TargetCXXABI::Microsoft);
1334
104
}
Unexecuted instantiation: clang::targets::MicrosoftARMleTargetInfo::MicrosoftARMleTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::MicrosoftARMleTargetInfo::MicrosoftARMleTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1332
104
    : WindowsARMTargetInfo(Triple, Opts) {
1333
104
  TheCXXABI.set(TargetCXXABI::Microsoft);
1334
104
}
1335
1336
void MicrosoftARMleTargetInfo::getTargetDefines(const LangOptions &Opts,
1337
104
                                                MacroBuilder &Builder) const {
1338
104
  WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
1339
104
  WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
1340
104
}
1341
1342
MinGWARMTargetInfo::MinGWARMTargetInfo(const llvm::Triple &Triple,
1343
                                       const TargetOptions &Opts)
1344
4
    : WindowsARMTargetInfo(Triple, Opts) {
1345
4
  TheCXXABI.set(TargetCXXABI::GenericARM);
1346
4
}
Unexecuted instantiation: clang::targets::MinGWARMTargetInfo::MinGWARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::MinGWARMTargetInfo::MinGWARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1344
4
    : WindowsARMTargetInfo(Triple, Opts) {
1345
4
  TheCXXABI.set(TargetCXXABI::GenericARM);
1346
4
}
1347
1348
void MinGWARMTargetInfo::getTargetDefines(const LangOptions &Opts,
1349
4
                                          MacroBuilder &Builder) const {
1350
4
  WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
1351
4
  Builder.defineMacro("_ARM_");
1352
4
}
1353
1354
CygwinARMTargetInfo::CygwinARMTargetInfo(const llvm::Triple &Triple,
1355
                                         const TargetOptions &Opts)
1356
1
    : ARMleTargetInfo(Triple, Opts) {
1357
1
  this->WCharType = TargetInfo::UnsignedShort;
1358
1
  TLSSupported = false;
1359
1
  DoubleAlign = LongLongAlign = 64;
1360
1
  resetDataLayout("e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64");
1361
1
}
Unexecuted instantiation: clang::targets::CygwinARMTargetInfo::CygwinARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::CygwinARMTargetInfo::CygwinARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1356
1
    : ARMleTargetInfo(Triple, Opts) {
1357
1
  this->WCharType = TargetInfo::UnsignedShort;
1358
1
  TLSSupported = false;
1359
1
  DoubleAlign = LongLongAlign = 64;
1360
1
  resetDataLayout("e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64");
1361
1
}
1362
1363
void CygwinARMTargetInfo::getTargetDefines(const LangOptions &Opts,
1364
1
                                           MacroBuilder &Builder) const {
1365
1
  ARMleTargetInfo::getTargetDefines(Opts, Builder);
1366
1
  Builder.defineMacro("_ARM_");
1367
1
  Builder.defineMacro("__CYGWIN__");
1368
1
  Builder.defineMacro("__CYGWIN32__");
1369
1
  DefineStd(Builder, "unix", Opts);
1370
1
  if (Opts.CPlusPlus)
1371
0
    Builder.defineMacro("_GNU_SOURCE");
1372
1
}
1373
1374
DarwinARMTargetInfo::DarwinARMTargetInfo(const llvm::Triple &Triple,
1375
                                         const TargetOptions &Opts)
1376
214
    : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) {
1377
214
  HasAlignMac68kSupport = true;
1378
  // iOS always has 64-bit atomic instructions.
1379
  // FIXME: This should be based off of the target features in
1380
  // ARMleTargetInfo.
1381
214
  MaxAtomicInlineWidth = 64;
1382
1383
214
  if (Triple.isWatchABI()) {
1384
    // Darwin on iOS uses a variant of the ARM C++ ABI.
1385
29
    TheCXXABI.set(TargetCXXABI::WatchOS);
1386
1387
    // BOOL should be a real boolean on the new ABI
1388
29
    UseSignedCharForObjCBool = false;
1389
29
  } else
1390
185
    TheCXXABI.set(TargetCXXABI::iOS);
1391
214
}
Unexecuted instantiation: clang::targets::DarwinARMTargetInfo::DarwinARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
clang::targets::DarwinARMTargetInfo::DarwinARMTargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1376
214
    : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) {
1377
214
  HasAlignMac68kSupport = true;
1378
  // iOS always has 64-bit atomic instructions.
1379
  // FIXME: This should be based off of the target features in
1380
  // ARMleTargetInfo.
1381
214
  MaxAtomicInlineWidth = 64;
1382
1383
214
  if (Triple.isWatchABI()) {
1384
    // Darwin on iOS uses a variant of the ARM C++ ABI.
1385
29
    TheCXXABI.set(TargetCXXABI::WatchOS);
1386
1387
    // BOOL should be a real boolean on the new ABI
1388
29
    UseSignedCharForObjCBool = false;
1389
29
  } else
1390
185
    TheCXXABI.set(TargetCXXABI::iOS);
1391
214
}
1392
1393
void DarwinARMTargetInfo::getOSDefines(const LangOptions &Opts,
1394
                                       const llvm::Triple &Triple,
1395
203
                                       MacroBuilder &Builder) const {
1396
203
  getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
1397
203
}
1398
1399
RenderScript32TargetInfo::RenderScript32TargetInfo(const llvm::Triple &Triple,
1400
                                                   const TargetOptions &Opts)
1401
    : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(),
1402
                                   Triple.getOSName(),
1403
                                   Triple.getEnvironmentName()),
1404
1
                      Opts) {
1405
1
  IsRenderScriptTarget = true;
1406
1
  LongWidth = LongAlign = 64;
1407
1
}
clang::targets::RenderScript32TargetInfo::RenderScript32TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
Line
Count
Source
1404
1
                      Opts) {
1405
1
  IsRenderScriptTarget = true;
1406
1
  LongWidth = LongAlign = 64;
1407
1
}
Unexecuted instantiation: clang::targets::RenderScript32TargetInfo::RenderScript32TargetInfo(llvm::Triple const&, clang::TargetOptions const&)
1408
1409
void RenderScript32TargetInfo::getTargetDefines(const LangOptions &Opts,
1410
1
                                                MacroBuilder &Builder) const {
1411
1
  Builder.defineMacro("__RENDERSCRIPT__");
1412
1
  ARMleTargetInfo::getTargetDefines(Opts, Builder);
1413
1
}