Coverage Report

Created: 2022-07-16 07:03

/Users/buildslave/jenkins/workspace/coverage/llvm-project/clang/lib/Basic/Targets/NVPTX.cpp
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Source (jump to first uncovered line)
1
//===--- NVPTX.cpp - Implement NVPTX target feature support ---------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
8
//
9
// This file implements NVPTX TargetInfo objects.
10
//
11
//===----------------------------------------------------------------------===//
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13
#include "NVPTX.h"
14
#include "Targets.h"
15
#include "clang/Basic/Builtins.h"
16
#include "clang/Basic/MacroBuilder.h"
17
#include "clang/Basic/TargetBuiltins.h"
18
#include "llvm/ADT/StringSwitch.h"
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20
using namespace clang;
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using namespace clang::targets;
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23
const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
24
#define BUILTIN(ID, TYPE, ATTRS)                                               \
25
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
26
#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER)                                    \
27
  {#ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr},
28
#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)                               \
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  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
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#include "clang/Basic/BuiltinsNVPTX.def"
31
};
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const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"};
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NVPTXTargetInfo::NVPTXTargetInfo(const llvm::Triple &Triple,
36
                                 const TargetOptions &Opts,
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                                 unsigned TargetPointerWidth)
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315
    : TargetInfo(Triple) {
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315
  assert((TargetPointerWidth == 32 || TargetPointerWidth == 64) &&
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315
         "NVPTX only supports 32- and 64-bit modes.");
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0
  PTXVersion = 32;
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315
  for (const StringRef Feature : Opts.FeaturesAsWritten) {
44
22
    if (!Feature.startswith("+ptx"))
45
0
      continue;
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22
    PTXVersion = llvm::StringSwitch<unsigned>(Feature)
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22
                     .Case("+ptx75", 75)
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22
                     .Case("+ptx74", 74)
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22
                     .Case("+ptx73", 73)
50
22
                     .Case("+ptx72", 72)
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22
                     .Case("+ptx71", 71)
52
22
                     .Case("+ptx70", 70)
53
22
                     .Case("+ptx65", 65)
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22
                     .Case("+ptx64", 64)
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22
                     .Case("+ptx63", 63)
56
22
                     .Case("+ptx61", 61)
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22
                     .Case("+ptx60", 60)
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22
                     .Case("+ptx50", 50)
59
22
                     .Case("+ptx43", 43)
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22
                     .Case("+ptx42", 42)
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22
                     .Case("+ptx41", 41)
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22
                     .Case("+ptx40", 40)
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22
                     .Case("+ptx32", 32)
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22
                     .Default(32);
65
22
  }
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67
315
  TLSSupported = false;
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315
  VLASupported = false;
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315
  AddrSpaceMap = &NVPTXAddrSpaceMap;
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315
  UseAddrSpaceMapMangling = true;
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  // Define available target features
73
  // These must be defined in sorted order!
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315
  NoAsmVariants = true;
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315
  GPU = CudaArch::SM_20;
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  if (TargetPointerWidth == 32)
78
142
    resetDataLayout("e-p:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64");
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  else if (Opts.NVPTXUseShortPointers)
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0
    resetDataLayout(
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0
        "e-p3:32:32-p4:32:32-p5:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64");
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  else
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173
    resetDataLayout("e-i64:64-i128:128-v16:16-v32:32-n16:32:64");
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  // If possible, get a TargetInfo for our host triple, so we can match its
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  // types.
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  llvm::Triple HostTriple(Opts.HostTriple);
88
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  if (!HostTriple.isNVPTX())
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    HostTarget.reset(AllocateTarget(llvm::Triple(Opts.HostTriple), Opts));
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  // If no host target, make some guesses about the data layout and return.
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315
  if (!HostTarget) {
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    LongWidth = LongAlign = TargetPointerWidth;
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    PointerWidth = PointerAlign = TargetPointerWidth;
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235
    switch (TargetPointerWidth) {
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    case 32:
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      SizeType = TargetInfo::UnsignedInt;
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      PtrDiffType = TargetInfo::SignedInt;
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      IntPtrType = TargetInfo::SignedInt;
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      break;
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    case 64:
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      SizeType = TargetInfo::UnsignedLong;
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      PtrDiffType = TargetInfo::SignedLong;
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      IntPtrType = TargetInfo::SignedLong;
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111
      break;
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0
    default:
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0
      llvm_unreachable("TargetPointerWidth must be 32 or 64");
108
235
    }
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235
    return;
110
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  }
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  // Copy properties from host target.
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80
  PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0);
114
80
  PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0);
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  BoolWidth = HostTarget->getBoolWidth();
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  BoolAlign = HostTarget->getBoolAlign();
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  IntWidth = HostTarget->getIntWidth();
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  IntAlign = HostTarget->getIntAlign();
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  HalfWidth = HostTarget->getHalfWidth();
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  HalfAlign = HostTarget->getHalfAlign();
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  FloatWidth = HostTarget->getFloatWidth();
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  FloatAlign = HostTarget->getFloatAlign();
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  DoubleWidth = HostTarget->getDoubleWidth();
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  DoubleAlign = HostTarget->getDoubleAlign();
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  LongWidth = HostTarget->getLongWidth();
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  LongAlign = HostTarget->getLongAlign();
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  LongLongWidth = HostTarget->getLongLongWidth();
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  LongLongAlign = HostTarget->getLongLongAlign();
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  MinGlobalAlign = HostTarget->getMinGlobalAlign(/* TypeSize = */ 0);
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  NewAlign = HostTarget->getNewAlign();
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80
  DefaultAlignForAttributeAligned =
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      HostTarget->getDefaultAlignForAttributeAligned();
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  SizeType = HostTarget->getSizeType();
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  IntMaxType = HostTarget->getIntMaxType();
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  PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0);
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  IntPtrType = HostTarget->getIntPtrType();
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  WCharType = HostTarget->getWCharType();
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  WIntType = HostTarget->getWIntType();
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  Char16Type = HostTarget->getChar16Type();
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  Char32Type = HostTarget->getChar32Type();
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  Int64Type = HostTarget->getInt64Type();
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  SigAtomicType = HostTarget->getSigAtomicType();
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  ProcessIDType = HostTarget->getProcessIDType();
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  UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment();
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  UseZeroLengthBitfieldAlignment = HostTarget->useZeroLengthBitfieldAlignment();
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80
  UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment();
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80
  ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary();
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  // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and
151
  // we need those macros to be identical on host and device, because (among
152
  // other things) they affect which standard library classes are defined, and
153
  // we need all classes to be defined on both the host and device.
154
80
  MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth();
155
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  // Properties intentionally not copied from host:
157
  // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the
158
  //   host/device boundary.
159
  // - SuitableAlign: Not visible across the host/device boundary, and may
160
  //   correctly be different on host/device, e.g. if host has wider vector
161
  //   types than device.
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  // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same
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  //   as its double type, but that's not necessarily true on the host.
164
  //   TODO: nvcc emits a warning when using long double on device; we should
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  //   do the same.
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80
}
Unexecuted instantiation: clang::targets::NVPTXTargetInfo::NVPTXTargetInfo(llvm::Triple const&, clang::TargetOptions const&, unsigned int)
clang::targets::NVPTXTargetInfo::NVPTXTargetInfo(llvm::Triple const&, clang::TargetOptions const&, unsigned int)
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Source
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315
    : TargetInfo(Triple) {
39
315
  assert((TargetPointerWidth == 32 || TargetPointerWidth == 64) &&
40
315
         "NVPTX only supports 32- and 64-bit modes.");
41
42
0
  PTXVersion = 32;
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315
  for (const StringRef Feature : Opts.FeaturesAsWritten) {
44
22
    if (!Feature.startswith("+ptx"))
45
0
      continue;
46
22
    PTXVersion = llvm::StringSwitch<unsigned>(Feature)
47
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                     .Case("+ptx75", 75)
48
22
                     .Case("+ptx74", 74)
49
22
                     .Case("+ptx73", 73)
50
22
                     .Case("+ptx72", 72)
51
22
                     .Case("+ptx71", 71)
52
22
                     .Case("+ptx70", 70)
53
22
                     .Case("+ptx65", 65)
54
22
                     .Case("+ptx64", 64)
55
22
                     .Case("+ptx63", 63)
56
22
                     .Case("+ptx61", 61)
57
22
                     .Case("+ptx60", 60)
58
22
                     .Case("+ptx50", 50)
59
22
                     .Case("+ptx43", 43)
60
22
                     .Case("+ptx42", 42)
61
22
                     .Case("+ptx41", 41)
62
22
                     .Case("+ptx40", 40)
63
22
                     .Case("+ptx32", 32)
64
22
                     .Default(32);
65
22
  }
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315
  TLSSupported = false;
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  VLASupported = false;
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  AddrSpaceMap = &NVPTXAddrSpaceMap;
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  UseAddrSpaceMapMangling = true;
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  // Define available target features
73
  // These must be defined in sorted order!
74
315
  NoAsmVariants = true;
75
315
  GPU = CudaArch::SM_20;
76
77
315
  if (TargetPointerWidth == 32)
78
142
    resetDataLayout("e-p:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64");
79
173
  else if (Opts.NVPTXUseShortPointers)
80
0
    resetDataLayout(
81
0
        "e-p3:32:32-p4:32:32-p5:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64");
82
173
  else
83
173
    resetDataLayout("e-i64:64-i128:128-v16:16-v32:32-n16:32:64");
84
85
  // If possible, get a TargetInfo for our host triple, so we can match its
86
  // types.
87
315
  llvm::Triple HostTriple(Opts.HostTriple);
88
315
  if (!HostTriple.isNVPTX())
89
315
    HostTarget.reset(AllocateTarget(llvm::Triple(Opts.HostTriple), Opts));
90
91
  // If no host target, make some guesses about the data layout and return.
92
315
  if (!HostTarget) {
93
235
    LongWidth = LongAlign = TargetPointerWidth;
94
235
    PointerWidth = PointerAlign = TargetPointerWidth;
95
235
    switch (TargetPointerWidth) {
96
124
    case 32:
97
124
      SizeType = TargetInfo::UnsignedInt;
98
124
      PtrDiffType = TargetInfo::SignedInt;
99
124
      IntPtrType = TargetInfo::SignedInt;
100
124
      break;
101
111
    case 64:
102
111
      SizeType = TargetInfo::UnsignedLong;
103
111
      PtrDiffType = TargetInfo::SignedLong;
104
111
      IntPtrType = TargetInfo::SignedLong;
105
111
      break;
106
0
    default:
107
0
      llvm_unreachable("TargetPointerWidth must be 32 or 64");
108
235
    }
109
235
    return;
110
235
  }
111
112
  // Copy properties from host target.
113
80
  PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0);
114
80
  PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0);
115
80
  BoolWidth = HostTarget->getBoolWidth();
116
80
  BoolAlign = HostTarget->getBoolAlign();
117
80
  IntWidth = HostTarget->getIntWidth();
118
80
  IntAlign = HostTarget->getIntAlign();
119
80
  HalfWidth = HostTarget->getHalfWidth();
120
80
  HalfAlign = HostTarget->getHalfAlign();
121
80
  FloatWidth = HostTarget->getFloatWidth();
122
80
  FloatAlign = HostTarget->getFloatAlign();
123
80
  DoubleWidth = HostTarget->getDoubleWidth();
124
80
  DoubleAlign = HostTarget->getDoubleAlign();
125
80
  LongWidth = HostTarget->getLongWidth();
126
80
  LongAlign = HostTarget->getLongAlign();
127
80
  LongLongWidth = HostTarget->getLongLongWidth();
128
80
  LongLongAlign = HostTarget->getLongLongAlign();
129
80
  MinGlobalAlign = HostTarget->getMinGlobalAlign(/* TypeSize = */ 0);
130
80
  NewAlign = HostTarget->getNewAlign();
131
80
  DefaultAlignForAttributeAligned =
132
80
      HostTarget->getDefaultAlignForAttributeAligned();
133
80
  SizeType = HostTarget->getSizeType();
134
80
  IntMaxType = HostTarget->getIntMaxType();
135
80
  PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0);
136
80
  IntPtrType = HostTarget->getIntPtrType();
137
80
  WCharType = HostTarget->getWCharType();
138
80
  WIntType = HostTarget->getWIntType();
139
80
  Char16Type = HostTarget->getChar16Type();
140
80
  Char32Type = HostTarget->getChar32Type();
141
80
  Int64Type = HostTarget->getInt64Type();
142
80
  SigAtomicType = HostTarget->getSigAtomicType();
143
80
  ProcessIDType = HostTarget->getProcessIDType();
144
145
80
  UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment();
146
80
  UseZeroLengthBitfieldAlignment = HostTarget->useZeroLengthBitfieldAlignment();
147
80
  UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment();
148
80
  ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary();
149
150
  // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and
151
  // we need those macros to be identical on host and device, because (among
152
  // other things) they affect which standard library classes are defined, and
153
  // we need all classes to be defined on both the host and device.
154
80
  MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth();
155
156
  // Properties intentionally not copied from host:
157
  // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the
158
  //   host/device boundary.
159
  // - SuitableAlign: Not visible across the host/device boundary, and may
160
  //   correctly be different on host/device, e.g. if host has wider vector
161
  //   types than device.
162
  // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same
163
  //   as its double type, but that's not necessarily true on the host.
164
  //   TODO: nvcc emits a warning when using long double on device; we should
165
  //   do the same.
166
80
}
167
168
0
ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const {
169
0
  return llvm::makeArrayRef(GCCRegNames);
170
0
}
171
172
230
bool NVPTXTargetInfo::hasFeature(StringRef Feature) const {
173
230
  return llvm::StringSwitch<bool>(Feature)
174
230
      .Cases("ptx", "nvptx", true)
175
230
      .Default(false);
176
230
}
177
178
void NVPTXTargetInfo::getTargetDefines(const LangOptions &Opts,
179
314
                                       MacroBuilder &Builder) const {
180
314
  Builder.defineMacro("__PTX__");
181
314
  Builder.defineMacro("__NVPTX__");
182
314
  if (Opts.CUDAIsDevice || 
Opts.OpenMPIsDevice230
) {
183
    // Set __CUDA_ARCH__ for the GPU specified.
184
261
    std::string CUDAArchCode = [this] {
185
261
      switch (GPU) {
186
0
      case CudaArch::GFX600:
187
0
      case CudaArch::GFX601:
188
0
      case CudaArch::GFX602:
189
0
      case CudaArch::GFX700:
190
0
      case CudaArch::GFX701:
191
0
      case CudaArch::GFX702:
192
0
      case CudaArch::GFX703:
193
0
      case CudaArch::GFX704:
194
0
      case CudaArch::GFX705:
195
0
      case CudaArch::GFX801:
196
0
      case CudaArch::GFX802:
197
0
      case CudaArch::GFX803:
198
0
      case CudaArch::GFX805:
199
0
      case CudaArch::GFX810:
200
0
      case CudaArch::GFX900:
201
0
      case CudaArch::GFX902:
202
0
      case CudaArch::GFX904:
203
0
      case CudaArch::GFX906:
204
0
      case CudaArch::GFX908:
205
0
      case CudaArch::GFX909:
206
0
      case CudaArch::GFX90a:
207
0
      case CudaArch::GFX90c:
208
0
      case CudaArch::GFX940:
209
0
      case CudaArch::GFX1010:
210
0
      case CudaArch::GFX1011:
211
0
      case CudaArch::GFX1012:
212
0
      case CudaArch::GFX1013:
213
0
      case CudaArch::GFX1030:
214
0
      case CudaArch::GFX1031:
215
0
      case CudaArch::GFX1032:
216
0
      case CudaArch::GFX1033:
217
0
      case CudaArch::GFX1034:
218
0
      case CudaArch::GFX1035:
219
0
      case CudaArch::GFX1036:
220
0
      case CudaArch::GFX1100:
221
0
      case CudaArch::GFX1101:
222
0
      case CudaArch::GFX1102:
223
0
      case CudaArch::GFX1103:
224
0
      case CudaArch::Generic:
225
0
      case CudaArch::LAST:
226
0
        break;
227
0
      case CudaArch::UNUSED:
228
0
      case CudaArch::UNKNOWN:
229
0
        assert(false && "No GPU arch when compiling CUDA device code.");
230
0
        return "";
231
218
      case CudaArch::SM_20:
232
218
        return "200";
233
1
      case CudaArch::SM_21:
234
1
        return "210";
235
1
      case CudaArch::SM_30:
236
1
        return "300";
237
1
      case CudaArch::SM_32:
238
1
        return "320";
239
13
      case CudaArch::SM_35:
240
13
        return "350";
241
1
      case CudaArch::SM_37:
242
1
        return "370";
243
2
      case CudaArch::SM_50:
244
2
        return "500";
245
1
      case CudaArch::SM_52:
246
1
        return "520";
247
1
      case CudaArch::SM_53:
248
1
        return "530";
249
4
      case CudaArch::SM_60:
250
4
        return "600";
251
1
      case CudaArch::SM_61:
252
1
        return "610";
253
1
      case CudaArch::SM_62:
254
1
        return "620";
255
8
      case CudaArch::SM_70:
256
8
        return "700";
257
1
      case CudaArch::SM_72:
258
1
        return "720";
259
1
      case CudaArch::SM_75:
260
1
        return "750";
261
5
      case CudaArch::SM_80:
262
5
        return "800";
263
1
      case CudaArch::SM_86:
264
1
        return "860";
265
261
      }
266
0
      llvm_unreachable("unhandled CudaArch");
267
0
    }();
268
261
    Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
269
261
  }
270
314
}
271
272
314
ArrayRef<Builtin::Info> NVPTXTargetInfo::getTargetBuiltins() const {
273
314
  return llvm::makeArrayRef(BuiltinInfo, clang::NVPTX::LastTSBuiltin -
274
314
                                             Builtin::FirstTSBuiltin);
275
314
}