Coverage Report

Created: 2022-07-16 07:03

/Users/buildslave/jenkins/workspace/coverage/llvm-project/clang/lib/Basic/Targets/PPC.cpp
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Count
Source (jump to first uncovered line)
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//===--- PPC.cpp - Implement PPC target feature support -------------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
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//
9
// This file implements PPC TargetInfo objects.
10
//
11
//===----------------------------------------------------------------------===//
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13
#include "PPC.h"
14
#include "clang/Basic/Diagnostic.h"
15
#include "clang/Basic/MacroBuilder.h"
16
#include "clang/Basic/TargetBuiltins.h"
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using namespace clang;
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using namespace clang::targets;
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const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
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#define BUILTIN(ID, TYPE, ATTRS)                                               \
23
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
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#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER)                                    \
25
  {#ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr},
26
#include "clang/Basic/BuiltinsPPC.def"
27
};
28
29
/// handleTargetFeatures - Perform initialization based on the user
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/// configured set of features.
31
bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
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4.12k
                                         DiagnosticsEngine &Diags) {
33
4.12k
  FloatABI = HardFloat;
34
70.4k
  for (const auto &Feature : Features) {
35
70.4k
    if (Feature == "+altivec") {
36
316
      HasAltivec = true;
37
70.1k
    } else if (Feature == "+vsx") {
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246
      HasVSX = true;
39
69.9k
    } else if (Feature == "+crbits") {
40
149
      UseCRBits = true;
41
69.7k
    } else if (Feature == "+bpermd") {
42
208
      HasBPERMD = true;
43
69.5k
    } else if (Feature == "+extdiv") {
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208
      HasExtDiv = true;
45
69.3k
    } else if (Feature == "+power8-vector") {
46
154
      HasP8Vector = true;
47
69.2k
    } else if (Feature == "+crypto") {
48
154
      HasP8Crypto = true;
49
69.0k
    } else if (Feature == "+direct-move") {
50
152
      HasDirectMove = true;
51
68.9k
    } else if (Feature == "+htm") {
52
109
      HasHTM = true;
53
68.7k
    } else if (Feature == "+float128") {
54
18
      HasFloat128 = true;
55
68.7k
    } else if (Feature == "+power9-vector") {
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84
      HasP9Vector = true;
57
68.6k
    } else if (Feature == "+power10-vector") {
58
47
      HasP10Vector = true;
59
68.6k
    } else if (Feature == "+pcrelative-memops") {
60
48
      HasPCRelativeMemops = true;
61
68.5k
    } else if (Feature == "+prefix-instrs") {
62
48
      HasPrefixInstrs = true;
63
68.5k
    } else if (Feature == "+spe" || 
Feature == "+efpu2"68.5k
) {
64
2
      HasStrictFP = false;
65
2
      HasSPE = true;
66
2
      LongDoubleWidth = LongDoubleAlign = 64;
67
2
      LongDoubleFormat = &llvm::APFloat::IEEEdouble();
68
68.5k
    } else if (Feature == "-hard-float") {
69
2
      FloatABI = SoftFloat;
70
68.5k
    } else if (Feature == "+paired-vector-memops") {
71
48
      PairedVectorMemops = true;
72
68.4k
    } else if (Feature == "+mma") {
73
48
      HasMMA = true;
74
68.4k
    } else if (Feature == "+rop-protect") {
75
9
      HasROPProtect = true;
76
68.4k
    } else if (Feature == "+privileged") {
77
6
      HasPrivileged = true;
78
68.4k
    } else if (Feature == "+isa-v206-instructions") {
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209
      IsISA2_06 = true;
80
68.2k
    } else if (Feature == "+isa-v207-instructions") {
81
153
      IsISA2_07 = true;
82
68.0k
    } else if (Feature == "+isa-v30-instructions") {
83
84
      IsISA3_0 = true;
84
67.9k
    } else if (Feature == "+isa-v31-instructions") {
85
49
      IsISA3_1 = true;
86
67.9k
    } else if (Feature == "+quadword-atomics") {
87
103
      HasQuadwordAtomics = true;
88
103
    }
89
    // TODO: Finish this list and add an assert that we've handled them
90
    // all.
91
70.4k
  }
92
93
4.12k
  return true;
94
4.12k
}
95
96
559
static void defineXLCompatMacros(MacroBuilder &Builder) {
97
559
  Builder.defineMacro("__popcntb", "__builtin_ppc_popcntb");
98
559
  Builder.defineMacro("__poppar4", "__builtin_ppc_poppar4");
99
559
  Builder.defineMacro("__poppar8", "__builtin_ppc_poppar8");
100
559
  Builder.defineMacro("__eieio", "__builtin_ppc_eieio");
101
559
  Builder.defineMacro("__iospace_eieio", "__builtin_ppc_iospace_eieio");
102
559
  Builder.defineMacro("__isync", "__builtin_ppc_isync");
103
559
  Builder.defineMacro("__lwsync", "__builtin_ppc_lwsync");
104
559
  Builder.defineMacro("__iospace_lwsync", "__builtin_ppc_iospace_lwsync");
105
559
  Builder.defineMacro("__sync", "__builtin_ppc_sync");
106
559
  Builder.defineMacro("__iospace_sync", "__builtin_ppc_iospace_sync");
107
559
  Builder.defineMacro("__dcbfl", "__builtin_ppc_dcbfl");
108
559
  Builder.defineMacro("__dcbflp", "__builtin_ppc_dcbflp");
109
559
  Builder.defineMacro("__dcbst", "__builtin_ppc_dcbst");
110
559
  Builder.defineMacro("__dcbt", "__builtin_ppc_dcbt");
111
559
  Builder.defineMacro("__dcbtst", "__builtin_ppc_dcbtst");
112
559
  Builder.defineMacro("__dcbz", "__builtin_ppc_dcbz");
113
559
  Builder.defineMacro("__icbt", "__builtin_ppc_icbt");
114
559
  Builder.defineMacro("__compare_and_swap", "__builtin_ppc_compare_and_swap");
115
559
  Builder.defineMacro("__compare_and_swaplp",
116
559
                      "__builtin_ppc_compare_and_swaplp");
117
559
  Builder.defineMacro("__fetch_and_add", "__builtin_ppc_fetch_and_add");
118
559
  Builder.defineMacro("__fetch_and_addlp", "__builtin_ppc_fetch_and_addlp");
119
559
  Builder.defineMacro("__fetch_and_and", "__builtin_ppc_fetch_and_and");
120
559
  Builder.defineMacro("__fetch_and_andlp", "__builtin_ppc_fetch_and_andlp");
121
559
  Builder.defineMacro("__fetch_and_or", "__builtin_ppc_fetch_and_or");
122
559
  Builder.defineMacro("__fetch_and_orlp", "__builtin_ppc_fetch_and_orlp");
123
559
  Builder.defineMacro("__fetch_and_swap", "__builtin_ppc_fetch_and_swap");
124
559
  Builder.defineMacro("__fetch_and_swaplp", "__builtin_ppc_fetch_and_swaplp");
125
559
  Builder.defineMacro("__ldarx", "__builtin_ppc_ldarx");
126
559
  Builder.defineMacro("__lwarx", "__builtin_ppc_lwarx");
127
559
  Builder.defineMacro("__lharx", "__builtin_ppc_lharx");
128
559
  Builder.defineMacro("__lbarx", "__builtin_ppc_lbarx");
129
559
  Builder.defineMacro("__stfiw", "__builtin_ppc_stfiw");
130
559
  Builder.defineMacro("__stdcx", "__builtin_ppc_stdcx");
131
559
  Builder.defineMacro("__stwcx", "__builtin_ppc_stwcx");
132
559
  Builder.defineMacro("__sthcx", "__builtin_ppc_sthcx");
133
559
  Builder.defineMacro("__stbcx", "__builtin_ppc_stbcx");
134
559
  Builder.defineMacro("__tdw", "__builtin_ppc_tdw");
135
559
  Builder.defineMacro("__tw", "__builtin_ppc_tw");
136
559
  Builder.defineMacro("__trap", "__builtin_ppc_trap");
137
559
  Builder.defineMacro("__trapd", "__builtin_ppc_trapd");
138
559
  Builder.defineMacro("__fcfid", "__builtin_ppc_fcfid");
139
559
  Builder.defineMacro("__fcfud", "__builtin_ppc_fcfud");
140
559
  Builder.defineMacro("__fctid", "__builtin_ppc_fctid");
141
559
  Builder.defineMacro("__fctidz", "__builtin_ppc_fctidz");
142
559
  Builder.defineMacro("__fctiw", "__builtin_ppc_fctiw");
143
559
  Builder.defineMacro("__fctiwz", "__builtin_ppc_fctiwz");
144
559
  Builder.defineMacro("__fctudz", "__builtin_ppc_fctudz");
145
559
  Builder.defineMacro("__fctuwz", "__builtin_ppc_fctuwz");
146
559
  Builder.defineMacro("__cmpeqb", "__builtin_ppc_cmpeqb");
147
559
  Builder.defineMacro("__cmprb", "__builtin_ppc_cmprb");
148
559
  Builder.defineMacro("__setb", "__builtin_ppc_setb");
149
559
  Builder.defineMacro("__cmpb", "__builtin_ppc_cmpb");
150
559
  Builder.defineMacro("__mulhd", "__builtin_ppc_mulhd");
151
559
  Builder.defineMacro("__mulhdu", "__builtin_ppc_mulhdu");
152
559
  Builder.defineMacro("__mulhw", "__builtin_ppc_mulhw");
153
559
  Builder.defineMacro("__mulhwu", "__builtin_ppc_mulhwu");
154
559
  Builder.defineMacro("__maddhd", "__builtin_ppc_maddhd");
155
559
  Builder.defineMacro("__maddhdu", "__builtin_ppc_maddhdu");
156
559
  Builder.defineMacro("__maddld", "__builtin_ppc_maddld");
157
559
  Builder.defineMacro("__rlwnm", "__builtin_ppc_rlwnm");
158
559
  Builder.defineMacro("__rlwimi", "__builtin_ppc_rlwimi");
159
559
  Builder.defineMacro("__rldimi", "__builtin_ppc_rldimi");
160
559
  Builder.defineMacro("__load2r", "__builtin_ppc_load2r");
161
559
  Builder.defineMacro("__load4r", "__builtin_ppc_load4r");
162
559
  Builder.defineMacro("__load8r", "__builtin_ppc_load8r");
163
559
  Builder.defineMacro("__store2r", "__builtin_ppc_store2r");
164
559
  Builder.defineMacro("__store4r", "__builtin_ppc_store4r");
165
559
  Builder.defineMacro("__store8r", "__builtin_ppc_store8r");
166
559
  Builder.defineMacro("__extract_exp", "__builtin_ppc_extract_exp");
167
559
  Builder.defineMacro("__extract_sig", "__builtin_ppc_extract_sig");
168
559
  Builder.defineMacro("__mtfsb0", "__builtin_ppc_mtfsb0");
169
559
  Builder.defineMacro("__mtfsb1", "__builtin_ppc_mtfsb1");
170
559
  Builder.defineMacro("__mtfsf", "__builtin_ppc_mtfsf");
171
559
  Builder.defineMacro("__mtfsfi", "__builtin_ppc_mtfsfi");
172
559
  Builder.defineMacro("__insert_exp", "__builtin_ppc_insert_exp");
173
559
  Builder.defineMacro("__fmsub", "__builtin_ppc_fmsub");
174
559
  Builder.defineMacro("__fmsubs", "__builtin_ppc_fmsubs");
175
559
  Builder.defineMacro("__fnmadd", "__builtin_ppc_fnmadd");
176
559
  Builder.defineMacro("__fnmadds", "__builtin_ppc_fnmadds");
177
559
  Builder.defineMacro("__fnmsub", "__builtin_ppc_fnmsub");
178
559
  Builder.defineMacro("__fnmsubs", "__builtin_ppc_fnmsubs");
179
559
  Builder.defineMacro("__fre", "__builtin_ppc_fre");
180
559
  Builder.defineMacro("__fres", "__builtin_ppc_fres");
181
559
  Builder.defineMacro("__swdiv_nochk", "__builtin_ppc_swdiv_nochk");
182
559
  Builder.defineMacro("__swdivs_nochk", "__builtin_ppc_swdivs_nochk");
183
559
  Builder.defineMacro("__alloca", "__builtin_alloca");
184
559
  Builder.defineMacro("__vcipher", "__builtin_altivec_crypto_vcipher");
185
559
  Builder.defineMacro("__vcipherlast", "__builtin_altivec_crypto_vcipherlast");
186
559
  Builder.defineMacro("__vncipher", "__builtin_altivec_crypto_vncipher");
187
559
  Builder.defineMacro("__vncipherlast",
188
559
                      "__builtin_altivec_crypto_vncipherlast");
189
559
  Builder.defineMacro("__vpermxor", "__builtin_altivec_crypto_vpermxor");
190
559
  Builder.defineMacro("__vpmsumb", "__builtin_altivec_crypto_vpmsumb");
191
559
  Builder.defineMacro("__vpmsumd", "__builtin_altivec_crypto_vpmsumd");
192
559
  Builder.defineMacro("__vpmsumh", "__builtin_altivec_crypto_vpmsumh");
193
559
  Builder.defineMacro("__vpmsumw", "__builtin_altivec_crypto_vpmsumw");
194
559
  Builder.defineMacro("__divde", "__builtin_divde");
195
559
  Builder.defineMacro("__divwe", "__builtin_divwe");
196
559
  Builder.defineMacro("__divdeu", "__builtin_divdeu");
197
559
  Builder.defineMacro("__divweu", "__builtin_divweu");
198
559
  Builder.defineMacro("__alignx", "__builtin_ppc_alignx");
199
559
  Builder.defineMacro("__bcopy", "bcopy");
200
559
  Builder.defineMacro("__bpermd", "__builtin_bpermd");
201
559
  Builder.defineMacro("__cntlz4", "__builtin_clz");
202
559
  Builder.defineMacro("__cntlz8", "__builtin_clzll");
203
559
  Builder.defineMacro("__cmplx", "__builtin_complex");
204
559
  Builder.defineMacro("__cmplxf", "__builtin_complex");
205
559
  Builder.defineMacro("__cnttz4", "__builtin_ctz");
206
559
  Builder.defineMacro("__cnttz8", "__builtin_ctzll");
207
559
  Builder.defineMacro("__darn", "__builtin_darn");
208
559
  Builder.defineMacro("__darn_32", "__builtin_darn_32");
209
559
  Builder.defineMacro("__darn_raw", "__builtin_darn_raw");
210
559
  Builder.defineMacro("__dcbf", "__builtin_dcbf");
211
559
  Builder.defineMacro("__fmadd", "__builtin_fma");
212
559
  Builder.defineMacro("__fmadds", "__builtin_fmaf");
213
559
  Builder.defineMacro("__abs", "__builtin_abs");
214
559
  Builder.defineMacro("__labs", "__builtin_labs");
215
559
  Builder.defineMacro("__llabs", "__builtin_llabs");
216
559
  Builder.defineMacro("__popcnt4", "__builtin_popcount");
217
559
  Builder.defineMacro("__popcnt8", "__builtin_popcountll");
218
559
  Builder.defineMacro("__readflm", "__builtin_readflm");
219
559
  Builder.defineMacro("__rotatel4", "__builtin_rotateleft32");
220
559
  Builder.defineMacro("__rotatel8", "__builtin_rotateleft64");
221
559
  Builder.defineMacro("__rdlam", "__builtin_ppc_rdlam");
222
559
  Builder.defineMacro("__setflm", "__builtin_setflm");
223
559
  Builder.defineMacro("__setrnd", "__builtin_setrnd");
224
559
  Builder.defineMacro("__dcbtstt", "__builtin_ppc_dcbtstt");
225
559
  Builder.defineMacro("__dcbtt", "__builtin_ppc_dcbtt");
226
559
  Builder.defineMacro("__mftbu", "__builtin_ppc_mftbu");
227
559
  Builder.defineMacro("__mfmsr", "__builtin_ppc_mfmsr");
228
559
  Builder.defineMacro("__mtmsr", "__builtin_ppc_mtmsr");
229
559
  Builder.defineMacro("__mfspr", "__builtin_ppc_mfspr");
230
559
  Builder.defineMacro("__mtspr", "__builtin_ppc_mtspr");
231
559
  Builder.defineMacro("__fric", "__builtin_ppc_fric");
232
559
  Builder.defineMacro("__frim", "__builtin_ppc_frim");
233
559
  Builder.defineMacro("__frims", "__builtin_ppc_frims");
234
559
  Builder.defineMacro("__frin", "__builtin_ppc_frin");
235
559
  Builder.defineMacro("__frins", "__builtin_ppc_frins");
236
559
  Builder.defineMacro("__frip", "__builtin_ppc_frip");
237
559
  Builder.defineMacro("__frips", "__builtin_ppc_frips");
238
559
  Builder.defineMacro("__friz", "__builtin_ppc_friz");
239
559
  Builder.defineMacro("__frizs", "__builtin_ppc_frizs");
240
559
  Builder.defineMacro("__fsel", "__builtin_ppc_fsel");
241
559
  Builder.defineMacro("__fsels", "__builtin_ppc_fsels");
242
559
  Builder.defineMacro("__frsqrte", "__builtin_ppc_frsqrte");
243
559
  Builder.defineMacro("__frsqrtes", "__builtin_ppc_frsqrtes");
244
559
  Builder.defineMacro("__fsqrt", "__builtin_ppc_fsqrt");
245
559
  Builder.defineMacro("__fsqrts", "__builtin_ppc_fsqrts");
246
559
  Builder.defineMacro("__addex", "__builtin_ppc_addex");
247
559
  Builder.defineMacro("__cmplxl", "__builtin_complex");
248
559
  Builder.defineMacro("__compare_exp_uo", "__builtin_ppc_compare_exp_uo");
249
559
  Builder.defineMacro("__compare_exp_lt", "__builtin_ppc_compare_exp_lt");
250
559
  Builder.defineMacro("__compare_exp_gt", "__builtin_ppc_compare_exp_gt");
251
559
  Builder.defineMacro("__compare_exp_eq", "__builtin_ppc_compare_exp_eq");
252
559
  Builder.defineMacro("__test_data_class", "__builtin_ppc_test_data_class");
253
559
  Builder.defineMacro("__swdiv", "__builtin_ppc_swdiv");
254
559
  Builder.defineMacro("__swdivs", "__builtin_ppc_swdivs");
255
559
  Builder.defineMacro("__fnabs", "__builtin_ppc_fnabs");
256
559
  Builder.defineMacro("__fnabss", "__builtin_ppc_fnabss");
257
559
  Builder.defineMacro("__builtin_maxfe", "__builtin_ppc_maxfe");
258
559
  Builder.defineMacro("__builtin_maxfl", "__builtin_ppc_maxfl");
259
559
  Builder.defineMacro("__builtin_maxfs", "__builtin_ppc_maxfs");
260
559
  Builder.defineMacro("__builtin_minfe", "__builtin_ppc_minfe");
261
559
  Builder.defineMacro("__builtin_minfl", "__builtin_ppc_minfl");
262
559
  Builder.defineMacro("__builtin_minfs", "__builtin_ppc_minfs");
263
559
}
264
265
/// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
266
/// #defines that are not tied to a specific subtarget.
267
void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
268
4.12k
                                     MacroBuilder &Builder) const {
269
270
  // We define the XLC compatibility macros only on AIX and Linux since XLC
271
  // was never available on any other platforms.
272
4.12k
  if (getTriple().isOSAIX() || 
getTriple().isOSLinux()3.87k
)
273
559
    defineXLCompatMacros(Builder);
274
275
  // Target identification.
276
4.12k
  Builder.defineMacro("__ppc__");
277
4.12k
  Builder.defineMacro("__PPC__");
278
4.12k
  Builder.defineMacro("_ARCH_PPC");
279
4.12k
  Builder.defineMacro("__powerpc__");
280
4.12k
  Builder.defineMacro("__POWERPC__");
281
4.12k
  if (PointerWidth == 64) {
282
3.87k
    Builder.defineMacro("_ARCH_PPC64");
283
3.87k
    Builder.defineMacro("__powerpc64__");
284
3.87k
    Builder.defineMacro("__ppc64__");
285
3.87k
    Builder.defineMacro("__PPC64__");
286
3.87k
  } else 
if (246
getTriple().isOSAIX()246
) {
287
    // The XL compilers on AIX define _ARCH_PPC64 for both 32 and 64-bit modes.
288
146
    Builder.defineMacro("_ARCH_PPC64");
289
146
  }
290
4.12k
  if (getTriple().isOSAIX()) {
291
252
    Builder.defineMacro("__THW_PPC__");
292
    // Define __PPC and __powerpc for AIX XL C/C++ compatibility
293
252
    Builder.defineMacro("__PPC");
294
252
    Builder.defineMacro("__powerpc");
295
252
  }
296
297
  // Target properties.
298
4.12k
  if (getTriple().getArch() == llvm::Triple::ppc64le ||
299
4.12k
      
getTriple().getArch() == llvm::Triple::ppcle519
) {
300
3.60k
    Builder.defineMacro("_LITTLE_ENDIAN");
301
3.60k
  } else {
302
517
    if (!getTriple().isOSNetBSD() &&
303
517
        
!getTriple().isOSOpenBSD()511
)
304
505
      Builder.defineMacro("_BIG_ENDIAN");
305
517
  }
306
307
  // ABI options.
308
4.12k
  if (ABI == "elfv1")
309
165
    Builder.defineMacro("_CALL_ELF", "1");
310
4.12k
  if (ABI == "elfv2")
311
3.60k
    Builder.defineMacro("_CALL_ELF", "2");
312
313
  // This typically is only for a new enough linker (bfd >= 2.16.2 or gold), but
314
  // our support post-dates this and it should work on all 64-bit ppc linux
315
  // platforms. It is guaranteed to work on all elfv2 platforms.
316
4.12k
  if (getTriple().getOS() == llvm::Triple::Linux && 
PointerWidth == 64307
)
317
280
    Builder.defineMacro("_CALL_LINUX", "1");
318
319
  // Subtarget options.
320
4.12k
  if (!getTriple().isOSAIX()){
321
3.87k
    Builder.defineMacro("__NATURAL_ALIGNMENT__");
322
3.87k
  }
323
4.12k
  Builder.defineMacro("__REGISTER_PREFIX__", "");
324
325
  // FIXME: Should be controlled by command line option.
326
4.12k
  if (LongDoubleWidth == 128) {
327
3.84k
    Builder.defineMacro("__LONG_DOUBLE_128__");
328
3.84k
    Builder.defineMacro("__LONGDOUBLE128");
329
3.84k
    if (Opts.PPCIEEELongDouble)
330
8
      Builder.defineMacro("__LONG_DOUBLE_IEEE128__");
331
3.84k
    else
332
3.84k
      Builder.defineMacro("__LONG_DOUBLE_IBM128__");
333
3.84k
  }
334
335
4.12k
  if (getTriple().isOSAIX() && 
Opts.LongDoubleSize == 64252
) {
336
1
    assert(LongDoubleWidth == 64);
337
0
    Builder.defineMacro("__LONGDOUBLE64");
338
1
  }
339
340
  // Define this for elfv2 (64-bit only) or 64-bit darwin.
341
4.12k
  if (ABI == "elfv2" ||
342
4.12k
      
(516
getTriple().getOS() == llvm::Triple::Darwin516
&&
PointerWidth == 645
))
343
3.60k
    Builder.defineMacro("__STRUCT_PARM_ALIGN__", "16");
344
345
4.12k
  if (ArchDefs & ArchDefineName)
346
3
    Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
347
4.12k
  if (ArchDefs & ArchDefinePpcgr)
348
231
    Builder.defineMacro("_ARCH_PPCGR");
349
4.12k
  if (ArchDefs & ArchDefinePpcsq)
350
226
    Builder.defineMacro("_ARCH_PPCSQ");
351
4.12k
  if (ArchDefs & ArchDefine440)
352
0
    Builder.defineMacro("_ARCH_440");
353
4.12k
  if (ArchDefs & ArchDefine603)
354
2
    Builder.defineMacro("_ARCH_603");
355
4.12k
  if (ArchDefs & ArchDefine604)
356
0
    Builder.defineMacro("_ARCH_604");
357
4.12k
  if (ArchDefs & ArchDefinePwr4)
358
226
    Builder.defineMacro("_ARCH_PWR4");
359
4.12k
  if (ArchDefs & ArchDefinePwr5)
360
224
    Builder.defineMacro("_ARCH_PWR5");
361
4.12k
  if (ArchDefs & ArchDefinePwr5x)
362
222
    Builder.defineMacro("_ARCH_PWR5X");
363
4.12k
  if (ArchDefs & ArchDefinePwr6)
364
220
    Builder.defineMacro("_ARCH_PWR6");
365
4.12k
  if (ArchDefs & ArchDefinePwr6x)
366
2
    Builder.defineMacro("_ARCH_PWR6X");
367
4.12k
  if (ArchDefs & ArchDefinePwr7)
368
215
    Builder.defineMacro("_ARCH_PWR7");
369
4.12k
  if (ArchDefs & ArchDefinePwr8)
370
159
    Builder.defineMacro("_ARCH_PWR8");
371
4.12k
  if (ArchDefs & ArchDefinePwr9)
372
87
    Builder.defineMacro("_ARCH_PWR9");
373
4.12k
  if (ArchDefs & ArchDefinePwr10)
374
49
    Builder.defineMacro("_ARCH_PWR10");
375
4.12k
  if (ArchDefs & ArchDefineA2)
376
1
    Builder.defineMacro("_ARCH_A2");
377
4.12k
  if (ArchDefs & ArchDefineE500)
378
1
    Builder.defineMacro("__NO_LWSYNC__");
379
4.12k
  if (ArchDefs & ArchDefineFuture)
380
3
    Builder.defineMacro("_ARCH_PWR_FUTURE");
381
382
4.12k
  if (HasAltivec) {
383
316
    Builder.defineMacro("__VEC__", "10206");
384
316
    Builder.defineMacro("__ALTIVEC__");
385
316
  }
386
4.12k
  if (HasSPE) {
387
2
    Builder.defineMacro("__SPE__");
388
2
    Builder.defineMacro("__NO_FPRS__");
389
2
  }
390
4.12k
  if (HasVSX)
391
246
    Builder.defineMacro("__VSX__");
392
4.12k
  if (HasP8Vector)
393
154
    Builder.defineMacro("__POWER8_VECTOR__");
394
4.12k
  if (HasP8Crypto)
395
154
    Builder.defineMacro("__CRYPTO__");
396
4.12k
  if (HasHTM)
397
109
    Builder.defineMacro("__HTM__");
398
4.12k
  if (HasFloat128)
399
18
    Builder.defineMacro("__FLOAT128__");
400
4.12k
  if (HasP9Vector)
401
84
    Builder.defineMacro("__POWER9_VECTOR__");
402
4.12k
  if (HasMMA)
403
48
    Builder.defineMacro("__MMA__");
404
4.12k
  if (HasROPProtect)
405
9
    Builder.defineMacro("__ROP_PROTECT__");
406
4.12k
  if (HasP10Vector)
407
47
    Builder.defineMacro("__POWER10_VECTOR__");
408
4.12k
  if (HasPCRelativeMemops)
409
48
    Builder.defineMacro("__PCREL__");
410
411
4.12k
  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
412
4.12k
  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
413
4.12k
  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
414
4.12k
  if (PointerWidth == 64)
415
3.87k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
416
417
  // We have support for the bswap intrinsics so we can define this.
418
4.12k
  Builder.defineMacro("__HAVE_BSWAP__", "1");
419
420
  // FIXME: The following are not yet generated here by Clang, but are
421
  //        generated by GCC:
422
  //
423
  //   _SOFT_FLOAT_
424
  //   __RECIP_PRECISION__
425
  //   __APPLE_ALTIVEC__
426
  //   __RECIP__
427
  //   __RECIPF__
428
  //   __RSQRTE__
429
  //   __RSQRTEF__
430
  //   _SOFT_DOUBLE_
431
  //   __NO_LWSYNC__
432
  //   __CMODEL_MEDIUM__
433
  //   __CMODEL_LARGE__
434
  //   _CALL_SYSV
435
  //   _CALL_DARWIN
436
4.12k
}
437
438
// Handle explicit options being passed to the compiler here: if we've
439
// explicitly turned off vsx and turned on any of:
440
// - power8-vector
441
// - direct-move
442
// - float128
443
// - power9-vector
444
// - paired-vector-memops
445
// - mma
446
// - power10-vector
447
// then go ahead and error since the customer has expressed an incompatible
448
// set of options.
449
static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags,
450
4.23k
                                 const std::vector<std::string> &FeaturesVec) {
451
452
  // vsx was not explicitly turned off.
453
4.23k
  if (!llvm::is_contained(FeaturesVec, "-vsx"))
454
4.19k
    return true;
455
456
308
  
auto FindVSXSubfeature = [&](StringRef Feature, StringRef Option) 44
{
457
308
    if (llvm::is_contained(FeaturesVec, Feature)) {
458
3
      Diags.Report(diag::err_opt_not_valid_with_opt) << Option << "-mno-vsx";
459
3
      return true;
460
3
    }
461
305
    return false;
462
308
  };
463
464
44
  bool Found = FindVSXSubfeature("+power8-vector", "-mpower8-vector");
465
44
  Found |= FindVSXSubfeature("+direct-move", "-mdirect-move");
466
44
  Found |= FindVSXSubfeature("+float128", "-mfloat128");
467
44
  Found |= FindVSXSubfeature("+power9-vector", "-mpower9-vector");
468
44
  Found |= FindVSXSubfeature("+paired-vector-memops", "-mpaired-vector-memops");
469
44
  Found |= FindVSXSubfeature("+mma", "-mmma");
470
44
  Found |= FindVSXSubfeature("+power10-vector", "-mpower10-vector");
471
472
  // Return false if any vsx subfeatures was found.
473
44
  return !Found;
474
4.23k
}
475
476
bool PPCTargetInfo::initFeatureMap(
477
    llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
478
4.23k
    const std::vector<std::string> &FeaturesVec) const {
479
4.23k
  Features["altivec"] = llvm::StringSwitch<bool>(CPU)
480
4.23k
                            .Case("7400", true)
481
4.23k
                            .Case("g4", true)
482
4.23k
                            .Case("7450", true)
483
4.23k
                            .Case("g4+", true)
484
4.23k
                            .Case("970", true)
485
4.23k
                            .Case("g5", true)
486
4.23k
                            .Case("pwr6", true)
487
4.23k
                            .Case("pwr7", true)
488
4.23k
                            .Case("pwr8", true)
489
4.23k
                            .Case("pwr9", true)
490
4.23k
                            .Case("ppc64", true)
491
4.23k
                            .Case("ppc64le", true)
492
4.23k
                            .Default(false);
493
494
4.23k
  Features["power9-vector"] = (CPU == "pwr9");
495
4.23k
  Features["crypto"] = llvm::StringSwitch<bool>(CPU)
496
4.23k
                           .Case("ppc64le", true)
497
4.23k
                           .Case("pwr9", true)
498
4.23k
                           .Case("pwr8", true)
499
4.23k
                           .Default(false);
500
4.23k
  Features["power8-vector"] = llvm::StringSwitch<bool>(CPU)
501
4.23k
                                  .Case("ppc64le", true)
502
4.23k
                                  .Case("pwr9", true)
503
4.23k
                                  .Case("pwr8", true)
504
4.23k
                                  .Default(false);
505
4.23k
  Features["bpermd"] = llvm::StringSwitch<bool>(CPU)
506
4.23k
                           .Case("ppc64le", true)
507
4.23k
                           .Case("pwr9", true)
508
4.23k
                           .Case("pwr8", true)
509
4.23k
                           .Case("pwr7", true)
510
4.23k
                           .Default(false);
511
4.23k
  Features["extdiv"] = llvm::StringSwitch<bool>(CPU)
512
4.23k
                           .Case("ppc64le", true)
513
4.23k
                           .Case("pwr9", true)
514
4.23k
                           .Case("pwr8", true)
515
4.23k
                           .Case("pwr7", true)
516
4.23k
                           .Default(false);
517
4.23k
  Features["direct-move"] = llvm::StringSwitch<bool>(CPU)
518
4.23k
                                .Case("ppc64le", true)
519
4.23k
                                .Case("pwr9", true)
520
4.23k
                                .Case("pwr8", true)
521
4.23k
                                .Default(false);
522
4.23k
  Features["crbits"] = llvm::StringSwitch<bool>(CPU)
523
4.23k
                                .Case("ppc64le", true)
524
4.23k
                                .Case("pwr9", true)
525
4.23k
                                .Case("pwr8", true)
526
4.23k
                                .Default(false);
527
4.23k
  Features["vsx"] = llvm::StringSwitch<bool>(CPU)
528
4.23k
                        .Case("ppc64le", true)
529
4.23k
                        .Case("pwr9", true)
530
4.23k
                        .Case("pwr8", true)
531
4.23k
                        .Case("pwr7", true)
532
4.23k
                        .Default(false);
533
4.23k
  Features["htm"] = llvm::StringSwitch<bool>(CPU)
534
4.23k
                        .Case("ppc64le", true)
535
4.23k
                        .Case("pwr9", true)
536
4.23k
                        .Case("pwr8", true)
537
4.23k
                        .Default(false);
538
539
  // ROP Protect is off by default.
540
4.23k
  Features["rop-protect"] = false;
541
  // Privileged instructions are off by default.
542
4.23k
  Features["privileged"] = false;
543
544
4.23k
  Features["spe"] = llvm::StringSwitch<bool>(CPU)
545
4.23k
                        .Case("8548", true)
546
4.23k
                        .Case("e500", true)
547
4.23k
                        .Default(false);
548
549
4.23k
  Features["isa-v206-instructions"] = llvm::StringSwitch<bool>(CPU)
550
4.23k
                                          .Case("ppc64le", true)
551
4.23k
                                          .Case("pwr9", true)
552
4.23k
                                          .Case("pwr8", true)
553
4.23k
                                          .Case("pwr7", true)
554
4.23k
                                          .Case("a2", true)
555
4.23k
                                          .Default(false);
556
557
4.23k
  Features["isa-v207-instructions"] = llvm::StringSwitch<bool>(CPU)
558
4.23k
                                          .Case("ppc64le", true)
559
4.23k
                                          .Case("pwr9", true)
560
4.23k
                                          .Case("pwr8", true)
561
4.23k
                                          .Default(false);
562
563
4.23k
  Features["isa-v30-instructions"] =
564
4.23k
      llvm::StringSwitch<bool>(CPU).Case("pwr9", true).Default(false);
565
566
4.23k
  Features["quadword-atomics"] =
567
4.23k
      getTriple().isArch64Bit() && llvm::StringSwitch<bool>(CPU)
568
3.98k
                                       .Case("pwr9", true)
569
3.98k
                                       .Case("pwr8", true)
570
3.98k
                                       .Default(false);
571
572
  // Power10 includes all the same features as Power9 plus any features specific
573
  // to the Power10 core.
574
4.23k
  if (CPU == "pwr10" || 
CPU == "power10"4.18k
) {
575
49
    initFeatureMap(Features, Diags, "pwr9", FeaturesVec);
576
49
    addP10SpecificFeatures(Features);
577
49
  }
578
579
  // Future CPU should include all of the features of Power 10 as well as any
580
  // additional features (yet to be determined) specific to it.
581
4.23k
  if (CPU == "future") {
582
3
    initFeatureMap(Features, Diags, "pwr10", FeaturesVec);
583
3
    addFutureSpecificFeatures(Features);
584
3
  }
585
586
4.23k
  if (!ppcUserFeaturesCheck(Diags, FeaturesVec))
587
3
    return false;
588
589
4.23k
  if (!(ArchDefs & ArchDefinePwr7) && 
(ArchDefs & ArchDefinePpcgr)3.94k
&&
590
4.23k
      
llvm::is_contained(FeaturesVec, "+float128")17
) {
591
    // We have __float128 on PPC but not pre-VSX targets.
592
1
    Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" << CPU;
593
1
    return false;
594
1
  }
595
596
4.23k
  if (!(ArchDefs & ArchDefinePwr10)) {
597
4.13k
    if (llvm::is_contained(FeaturesVec, "+mma")) {
598
      // MMA operations are not available pre-Power10.
599
4
      Diags.Report(diag::err_opt_not_valid_with_opt) << "-mmma" << CPU;
600
4
      return false;
601
4
    }
602
4.12k
    if (llvm::is_contained(FeaturesVec, "+pcrel")) {
603
      // PC-Relative instructions are not available pre-Power10,
604
      // and these instructions also require prefixed instructions support.
605
4
      Diags.Report(diag::err_opt_not_valid_without_opt)
606
4
          << "-mpcrel"
607
4
          << "-mcpu=pwr10 -mprefixed";
608
4
      return false;
609
4
    }
610
4.12k
    if (llvm::is_contained(FeaturesVec, "+prefixed")) {
611
      // Prefixed instructions are not available pre-Power10.
612
2
      Diags.Report(diag::err_opt_not_valid_without_opt) << "-mprefixed"
613
2
                                                        << "-mcpu=pwr10";
614
2
      return false;
615
2
    }
616
4.12k
    if (llvm::is_contained(FeaturesVec, "+paired-vector-memops")) {
617
      // Paired vector memops are not available pre-Power10.
618
2
      Diags.Report(diag::err_opt_not_valid_without_opt)
619
2
          << "-mpaired-vector-memops"
620
2
          << "-mcpu=pwr10";
621
2
      return false;
622
2
    }
623
4.12k
  }
624
625
4.21k
  if (!(ArchDefs & ArchDefinePwr8) &&
626
4.21k
      
llvm::is_contained(FeaturesVec, "+rop-protect")4.00k
) {
627
    // We can turn on ROP Protect on Power 8 and above.
628
2
    Diags.Report(diag::err_opt_not_valid_with_opt) << "-mrop-protect" << CPU;
629
2
    return false;
630
2
  }
631
632
4.21k
  if (!(ArchDefs & ArchDefinePwr8) &&
633
4.21k
      
llvm::is_contained(FeaturesVec, "+privileged")4.00k
) {
634
2
    Diags.Report(diag::err_opt_not_valid_with_opt) << "-mprivileged" << CPU;
635
2
    return false;
636
2
  }
637
638
4.21k
  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
639
4.21k
}
640
641
// Add any Power10 specific features.
642
void PPCTargetInfo::addP10SpecificFeatures(
643
49
    llvm::StringMap<bool> &Features) const {
644
49
  Features["htm"] = false; // HTM was removed for P10.
645
49
  Features["paired-vector-memops"] = true;
646
49
  Features["mma"] = true;
647
49
  Features["power10-vector"] = true;
648
49
  Features["pcrelative-memops"] = true;
649
49
  Features["prefix-instrs"] = true;
650
49
  Features["isa-v31-instructions"] = true;
651
49
}
652
653
// Add features specific to the "Future" CPU.
654
void PPCTargetInfo::addFutureSpecificFeatures(
655
3
    llvm::StringMap<bool> &Features) const {}
656
657
11.1k
bool PPCTargetInfo::hasFeature(StringRef Feature) const {
658
11.1k
  return llvm::StringSwitch<bool>(Feature)
659
11.1k
      .Case("powerpc", true)
660
11.1k
      .Case("altivec", HasAltivec)
661
11.1k
      .Case("vsx", HasVSX)
662
11.1k
      .Case("crbits", UseCRBits)
663
11.1k
      .Case("power8-vector", HasP8Vector)
664
11.1k
      .Case("crypto", HasP8Crypto)
665
11.1k
      .Case("direct-move", HasDirectMove)
666
11.1k
      .Case("htm", HasHTM)
667
11.1k
      .Case("bpermd", HasBPERMD)
668
11.1k
      .Case("extdiv", HasExtDiv)
669
11.1k
      .Case("float128", HasFloat128)
670
11.1k
      .Case("power9-vector", HasP9Vector)
671
11.1k
      .Case("paired-vector-memops", PairedVectorMemops)
672
11.1k
      .Case("power10-vector", HasP10Vector)
673
11.1k
      .Case("pcrelative-memops", HasPCRelativeMemops)
674
11.1k
      .Case("prefix-instrs", HasPrefixInstrs)
675
11.1k
      .Case("spe", HasSPE)
676
11.1k
      .Case("mma", HasMMA)
677
11.1k
      .Case("rop-protect", HasROPProtect)
678
11.1k
      .Case("privileged", HasPrivileged)
679
11.1k
      .Case("isa-v206-instructions", IsISA2_06)
680
11.1k
      .Case("isa-v207-instructions", IsISA2_07)
681
11.1k
      .Case("isa-v30-instructions", IsISA3_0)
682
11.1k
      .Case("isa-v31-instructions", IsISA3_1)
683
11.1k
      .Case("quadword-atomics", HasQuadwordAtomics)
684
11.1k
      .Default(false);
685
11.1k
}
686
687
void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
688
855
                                      StringRef Name, bool Enabled) const {
689
855
  if (Enabled) {
690
218
    if (Name == "efpu2")
691
0
      Features["spe"] = true;
692
    // If we're enabling any of the vsx based features then enable vsx and
693
    // altivec. We'll diagnose any problems later.
694
218
    bool FeatureHasVSX = llvm::StringSwitch<bool>(Name)
695
218
                             .Case("vsx", true)
696
218
                             .Case("direct-move", true)
697
218
                             .Case("power8-vector", true)
698
218
                             .Case("power9-vector", true)
699
218
                             .Case("paired-vector-memops", true)
700
218
                             .Case("power10-vector", true)
701
218
                             .Case("float128", true)
702
218
                             .Case("mma", true)
703
218
                             .Default(false);
704
218
    if (FeatureHasVSX)
705
70
      Features["vsx"] = Features["altivec"] = true;
706
218
    if (Name == "power9-vector")
707
1
      Features["power8-vector"] = true;
708
217
    else if (Name == "power10-vector")
709
4
      Features["power8-vector"] = Features["power9-vector"] = true;
710
218
    if (Name == "pcrel")
711
6
      Features["pcrelative-memops"] = true;
712
212
    else if (Name == "prefixed")
713
6
      Features["prefix-instrs"] = true;
714
206
    else
715
206
      Features[Name] = true;
716
637
  } else {
717
637
    if (Name == "spe")
718
36
      Features["efpu2"] = false;
719
    // If we're disabling altivec or vsx go ahead and disable all of the vsx
720
    // features.
721
637
    if ((Name == "altivec") || 
(Name == "vsx")601
)
722
77
      Features["vsx"] = Features["direct-move"] = Features["power8-vector"] =
723
77
          Features["float128"] = Features["power9-vector"] =
724
77
              Features["paired-vector-memops"] = Features["mma"] =
725
77
                  Features["power10-vector"] = false;
726
637
    if (Name == "power8-vector")
727
36
      Features["power9-vector"] = Features["paired-vector-memops"] =
728
36
          Features["mma"] = Features["power10-vector"] = false;
729
601
    else if (Name == "power9-vector")
730
36
      Features["paired-vector-memops"] = Features["mma"] =
731
36
          Features["power10-vector"] = false;
732
637
    if (Name == "pcrel")
733
2
      Features["pcrelative-memops"] = false;
734
635
    else if (Name == "prefixed")
735
2
      Features["prefix-instrs"] = false;
736
633
    else
737
633
      Features[Name] = false;
738
637
  }
739
855
}
740
741
const char *const PPCTargetInfo::GCCRegNames[] = {
742
    "r0",  "r1",     "r2",   "r3",      "r4",      "r5",  "r6",  "r7",  "r8",
743
    "r9",  "r10",    "r11",  "r12",     "r13",     "r14", "r15", "r16", "r17",
744
    "r18", "r19",    "r20",  "r21",     "r22",     "r23", "r24", "r25", "r26",
745
    "r27", "r28",    "r29",  "r30",     "r31",     "f0",  "f1",  "f2",  "f3",
746
    "f4",  "f5",     "f6",   "f7",      "f8",      "f9",  "f10", "f11", "f12",
747
    "f13", "f14",    "f15",  "f16",     "f17",     "f18", "f19", "f20", "f21",
748
    "f22", "f23",    "f24",  "f25",     "f26",     "f27", "f28", "f29", "f30",
749
    "f31", "mq",     "lr",   "ctr",     "ap",      "cr0", "cr1", "cr2", "cr3",
750
    "cr4", "cr5",    "cr6",  "cr7",     "xer",     "v0",  "v1",  "v2",  "v3",
751
    "v4",  "v5",     "v6",   "v7",      "v8",      "v9",  "v10", "v11", "v12",
752
    "v13", "v14",    "v15",  "v16",     "v17",     "v18", "v19", "v20", "v21",
753
    "v22", "v23",    "v24",  "v25",     "v26",     "v27", "v28", "v29", "v30",
754
    "v31", "vrsave", "vscr", "spe_acc", "spefscr", "sfp"
755
};
756
757
15
ArrayRef<const char *> PPCTargetInfo::getGCCRegNames() const {
758
15
  return llvm::makeArrayRef(GCCRegNames);
759
15
}
760
761
const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
762
    // While some of these aliases do map to different registers
763
    // they still share the same register name.
764
    {{"0"}, "r0"},     {{"1", "sp"}, "r1"}, {{"2"}, "r2"},
765
    {{"3"}, "r3"},     {{"4"}, "r4"},       {{"5"}, "r5"},
766
    {{"6"}, "r6"},     {{"7"}, "r7"},       {{"8"}, "r8"},
767
    {{"9"}, "r9"},     {{"10"}, "r10"},     {{"11"}, "r11"},
768
    {{"12"}, "r12"},   {{"13"}, "r13"},     {{"14"}, "r14"},
769
    {{"15"}, "r15"},   {{"16"}, "r16"},     {{"17"}, "r17"},
770
    {{"18"}, "r18"},   {{"19"}, "r19"},     {{"20"}, "r20"},
771
    {{"21"}, "r21"},   {{"22"}, "r22"},     {{"23"}, "r23"},
772
    {{"24"}, "r24"},   {{"25"}, "r25"},     {{"26"}, "r26"},
773
    {{"27"}, "r27"},   {{"28"}, "r28"},     {{"29"}, "r29"},
774
    {{"30"}, "r30"},   {{"31"}, "r31"},     {{"fr0"}, "f0"},
775
    {{"fr1"}, "f1"},   {{"fr2"}, "f2"},     {{"fr3"}, "f3"},
776
    {{"fr4"}, "f4"},   {{"fr5"}, "f5"},     {{"fr6"}, "f6"},
777
    {{"fr7"}, "f7"},   {{"fr8"}, "f8"},     {{"fr9"}, "f9"},
778
    {{"fr10"}, "f10"}, {{"fr11"}, "f11"},   {{"fr12"}, "f12"},
779
    {{"fr13"}, "f13"}, {{"fr14"}, "f14"},   {{"fr15"}, "f15"},
780
    {{"fr16"}, "f16"}, {{"fr17"}, "f17"},   {{"fr18"}, "f18"},
781
    {{"fr19"}, "f19"}, {{"fr20"}, "f20"},   {{"fr21"}, "f21"},
782
    {{"fr22"}, "f22"}, {{"fr23"}, "f23"},   {{"fr24"}, "f24"},
783
    {{"fr25"}, "f25"}, {{"fr26"}, "f26"},   {{"fr27"}, "f27"},
784
    {{"fr28"}, "f28"}, {{"fr29"}, "f29"},   {{"fr30"}, "f30"},
785
    {{"fr31"}, "f31"}, {{"cc"}, "cr0"},
786
};
787
788
6
ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const {
789
6
  return llvm::makeArrayRef(GCCRegAliases);
790
6
}
791
792
// PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
793
// vs0 ~ vs31 is mapping to 32 - 63,
794
// vs32 ~ vs63 is mapping to 77 - 108. 
795
const TargetInfo::AddlRegName GCCAddlRegNames[] = {
796
    // Table of additional register names to use in user input.
797
    {{"vs0"}, 32},   {{"vs1"}, 33},   {{"vs2"}, 34},   {{"vs3"}, 35}, 
798
    {{"vs4"}, 36},   {{"vs5"}, 37},   {{"vs6"}, 38},   {{"vs7"}, 39},
799
    {{"vs8"}, 40},   {{"vs9"}, 41},   {{"vs10"}, 42},  {{"vs11"}, 43},
800
    {{"vs12"}, 44},  {{"vs13"}, 45},  {{"vs14"}, 46},  {{"vs15"}, 47},
801
    {{"vs16"}, 48},  {{"vs17"}, 49},  {{"vs18"}, 50},  {{"vs19"}, 51},
802
    {{"vs20"}, 52},  {{"vs21"}, 53},  {{"vs22"}, 54},  {{"vs23"}, 55},
803
    {{"vs24"}, 56},  {{"vs25"}, 57},  {{"vs26"}, 58},  {{"vs27"}, 59},
804
    {{"vs28"}, 60},  {{"vs29"}, 61},  {{"vs30"}, 62},  {{"vs31"}, 63},
805
    {{"vs32"}, 77},  {{"vs33"}, 78},  {{"vs34"}, 79},  {{"vs35"}, 80},
806
    {{"vs36"}, 81},  {{"vs37"}, 82},  {{"vs38"}, 83},  {{"vs39"}, 84},
807
    {{"vs40"}, 85},  {{"vs41"}, 86},  {{"vs42"}, 87},  {{"vs43"}, 88},
808
    {{"vs44"}, 89},  {{"vs45"}, 90},  {{"vs46"}, 91},  {{"vs47"}, 92},
809
    {{"vs48"}, 93},  {{"vs49"}, 94},  {{"vs50"}, 95},  {{"vs51"}, 96},
810
    {{"vs52"}, 97},  {{"vs53"}, 98},  {{"vs54"}, 99},  {{"vs55"}, 100},
811
    {{"vs56"}, 101}, {{"vs57"}, 102}, {{"vs58"}, 103}, {{"vs59"}, 104},
812
    {{"vs60"}, 105}, {{"vs61"}, 106}, {{"vs62"}, 107}, {{"vs63"}, 108},
813
};
814
815
6
ArrayRef<TargetInfo::AddlRegName> PPCTargetInfo::getGCCAddlRegNames() const {
816
6
  if (ABI == "elfv2")
817
4
    return llvm::makeArrayRef(GCCAddlRegNames);
818
2
  else 
819
2
    return TargetInfo::getGCCAddlRegNames(); 
820
6
}
821
822
static constexpr llvm::StringLiteral ValidCPUNames[] = {
823
    {"generic"},     {"440"},     {"450"},    {"601"},       {"602"},
824
    {"603"},         {"603e"},    {"603ev"},  {"604"},       {"604e"},
825
    {"620"},         {"630"},     {"g3"},     {"7400"},      {"g4"},
826
    {"7450"},        {"g4+"},     {"750"},    {"8548"},      {"970"},
827
    {"g5"},          {"a2"},      {"e500"},   {"e500mc"},    {"e5500"},
828
    {"power3"},      {"pwr3"},    {"power4"}, {"pwr4"},      {"power5"},
829
    {"pwr5"},        {"power5x"}, {"pwr5x"},  {"power6"},    {"pwr6"},
830
    {"power6x"},     {"pwr6x"},   {"power7"}, {"pwr7"},      {"power8"},
831
    {"pwr8"},        {"power9"},  {"pwr9"},   {"power10"},   {"pwr10"},
832
    {"powerpc"},     {"ppc"},     {"ppc32"},  {"powerpc64"}, {"ppc64"},
833
    {"powerpc64le"}, {"ppc64le"}, {"future"}};
834
835
279
bool PPCTargetInfo::isValidCPUName(StringRef Name) const {
836
279
  return llvm::is_contained(ValidCPUNames, Name);
837
279
}
838
839
1
void PPCTargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
840
1
  Values.append(std::begin(ValidCPUNames), std::end(ValidCPUNames));
841
1
}
842
843
8.15k
void PPCTargetInfo::adjust(DiagnosticsEngine &Diags, LangOptions &Opts) {
844
8.15k
  if (HasAltivec)
845
630
    Opts.AltiVec = 1;
846
8.15k
  TargetInfo::adjust(Diags, Opts);
847
8.15k
  if (LongDoubleFormat != &llvm::APFloat::IEEEdouble())
848
7.60k
    LongDoubleFormat = Opts.PPCIEEELongDouble
849
7.60k
                           ? 
&llvm::APFloat::IEEEquad()16
850
7.60k
                           : 
&llvm::APFloat::PPCDoubleDouble()7.58k
;
851
8.15k
  Opts.IEEE128 = 1;
852
8.15k
}
853
854
4.12k
ArrayRef<Builtin::Info> PPCTargetInfo::getTargetBuiltins() const {
855
4.12k
  return llvm::makeArrayRef(BuiltinInfo, clang::PPC::LastTSBuiltin -
856
4.12k
                                             Builtin::FirstTSBuiltin);
857
4.12k
}