Coverage Report

Created: 2023-05-31 04:38

/Users/buildslave/jenkins/workspace/coverage/llvm-project/clang/lib/Basic/Targets/SPIR.h
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//===--- SPIR.h - Declare SPIR and SPIR-V target feature support *- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares SPIR and SPIR-V TargetInfo objects.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_SPIR_H
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#define LLVM_CLANG_LIB_BASIC_TARGETS_SPIR_H
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#include "Targets.h"
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#include "clang/Basic/TargetInfo.h"
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#include "clang/Basic/TargetOptions.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/TargetParser/Triple.h"
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#include <optional>
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namespace clang {
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namespace targets {
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// Used by both the SPIR and SPIR-V targets.
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static const unsigned SPIRDefIsPrivMap[] = {
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    0, // Default
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    1, // opencl_global
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    3, // opencl_local
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    2, // opencl_constant
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    0, // opencl_private
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    4, // opencl_generic
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    5, // opencl_global_device
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    6, // opencl_global_host
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    0, // cuda_device
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    0, // cuda_constant
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    0, // cuda_shared
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    // SYCL address space values for this map are dummy
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    0, // sycl_global
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    0, // sycl_global_device
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    0, // sycl_global_host
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    0, // sycl_local
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    0, // sycl_private
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    0, // ptr32_sptr
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    0, // ptr32_uptr
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    0, // ptr64
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    0, // hlsl_groupshared
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    // Wasm address space values for this target are dummy values,
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    // as it is only enabled for Wasm targets.
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    20, // wasm_funcref
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};
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// Used by both the SPIR and SPIR-V targets.
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static const unsigned SPIRDefIsGenMap[] = {
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    4, // Default
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    // OpenCL address space values for this map are dummy and they can't be used
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    0, // opencl_global
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    0, // opencl_local
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    0, // opencl_constant
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    0, // opencl_private
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    0, // opencl_generic
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    0, // opencl_global_device
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    0, // opencl_global_host
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    // cuda_* address space mapping is intended for HIPSPV (HIP to SPIR-V
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    // translation). This mapping is enabled when the language mode is HIP.
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    1, // cuda_device
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    // cuda_constant pointer can be casted to default/"flat" pointer, but in
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    // SPIR-V casts between constant and generic pointers are not allowed. For
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    // this reason cuda_constant is mapped to SPIR-V CrossWorkgroup.
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    1, // cuda_constant
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    3, // cuda_shared
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    1, // sycl_global
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    5, // sycl_global_device
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    6, // sycl_global_host
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    3, // sycl_local
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    0, // sycl_private
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    0, // ptr32_sptr
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    0, // ptr32_uptr
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    0, // ptr64
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    0, // hlsl_groupshared
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    // Wasm address space values for this target are dummy values,
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    // as it is only enabled for Wasm targets.
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    20, // wasm_funcref
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};
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// Base class for SPIR and SPIR-V target info.
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class LLVM_LIBRARY_VISIBILITY BaseSPIRTargetInfo : public TargetInfo {
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  std::unique_ptr<TargetInfo> HostTarget;
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protected:
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  BaseSPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
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      : TargetInfo(Triple) {
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    assert((Triple.isSPIR() || Triple.isSPIRV()) &&
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           "Invalid architecture for SPIR or SPIR-V.");
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    assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
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           "SPIR(-V) target must use unknown OS");
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    assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
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           "SPIR(-V) target must use unknown environment type");
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    TLSSupported = false;
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    VLASupported = false;
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    LongWidth = LongAlign = 64;
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    AddrSpaceMap = &SPIRDefIsPrivMap;
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    UseAddrSpaceMapMangling = true;
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    HasLegalHalfType = true;
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    HasFloat16 = true;
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    // Define available target features
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    // These must be defined in sorted order!
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    NoAsmVariants = true;
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    llvm::Triple HostTriple(Opts.HostTriple);
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    if (!HostTriple.isSPIR() && !HostTriple.isSPIRV() &&
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        HostTriple.getArch() != llvm::Triple::UnknownArch) {
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      HostTarget = AllocateTarget(llvm::Triple(Opts.HostTriple), Opts);
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      // Copy properties from host target.
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      BoolWidth = HostTarget->getBoolWidth();
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      BoolAlign = HostTarget->getBoolAlign();
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      IntWidth = HostTarget->getIntWidth();
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      IntAlign = HostTarget->getIntAlign();
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      HalfWidth = HostTarget->getHalfWidth();
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      HalfAlign = HostTarget->getHalfAlign();
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      FloatWidth = HostTarget->getFloatWidth();
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      FloatAlign = HostTarget->getFloatAlign();
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      DoubleWidth = HostTarget->getDoubleWidth();
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      DoubleAlign = HostTarget->getDoubleAlign();
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      LongWidth = HostTarget->getLongWidth();
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      LongAlign = HostTarget->getLongAlign();
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      LongLongWidth = HostTarget->getLongLongWidth();
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      LongLongAlign = HostTarget->getLongLongAlign();
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      MinGlobalAlign = HostTarget->getMinGlobalAlign(/* TypeSize = */ 0);
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      NewAlign = HostTarget->getNewAlign();
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      DefaultAlignForAttributeAligned =
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          HostTarget->getDefaultAlignForAttributeAligned();
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      IntMaxType = HostTarget->getIntMaxType();
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      WCharType = HostTarget->getWCharType();
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      WIntType = HostTarget->getWIntType();
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      Char16Type = HostTarget->getChar16Type();
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      Char32Type = HostTarget->getChar32Type();
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      Int64Type = HostTarget->getInt64Type();
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      SigAtomicType = HostTarget->getSigAtomicType();
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      ProcessIDType = HostTarget->getProcessIDType();
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      UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment();
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      UseZeroLengthBitfieldAlignment =
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          HostTarget->useZeroLengthBitfieldAlignment();
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      UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment();
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      ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary();
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      // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and
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      // we need those macros to be identical on host and device, because (among
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      // other things) they affect which standard library classes are defined,
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      // and we need all classes to be defined on both the host and device.
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      MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth();
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    }
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  }
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public:
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  // SPIR supports the half type and the only llvm intrinsic allowed in SPIR is
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  // memcpy as per section 3 of the SPIR spec.
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  bool useFP16ConversionIntrinsics() const override { return false; }
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  ArrayRef<Builtin::Info> getTargetBuiltins() const override {
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    return std::nullopt;
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  }
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  std::string_view getClobbers() const override { return ""; }
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  ArrayRef<const char *> getGCCRegNames() const override {
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    return std::nullopt;
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  }
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  bool validateAsmConstraint(const char *&Name,
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                             TargetInfo::ConstraintInfo &info) const override {
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    return true;
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  }
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  ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
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    return std::nullopt;
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  }
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  BuiltinVaListKind getBuiltinVaListKind() const override {
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    return TargetInfo::VoidPtrBuiltinVaList;
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  }
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  std::optional<unsigned>
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  getDWARFAddressSpace(unsigned AddressSpace) const override {
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    return AddressSpace;
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  }
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  CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
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    return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK
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                                                            : CCCR_Warning;
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  }
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  CallingConv getDefaultCallingConv() const override {
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    return CC_SpirFunction;
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  }
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  void setAddressSpaceMap(bool DefaultIsGeneric) {
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    AddrSpaceMap = DefaultIsGeneric ? 
&SPIRDefIsGenMap62
:
&SPIRDefIsPrivMap592
;
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  }
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  void adjust(DiagnosticsEngine &Diags, LangOptions &Opts) override {
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    TargetInfo::adjust(Diags, Opts);
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    // FIXME: SYCL specification considers unannotated pointers and references
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    // to be pointing to the generic address space. See section 5.9.3 of
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    // SYCL 2020 specification.
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    // Currently, there is no way of representing SYCL's and HIP/CUDA's default
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    // address space language semantic along with the semantics of embedded C's
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    // default address space in the same address space map. Hence the map needs
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    // to be reset to allow mapping to the desired value of 'Default' entry for
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    // SYCL and HIP/CUDA.
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    setAddressSpaceMap(
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        /*DefaultIsGeneric=*/Opts.SYCLIsDevice ||
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        // The address mapping from HIP/CUDA language for device code is only
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        // defined for SPIR-V.
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(620
getTriple().isSPIRV()620
&&
Opts.CUDAIsDevice44
));
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  }
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  void setSupportedOpenCLOpts() override {
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    // Assume all OpenCL extensions and optional core features are supported
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    // for SPIR and SPIR-V since they are generic targets.
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    supportAllOpenCLOpts();
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  }
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  bool hasBitIntType() const override { return true; }
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  bool hasInt128Type() const override { return false; }
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};
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class LLVM_LIBRARY_VISIBILITY SPIRTargetInfo : public BaseSPIRTargetInfo {
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public:
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  SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
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      : BaseSPIRTargetInfo(Triple, Opts) {
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    assert(Triple.isSPIR() && "Invalid architecture for SPIR.");
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    assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
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           "SPIR target must use unknown OS");
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    assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
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           "SPIR target must use unknown environment type");
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  }
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  void getTargetDefines(const LangOptions &Opts,
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                        MacroBuilder &Builder) const override;
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  bool hasFeature(StringRef Feature) const override {
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    return Feature == "spir";
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  }
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  bool checkArithmeticFenceSupported() const override { return true; }
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};
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class LLVM_LIBRARY_VISIBILITY SPIR32TargetInfo : public SPIRTargetInfo {
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public:
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  SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
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      : SPIRTargetInfo(Triple, Opts) {
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    assert(Triple.getArch() == llvm::Triple::spir &&
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           "Invalid architecture for 32-bit SPIR.");
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    PointerWidth = PointerAlign = 32;
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    SizeType = TargetInfo::UnsignedInt;
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    PtrDiffType = IntPtrType = TargetInfo::SignedInt;
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    resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
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                    "v96:128-v192:256-v256:256-v512:512-v1024:1024");
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  }
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  void getTargetDefines(const LangOptions &Opts,
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                        MacroBuilder &Builder) const override;
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};
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class LLVM_LIBRARY_VISIBILITY SPIR64TargetInfo : public SPIRTargetInfo {
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public:
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  SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
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      : SPIRTargetInfo(Triple, Opts) {
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    assert(Triple.getArch() == llvm::Triple::spir64 &&
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           "Invalid architecture for 64-bit SPIR.");
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    PointerWidth = PointerAlign = 64;
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    SizeType = TargetInfo::UnsignedLong;
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    PtrDiffType = IntPtrType = TargetInfo::SignedLong;
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    resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-"
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                    "v96:128-v192:256-v256:256-v512:512-v1024:1024");
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  }
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  void getTargetDefines(const LangOptions &Opts,
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                        MacroBuilder &Builder) const override;
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};
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class LLVM_LIBRARY_VISIBILITY SPIRVTargetInfo : public BaseSPIRTargetInfo {
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public:
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  SPIRVTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
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      : BaseSPIRTargetInfo(Triple, Opts) {
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    assert(Triple.isSPIRV() && "Invalid architecture for SPIR-V.");
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    assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
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           "SPIR-V target must use unknown OS");
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    assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
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           "SPIR-V target must use unknown environment type");
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  }
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  void getTargetDefines(const LangOptions &Opts,
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                        MacroBuilder &Builder) const override;
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  bool hasFeature(StringRef Feature) const override {
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    return Feature == "spirv";
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  }
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};
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class LLVM_LIBRARY_VISIBILITY SPIRV32TargetInfo : public SPIRVTargetInfo {
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public:
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  SPIRV32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
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      : SPIRVTargetInfo(Triple, Opts) {
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    assert(Triple.getArch() == llvm::Triple::spirv32 &&
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           "Invalid architecture for 32-bit SPIR-V.");
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    PointerWidth = PointerAlign = 32;
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    SizeType = TargetInfo::UnsignedInt;
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    PtrDiffType = IntPtrType = TargetInfo::SignedInt;
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    resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
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                    "v96:128-v192:256-v256:256-v512:512-v1024:1024");
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  }
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  void getTargetDefines(const LangOptions &Opts,
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                        MacroBuilder &Builder) const override;
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};
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class LLVM_LIBRARY_VISIBILITY SPIRV64TargetInfo : public SPIRVTargetInfo {
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public:
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  SPIRV64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
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      : SPIRVTargetInfo(Triple, Opts) {
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    assert(Triple.getArch() == llvm::Triple::spirv64 &&
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           "Invalid architecture for 64-bit SPIR-V.");
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    PointerWidth = PointerAlign = 64;
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    SizeType = TargetInfo::UnsignedLong;
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    PtrDiffType = IntPtrType = TargetInfo::SignedLong;
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    resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-"
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                    "v96:128-v192:256-v256:256-v512:512-v1024:1024");
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  }
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  void getTargetDefines(const LangOptions &Opts,
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                        MacroBuilder &Builder) const override;
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};
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} // namespace targets
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} // namespace clang
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#endif // LLVM_CLANG_LIB_BASIC_TARGETS_SPIR_H