Coverage Report

Created: 2022-05-17 06:19

/Users/buildslave/jenkins/workspace/coverage/llvm-project/clang/lib/Basic/Targets/X86.cpp
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Source (jump to first uncovered line)
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//===--- X86.cpp - Implement X86 target feature support -------------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file implements X86 TargetInfo objects.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "X86.h"
14
#include "clang/Basic/Builtins.h"
15
#include "clang/Basic/Diagnostic.h"
16
#include "clang/Basic/TargetBuiltins.h"
17
#include "llvm/ADT/StringExtras.h"
18
#include "llvm/ADT/StringRef.h"
19
#include "llvm/ADT/StringSwitch.h"
20
#include "llvm/Support/X86TargetParser.h"
21
22
namespace clang {
23
namespace targets {
24
25
const Builtin::Info BuiltinInfoX86[] = {
26
#define BUILTIN(ID, TYPE, ATTRS)                                               \
27
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
28
#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)                               \
29
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
30
#define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE)         \
31
  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
32
#include "clang/Basic/BuiltinsX86.def"
33
34
#define BUILTIN(ID, TYPE, ATTRS)                                               \
35
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
36
#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)                               \
37
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
38
#define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE)         \
39
  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
40
#include "clang/Basic/BuiltinsX86_64.def"
41
};
42
43
static const char *const GCCRegNames[] = {
44
    "ax",    "dx",    "cx",    "bx",    "si",      "di",    "bp",    "sp",
45
    "st",    "st(1)", "st(2)", "st(3)", "st(4)",   "st(5)", "st(6)", "st(7)",
46
    "argp",  "flags", "fpcr",  "fpsr",  "dirflag", "frame", "xmm0",  "xmm1",
47
    "xmm2",  "xmm3",  "xmm4",  "xmm5",  "xmm6",    "xmm7",  "mm0",   "mm1",
48
    "mm2",   "mm3",   "mm4",   "mm5",   "mm6",     "mm7",   "r8",    "r9",
49
    "r10",   "r11",   "r12",   "r13",   "r14",     "r15",   "xmm8",  "xmm9",
50
    "xmm10", "xmm11", "xmm12", "xmm13", "xmm14",   "xmm15", "ymm0",  "ymm1",
51
    "ymm2",  "ymm3",  "ymm4",  "ymm5",  "ymm6",    "ymm7",  "ymm8",  "ymm9",
52
    "ymm10", "ymm11", "ymm12", "ymm13", "ymm14",   "ymm15", "xmm16", "xmm17",
53
    "xmm18", "xmm19", "xmm20", "xmm21", "xmm22",   "xmm23", "xmm24", "xmm25",
54
    "xmm26", "xmm27", "xmm28", "xmm29", "xmm30",   "xmm31", "ymm16", "ymm17",
55
    "ymm18", "ymm19", "ymm20", "ymm21", "ymm22",   "ymm23", "ymm24", "ymm25",
56
    "ymm26", "ymm27", "ymm28", "ymm29", "ymm30",   "ymm31", "zmm0",  "zmm1",
57
    "zmm2",  "zmm3",  "zmm4",  "zmm5",  "zmm6",    "zmm7",  "zmm8",  "zmm9",
58
    "zmm10", "zmm11", "zmm12", "zmm13", "zmm14",   "zmm15", "zmm16", "zmm17",
59
    "zmm18", "zmm19", "zmm20", "zmm21", "zmm22",   "zmm23", "zmm24", "zmm25",
60
    "zmm26", "zmm27", "zmm28", "zmm29", "zmm30",   "zmm31", "k0",    "k1",
61
    "k2",    "k3",    "k4",    "k5",    "k6",      "k7",
62
    "cr0",   "cr2",   "cr3",   "cr4",   "cr8",
63
    "dr0",   "dr1",   "dr2",   "dr3",   "dr6",     "dr7",
64
    "bnd0",  "bnd1",  "bnd2",  "bnd3",
65
    "tmm0",  "tmm1",  "tmm2",  "tmm3",  "tmm4",    "tmm5",  "tmm6",  "tmm7",
66
};
67
68
const TargetInfo::AddlRegName AddlRegNames[] = {
69
    {{"al", "ah", "eax", "rax"}, 0},
70
    {{"bl", "bh", "ebx", "rbx"}, 3},
71
    {{"cl", "ch", "ecx", "rcx"}, 2},
72
    {{"dl", "dh", "edx", "rdx"}, 1},
73
    {{"esi", "rsi"}, 4},
74
    {{"edi", "rdi"}, 5},
75
    {{"esp", "rsp"}, 7},
76
    {{"ebp", "rbp"}, 6},
77
    {{"r8d", "r8w", "r8b"}, 38},
78
    {{"r9d", "r9w", "r9b"}, 39},
79
    {{"r10d", "r10w", "r10b"}, 40},
80
    {{"r11d", "r11w", "r11b"}, 41},
81
    {{"r12d", "r12w", "r12b"}, 42},
82
    {{"r13d", "r13w", "r13b"}, 43},
83
    {{"r14d", "r14w", "r14b"}, 44},
84
    {{"r15d", "r15w", "r15b"}, 45},
85
};
86
87
} // namespace targets
88
} // namespace clang
89
90
using namespace clang;
91
using namespace clang::targets;
92
93
5
bool X86TargetInfo::setFPMath(StringRef Name) {
94
5
  if (Name == "387") {
95
2
    FPMath = FP_387;
96
2
    return true;
97
2
  }
98
3
  if (Name == "sse") {
99
2
    FPMath = FP_SSE;
100
2
    return true;
101
2
  }
102
1
  return false;
103
3
}
104
105
bool X86TargetInfo::initFeatureMap(
106
    llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
107
144k
    const std::vector<std::string> &FeaturesVec) const {
108
  // FIXME: This *really* should not be here.
109
  // X86_64 always has SSE2.
110
144k
  if (getTriple().getArch() == llvm::Triple::x86_64)
111
123k
    setFeatureEnabled(Features, "sse2", true);
112
113
144k
  using namespace llvm::X86;
114
115
144k
  SmallVector<StringRef, 16> CPUFeatures;
116
144k
  getFeaturesForCPU(CPU, CPUFeatures);
117
144k
  for (auto &F : CPUFeatures)
118
548k
    setFeatureEnabled(Features, F, true);
119
120
144k
  std::vector<std::string> UpdatedFeaturesVec;
121
144k
  for (const auto &Feature : FeaturesVec) {
122
    // Expand general-regs-only to -x86, -mmx and -sse
123
142k
    if (Feature == "+general-regs-only") {
124
30
      UpdatedFeaturesVec.push_back("-x87");
125
30
      UpdatedFeaturesVec.push_back("-mmx");
126
30
      UpdatedFeaturesVec.push_back("-sse");
127
30
      continue;
128
30
    }
129
130
142k
    UpdatedFeaturesVec.push_back(Feature);
131
142k
  }
132
133
144k
  if (!TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec))
134
0
    return false;
135
136
  // Can't do this earlier because we need to be able to explicitly enable
137
  // or disable these features and the things that they depend upon.
138
139
  // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
140
144k
  auto I = Features.find("sse4.2");
141
144k
  if (I != Features.end() && 
I->getValue()48.3k
&&
142
144k
      
!llvm::is_contained(UpdatedFeaturesVec, "-popcnt")48.2k
)
143
48.2k
    Features["popcnt"] = true;
144
145
  // Additionally, if SSE is enabled and mmx is not explicitly disabled,
146
  // then enable MMX.
147
144k
  I = Features.find("sse");
148
144k
  if (I != Features.end() && 
I->getValue()139k
&&
149
144k
      
!llvm::is_contained(UpdatedFeaturesVec, "-mmx")139k
)
150
139k
    Features["mmx"] = true;
151
152
  // Enable xsave if avx is enabled and xsave is not explicitly disabled.
153
144k
  I = Features.find("avx");
154
144k
  if (I != Features.end() && 
I->getValue()47.9k
&&
155
144k
      
!llvm::is_contained(UpdatedFeaturesVec, "-xsave")47.8k
)
156
47.8k
    Features["xsave"] = true;
157
158
  // Enable CRC32 if SSE4.2 is enabled and CRC32 is not explicitly disabled.
159
144k
  I = Features.find("sse4.2");
160
144k
  if (I != Features.end() && 
I->getValue()48.3k
&&
161
144k
      
!llvm::is_contained(UpdatedFeaturesVec, "-crc32")48.2k
)
162
48.2k
    Features["crc32"] = true;
163
164
144k
  return true;
165
144k
}
166
167
void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
168
4.48M
                                      StringRef Name, bool Enabled) const {
169
4.48M
  if (Name == "sse4") {
170
    // We can get here via the __target__ attribute since that's not controlled
171
    // via the -msse4/-mno-sse4 command line alias. Handle this the same way
172
    // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
173
    // disabled.
174
4
    if (Enabled)
175
2
      Name = "sse4.2";
176
2
    else
177
2
      Name = "sse4.1";
178
4
  }
179
180
4.48M
  Features[Name] = Enabled;
181
4.48M
  llvm::X86::updateImpliedFeatures(Name, Enabled, Features);
182
4.48M
}
183
184
/// handleTargetFeatures - Perform initialization based on the user
185
/// configured set of features.
186
bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
187
87.2k
                                         DiagnosticsEngine &Diags) {
188
554k
  for (const auto &Feature : Features) {
189
554k
    if (Feature[0] != '+')
190
2.67k
      continue;
191
192
551k
    if (Feature == "+aes") {
193
60
      HasAES = true;
194
551k
    } else if (Feature == "+vaes") {
195
6
      HasVAES = true;
196
551k
    } else if (Feature == "+pclmul") {
197
75
      HasPCLMUL = true;
198
551k
    } else if (Feature == "+vpclmulqdq") {
199
6
      HasVPCLMULQDQ = true;
200
551k
    } else if (Feature == "+lzcnt") {
201
70
      HasLZCNT = true;
202
551k
    } else if (Feature == "+rdrnd") {
203
43
      HasRDRND = true;
204
551k
    } else if (Feature == "+fsgsbase") {
205
41
      HasFSGSBASE = true;
206
551k
    } else if (Feature == "+bmi") {
207
64
      HasBMI = true;
208
551k
    } else if (Feature == "+bmi2") {
209
43
      HasBMI2 = true;
210
551k
    } else if (Feature == "+popcnt") {
211
320
      HasPOPCNT = true;
212
550k
    } else if (Feature == "+rtm") {
213
1
      HasRTM = true;
214
550k
    } else if (Feature == "+prfchw") {
215
67
      HasPRFCHW = true;
216
550k
    } else if (Feature == "+rdseed") {
217
37
      HasRDSEED = true;
218
550k
    } else if (Feature == "+adx") {
219
36
      HasADX = true;
220
550k
    } else if (Feature == "+tbm") {
221
5
      HasTBM = true;
222
550k
    } else if (Feature == "+lwp") {
223
7
      HasLWP = true;
224
550k
    } else if (Feature == "+fma") {
225
164
      HasFMA = true;
226
550k
    } else if (Feature == "+f16c") {
227
182
      HasF16C = true;
228
550k
    } else if (Feature == "+gfni") {
229
6
      HasGFNI = true;
230
550k
    } else if (Feature == "+avx512cd") {
231
26
      HasAVX512CD = true;
232
550k
    } else if (Feature == "+avx512vpopcntdq") {
233
5
      HasAVX512VPOPCNTDQ = true;
234
550k
    } else if (Feature == "+avx512vnni") {
235
5
      HasAVX512VNNI = true;
236
550k
    } else if (Feature == "+avx512bf16") {
237
4
      HasAVX512BF16 = true;
238
550k
    } else if (Feature == "+avx512er") {
239
8
      HasAVX512ER = true;
240
550k
    } else if (Feature == "+avx512fp16") {
241
8
      HasAVX512FP16 = true;
242
8
      HasFloat16 = true;
243
550k
    } else if (Feature == "+avx512pf") {
244
7
      HasAVX512PF = true;
245
550k
    } else if (Feature == "+avx512dq") {
246
35
      HasAVX512DQ = true;
247
550k
    } else if (Feature == "+avx512bitalg") {
248
5
      HasAVX512BITALG = true;
249
550k
    } else if (Feature == "+avx512bw") {
250
47
      HasAVX512BW = true;
251
550k
    } else if (Feature == "+avx512vl") {
252
54
      HasAVX512VL = true;
253
550k
    } else if (Feature == "+avx512vbmi") {
254
6
      HasAVX512VBMI = true;
255
550k
    } else if (Feature == "+avx512vbmi2") {
256
5
      HasAVX512VBMI2 = true;
257
550k
    } else if (Feature == "+avx512ifma") {
258
6
      HasAVX512IFMA = true;
259
549k
    } else if (Feature == "+avx512vp2intersect") {
260
5
      HasAVX512VP2INTERSECT = true;
261
549k
    } else if (Feature == "+sha") {
262
10
      HasSHA = true;
263
549k
    } else if (Feature == "+shstk") {
264
6
      HasSHSTK = true;
265
549k
    } else if (Feature == "+movbe") {
266
123
      HasMOVBE = true;
267
549k
    } else if (Feature == "+sgx") {
268
13
      HasSGX = true;
269
549k
    } else if (Feature == "+cx8") {
270
87.2k
      HasCX8 = true;
271
462k
    } else if (Feature == "+cx16") {
272
17.6k
      HasCX16 = true;
273
444k
    } else if (Feature == "+fxsr") {
274
36.6k
      HasFXSR = true;
275
408k
    } else if (Feature == "+xsave") {
276
300
      HasXSAVE = true;
277
408k
    } else if (Feature == "+xsaveopt") {
278
74
      HasXSAVEOPT = true;
279
407k
    } else if (Feature == "+xsavec") {
280
33
      HasXSAVEC = true;
281
407k
    } else if (Feature == "+xsaves") {
282
33
      HasXSAVES = true;
283
407k
    } else if (Feature == "+mwaitx") {
284
10
      HasMWAITX = true;
285
407k
    } else if (Feature == "+pku") {
286
19
      HasPKU = true;
287
407k
    } else if (Feature == "+clflushopt") {
288
27
      HasCLFLUSHOPT = true;
289
407k
    } else if (Feature == "+clwb") {
290
20
      HasCLWB = true;
291
407k
    } else if (Feature == "+wbnoinvd") {
292
9
      HasWBNOINVD = true;
293
407k
    } else if (Feature == "+prefetchwt1") {
294
7
      HasPREFETCHWT1 = true;
295
407k
    } else if (Feature == "+clzero") {
296
10
      HasCLZERO = true;
297
407k
    } else if (Feature == "+cldemote") {
298
5
      HasCLDEMOTE = true;
299
407k
    } else if (Feature == "+rdpid") {
300
8
      HasRDPID = true;
301
407k
    } else if (Feature == "+kl") {
302
4
      HasKL = true;
303
407k
    } else if (Feature == "+widekl") {
304
3
      HasWIDEKL = true;
305
407k
    } else if (Feature == "+retpoline-external-thunk") {
306
0
      HasRetpolineExternalThunk = true;
307
407k
    } else if (Feature == "+sahf") {
308
17.6k
      HasLAHFSAHF = true;
309
390k
    } else if (Feature == "+waitpkg") {
310
2
      HasWAITPKG = true;
311
390k
    } else if (Feature == "+movdiri") {
312
3
      HasMOVDIRI = true;
313
390k
    } else if (Feature == "+movdir64b") {
314
3
      HasMOVDIR64B = true;
315
390k
    } else if (Feature == "+pconfig") {
316
9
      HasPCONFIG = true;
317
390k
    } else if (Feature == "+ptwrite") {
318
2
      HasPTWRITE = true;
319
390k
    } else if (Feature == "+invpcid") {
320
35
      HasINVPCID = true;
321
390k
    } else if (Feature == "+enqcmd") {
322
3
      HasENQCMD = true;
323
390k
    } else if (Feature == "+hreset") {
324
9
      HasHRESET = true;
325
390k
    } else if (Feature == "+amx-bf16") {
326
5
      HasAMXBF16 = true;
327
390k
    } else if (Feature == "+amx-int8") {
328
5
      HasAMXINT8 = true;
329
390k
    } else if (Feature == "+amx-tile") {
330
7
      HasAMXTILE = true;
331
389k
    } else if (Feature == "+avxvnni") {
332
3
      HasAVXVNNI = true;
333
389k
    } else if (Feature == "+serialize") {
334
3
      HasSERIALIZE = true;
335
389k
    } else if (Feature == "+tsxldtrk") {
336
3
      HasTSXLDTRK = true;
337
389k
    } else if (Feature == "+uintr") {
338
2
      HasUINTR = true;
339
389k
    } else if (Feature == "+crc32") {
340
321
      HasCRC32 = true;
341
389k
    } else if (Feature == "+x87") {
342
87.2k
      HasX87 = true;
343
87.2k
    }
344
345
551k
    X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
346
551k
                           .Case("+avx512f", AVX512F)
347
551k
                           .Case("+avx2", AVX2)
348
551k
                           .Case("+avx", AVX)
349
551k
                           .Case("+sse4.2", SSE42)
350
551k
                           .Case("+sse4.1", SSE41)
351
551k
                           .Case("+ssse3", SSSE3)
352
551k
                           .Case("+sse3", SSE3)
353
551k
                           .Case("+sse2", SSE2)
354
551k
                           .Case("+sse", SSE1)
355
551k
                           .Default(NoSSE);
356
551k
    SSELevel = std::max(SSELevel, Level);
357
358
551k
    MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature)
359
551k
                                      .Case("+3dnowa", AMD3DNowAthlon)
360
551k
                                      .Case("+3dnow", AMD3DNow)
361
551k
                                      .Case("+mmx", MMX)
362
551k
                                      .Default(NoMMX3DNow);
363
551k
    MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
364
365
551k
    XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
366
551k
                         .Case("+xop", XOP)
367
551k
                         .Case("+fma4", FMA4)
368
551k
                         .Case("+sse4a", SSE4A)
369
551k
                         .Default(NoXOP);
370
551k
    XOPLevel = std::max(XOPLevel, XLevel);
371
551k
  }
372
373
  // LLVM doesn't have a separate switch for fpmath, so only accept it if it
374
  // matches the selected sse level.
375
87.2k
  if ((FPMath == FP_SSE && 
SSELevel < SSE12
) ||
376
87.2k
      
(87.2k
FPMath == FP_38787.2k
&&
SSELevel >= SSE12
)) {
377
2
    Diags.Report(diag::err_target_unsupported_fpmath)
378
2
        << (FPMath == FP_SSE ? 
"sse"1
:
"387"1
);
379
2
    return false;
380
2
  }
381
382
87.2k
  SimdDefaultAlign =
383
87.2k
      hasFeature("avx512f") ? 
512139
:
hasFeature("avx")87.1k
?
256133
:
12886.9k
;
384
385
  // FIXME: We should allow long double type on 32-bits to match with GCC.
386
  // This requires backend to be able to lower f80 without x87 first.
387
87.2k
  if (!HasX87 && 
LongDoubleFormat == &llvm::APFloat::x87DoubleExtended()32
)
388
32
    HasLongDouble = false;
389
390
87.2k
  return true;
391
87.2k
}
392
393
/// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
394
/// definitions for this particular subtarget.
395
void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
396
78.6k
                                     MacroBuilder &Builder) const {
397
  // Inline assembly supports X86 flag outputs.
398
78.6k
  Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__");
399
400
78.6k
  std::string CodeModel = getTargetOpts().CodeModel;
401
78.6k
  if (CodeModel == "default")
402
63.1k
    CodeModel = "small";
403
78.6k
  Builder.defineMacro("__code_model_" + CodeModel + "__");
404
405
  // Target identification.
406
78.6k
  if (getTriple().getArch() == llvm::Triple::x86_64) {
407
63.9k
    Builder.defineMacro("__amd64__");
408
63.9k
    Builder.defineMacro("__amd64");
409
63.9k
    Builder.defineMacro("__x86_64");
410
63.9k
    Builder.defineMacro("__x86_64__");
411
63.9k
    if (getTriple().getArchName() == "x86_64h") {
412
2
      Builder.defineMacro("__x86_64h");
413
2
      Builder.defineMacro("__x86_64h__");
414
2
    }
415
63.9k
  } else {
416
14.6k
    DefineStd(Builder, "i386", Opts);
417
14.6k
  }
418
419
78.6k
  Builder.defineMacro("__SEG_GS");
420
78.6k
  Builder.defineMacro("__SEG_FS");
421
78.6k
  Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))");
422
78.6k
  Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))");
423
424
  // Subtarget options.
425
  // FIXME: We are hard-coding the tune parameters based on the CPU, but they
426
  // truly should be based on -mtune options.
427
78.6k
  using namespace llvm::X86;
428
78.6k
  switch (CPU) {
429
42.4k
  case CK_None:
430
42.4k
    break;
431
30
  case CK_i386:
432
    // The rest are coming from the i386 define above.
433
30
    Builder.defineMacro("__tune_i386__");
434
30
    break;
435
4
  case CK_i486:
436
4
  case CK_WinChipC6:
437
4
  case CK_WinChip2:
438
4
  case CK_C3:
439
4
    defineCPUMacros(Builder, "i486");
440
4
    break;
441
0
  case CK_PentiumMMX:
442
0
    Builder.defineMacro("__pentium_mmx__");
443
0
    Builder.defineMacro("__tune_pentium_mmx__");
444
0
    LLVM_FALLTHROUGH;
445
1
  case CK_i586:
446
4
  case CK_Pentium:
447
4
    defineCPUMacros(Builder, "i586");
448
4
    defineCPUMacros(Builder, "pentium");
449
4
    break;
450
2
  case CK_Pentium3:
451
5
  case CK_PentiumM:
452
5
    Builder.defineMacro("__tune_pentium3__");
453
5
    LLVM_FALLTHROUGH;
454
5
  case CK_Pentium2:
455
5
  case CK_C3_2:
456
5
    Builder.defineMacro("__tune_pentium2__");
457
5
    LLVM_FALLTHROUGH;
458
14
  case CK_PentiumPro:
459
29
  case CK_i686:
460
29
    defineCPUMacros(Builder, "i686");
461
29
    defineCPUMacros(Builder, "pentiumpro");
462
29
    break;
463
9.97k
  case CK_Pentium4:
464
9.97k
    defineCPUMacros(Builder, "pentium4");
465
9.97k
    break;
466
9
  case CK_Yonah:
467
9
  case CK_Prescott:
468
10
  case CK_Nocona:
469
10
    defineCPUMacros(Builder, "nocona");
470
10
    break;
471
173
  case CK_Core2:
472
17.1k
  case CK_Penryn:
473
17.1k
    defineCPUMacros(Builder, "core2");
474
17.1k
    break;
475
59
  case CK_Bonnell:
476
59
    defineCPUMacros(Builder, "atom");
477
59
    break;
478
2
  case CK_Silvermont:
479
2
    defineCPUMacros(Builder, "slm");
480
2
    break;
481
0
  case CK_Goldmont:
482
0
    defineCPUMacros(Builder, "goldmont");
483
0
    break;
484
0
  case CK_GoldmontPlus:
485
0
    defineCPUMacros(Builder, "goldmont_plus");
486
0
    break;
487
0
  case CK_Tremont:
488
0
    defineCPUMacros(Builder, "tremont");
489
0
    break;
490
9
  case CK_Nehalem:
491
10
  case CK_Westmere:
492
16
  case CK_SandyBridge:
493
17
  case CK_IvyBridge:
494
21
  case CK_Haswell:
495
23
  case CK_Broadwell:
496
25
  case CK_SkylakeClient:
497
39
  case CK_SkylakeServer:
498
39
  case CK_Cascadelake:
499
39
  case CK_Cooperlake:
500
40
  case CK_Cannonlake:
501
41
  case CK_IcelakeClient:
502
41
  case CK_Rocketlake:
503
42
  case CK_IcelakeServer:
504
42
  case CK_Tigerlake:
505
42
  case CK_SapphireRapids:
506
42
  case CK_Alderlake:
507
    // FIXME: Historically, we defined this legacy name, it would be nice to
508
    // remove it at some point. We've never exposed fine-grained names for
509
    // recent primary x86 CPUs, and we should keep it that way.
510
42
    defineCPUMacros(Builder, "corei7");
511
42
    break;
512
6
  case CK_KNL:
513
6
    defineCPUMacros(Builder, "knl");
514
6
    break;
515
1
  case CK_KNM:
516
1
    break;
517
0
  case CK_Lakemont:
518
0
    defineCPUMacros(Builder, "i586", /*Tuning*/false);
519
0
    defineCPUMacros(Builder, "pentium", /*Tuning*/false);
520
0
    Builder.defineMacro("__tune_lakemont__");
521
0
    break;
522
0
  case CK_K6_2:
523
0
    Builder.defineMacro("__k6_2__");
524
0
    Builder.defineMacro("__tune_k6_2__");
525
0
    LLVM_FALLTHROUGH;
526
0
  case CK_K6_3:
527
0
    if (CPU != CK_K6_2) { // In case of fallthrough
528
      // FIXME: GCC may be enabling these in cases where some other k6
529
      // architecture is specified but -m3dnow is explicitly provided. The
530
      // exact semantics need to be determined and emulated here.
531
0
      Builder.defineMacro("__k6_3__");
532
0
      Builder.defineMacro("__tune_k6_3__");
533
0
    }
534
0
    LLVM_FALLTHROUGH;
535
0
  case CK_K6:
536
0
    defineCPUMacros(Builder, "k6");
537
0
    break;
538
0
  case CK_Athlon:
539
0
  case CK_AthlonXP:
540
0
    defineCPUMacros(Builder, "athlon");
541
0
    if (SSELevel != NoSSE) {
542
0
      Builder.defineMacro("__athlon_sse__");
543
0
      Builder.defineMacro("__tune_athlon_sse__");
544
0
    }
545
0
    break;
546
4
  case CK_K8:
547
7
  case CK_K8SSE3:
548
8.90k
  case CK_x86_64:
549
8.90k
    defineCPUMacros(Builder, "k8");
550
8.90k
    break;
551
1
  case CK_x86_64_v2:
552
2
  case CK_x86_64_v3:
553
3
  case CK_x86_64_v4:
554
3
    break;
555
2
  case CK_AMDFAM10:
556
2
    defineCPUMacros(Builder, "amdfam10");
557
2
    break;
558
2
  case CK_BTVER1:
559
2
    defineCPUMacros(Builder, "btver1");
560
2
    break;
561
17
  case CK_BTVER2:
562
17
    defineCPUMacros(Builder, "btver2");
563
17
    break;
564
2
  case CK_BDVER1:
565
2
    defineCPUMacros(Builder, "bdver1");
566
2
    break;
567
2
  case CK_BDVER2:
568
2
    defineCPUMacros(Builder, "bdver2");
569
2
    break;
570
1
  case CK_BDVER3:
571
1
    defineCPUMacros(Builder, "bdver3");
572
1
    break;
573
1
  case CK_BDVER4:
574
1
    defineCPUMacros(Builder, "bdver4");
575
1
    break;
576
2
  case CK_ZNVER1:
577
2
    defineCPUMacros(Builder, "znver1");
578
2
    break;
579
3
  case CK_ZNVER2:
580
3
    defineCPUMacros(Builder, "znver2");
581
3
    break;
582
1
  case CK_ZNVER3:
583
1
    defineCPUMacros(Builder, "znver3");
584
1
    break;
585
0
  case CK_Geode:
586
0
    defineCPUMacros(Builder, "geode");
587
0
    break;
588
78.6k
  }
589
590
  // Target properties.
591
78.6k
  Builder.defineMacro("__REGISTER_PREFIX__", "");
592
593
  // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
594
  // functions in glibc header files that use FP Stack inline asm which the
595
  // backend can't deal with (PR879).
596
78.6k
  Builder.defineMacro("__NO_MATH_INLINES");
597
598
78.6k
  if (HasAES)
599
58
    Builder.defineMacro("__AES__");
600
601
78.6k
  if (HasVAES)
602
6
    Builder.defineMacro("__VAES__");
603
604
78.6k
  if (HasPCLMUL)
605
73
    Builder.defineMacro("__PCLMUL__");
606
607
78.6k
  if (HasVPCLMULQDQ)
608
6
    Builder.defineMacro("__VPCLMULQDQ__");
609
610
  // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM,
611
  // the feature flag only applies to 64-bit mode.
612
78.6k
  if (HasLAHFSAHF || 
getTriple().getArch() == llvm::Triple::x8661.3k
)
613
31.8k
    Builder.defineMacro("__LAHF_SAHF__");
614
615
78.6k
  if (HasLZCNT)
616
68
    Builder.defineMacro("__LZCNT__");
617
618
78.6k
  if (HasRDRND)
619
43
    Builder.defineMacro("__RDRND__");
620
621
78.6k
  if (HasFSGSBASE)
622
41
    Builder.defineMacro("__FSGSBASE__");
623
624
78.6k
  if (HasBMI)
625
62
    Builder.defineMacro("__BMI__");
626
627
78.6k
  if (HasBMI2)
628
43
    Builder.defineMacro("__BMI2__");
629
630
78.6k
  if (HasPOPCNT)
631
318
    Builder.defineMacro("__POPCNT__");
632
633
78.6k
  if (HasRTM)
634
1
    Builder.defineMacro("__RTM__");
635
636
78.6k
  if (HasPRFCHW)
637
65
    Builder.defineMacro("__PRFCHW__");
638
639
78.6k
  if (HasRDSEED)
640
37
    Builder.defineMacro("__RDSEED__");
641
642
78.6k
  if (HasADX)
643
36
    Builder.defineMacro("__ADX__");
644
645
78.6k
  if (HasTBM)
646
5
    Builder.defineMacro("__TBM__");
647
648
78.6k
  if (HasLWP)
649
7
    Builder.defineMacro("__LWP__");
650
651
78.6k
  if (HasMWAITX)
652
10
    Builder.defineMacro("__MWAITX__");
653
654
78.6k
  if (HasMOVBE)
655
121
    Builder.defineMacro("__MOVBE__");
656
657
78.6k
  switch (XOPLevel) {
658
14
  case XOP:
659
14
    Builder.defineMacro("__XOP__");
660
14
    LLVM_FALLTHROUGH;
661
16
  case FMA4:
662
16
    Builder.defineMacro("__FMA4__");
663
16
    LLVM_FALLTHROUGH;
664
44
  case SSE4A:
665
44
    Builder.defineMacro("__SSE4A__");
666
44
    LLVM_FALLTHROUGH;
667
78.6k
  case NoXOP:
668
78.6k
    break;
669
78.6k
  }
670
671
78.6k
  if (HasFMA)
672
164
    Builder.defineMacro("__FMA__");
673
674
78.6k
  if (HasF16C)
675
180
    Builder.defineMacro("__F16C__");
676
677
78.6k
  if (HasGFNI)
678
6
    Builder.defineMacro("__GFNI__");
679
680
78.6k
  if (HasAVX512CD)
681
26
    Builder.defineMacro("__AVX512CD__");
682
78.6k
  if (HasAVX512VPOPCNTDQ)
683
5
    Builder.defineMacro("__AVX512VPOPCNTDQ__");
684
78.6k
  if (HasAVX512VNNI)
685
5
    Builder.defineMacro("__AVX512VNNI__");
686
78.6k
  if (HasAVX512BF16)
687
4
    Builder.defineMacro("__AVX512BF16__");
688
78.6k
  if (HasAVX512ER)
689
8
    Builder.defineMacro("__AVX512ER__");
690
78.6k
  if (HasAVX512FP16)
691
8
    Builder.defineMacro("__AVX512FP16__");
692
78.6k
  if (HasAVX512PF)
693
7
    Builder.defineMacro("__AVX512PF__");
694
78.6k
  if (HasAVX512DQ)
695
35
    Builder.defineMacro("__AVX512DQ__");
696
78.6k
  if (HasAVX512BITALG)
697
5
    Builder.defineMacro("__AVX512BITALG__");
698
78.6k
  if (HasAVX512BW)
699
47
    Builder.defineMacro("__AVX512BW__");
700
78.6k
  if (HasAVX512VL)
701
54
    Builder.defineMacro("__AVX512VL__");
702
78.6k
  if (HasAVX512VBMI)
703
6
    Builder.defineMacro("__AVX512VBMI__");
704
78.6k
  if (HasAVX512VBMI2)
705
5
    Builder.defineMacro("__AVX512VBMI2__");
706
78.6k
  if (HasAVX512IFMA)
707
6
    Builder.defineMacro("__AVX512IFMA__");
708
78.6k
  if (HasAVX512VP2INTERSECT)
709
5
    Builder.defineMacro("__AVX512VP2INTERSECT__");
710
78.6k
  if (HasSHA)
711
10
    Builder.defineMacro("__SHA__");
712
713
78.6k
  if (HasFXSR)
714
36.1k
    Builder.defineMacro("__FXSR__");
715
78.6k
  if (HasXSAVE)
716
298
    Builder.defineMacro("__XSAVE__");
717
78.6k
  if (HasXSAVEOPT)
718
72
    Builder.defineMacro("__XSAVEOPT__");
719
78.6k
  if (HasXSAVEC)
720
33
    Builder.defineMacro("__XSAVEC__");
721
78.6k
  if (HasXSAVES)
722
33
    Builder.defineMacro("__XSAVES__");
723
78.6k
  if (HasPKU)
724
19
    Builder.defineMacro("__PKU__");
725
78.6k
  if (HasCLFLUSHOPT)
726
27
    Builder.defineMacro("__CLFLUSHOPT__");
727
78.6k
  if (HasCLWB)
728
20
    Builder.defineMacro("__CLWB__");
729
78.6k
  if (HasWBNOINVD)
730
9
    Builder.defineMacro("__WBNOINVD__");
731
78.6k
  if (HasSHSTK)
732
6
    Builder.defineMacro("__SHSTK__");
733
78.6k
  if (HasSGX)
734
13
    Builder.defineMacro("__SGX__");
735
78.6k
  if (HasPREFETCHWT1)
736
7
    Builder.defineMacro("__PREFETCHWT1__");
737
78.6k
  if (HasCLZERO)
738
10
    Builder.defineMacro("__CLZERO__");
739
78.6k
  if (HasKL)
740
4
    Builder.defineMacro("__KL__");
741
78.6k
  if (HasWIDEKL)
742
3
    Builder.defineMacro("__WIDEKL__");
743
78.6k
  if (HasRDPID)
744
8
    Builder.defineMacro("__RDPID__");
745
78.6k
  if (HasCLDEMOTE)
746
5
    Builder.defineMacro("__CLDEMOTE__");
747
78.6k
  if (HasWAITPKG)
748
2
    Builder.defineMacro("__WAITPKG__");
749
78.6k
  if (HasMOVDIRI)
750
3
    Builder.defineMacro("__MOVDIRI__");
751
78.6k
  if (HasMOVDIR64B)
752
3
    Builder.defineMacro("__MOVDIR64B__");
753
78.6k
  if (HasPCONFIG)
754
9
    Builder.defineMacro("__PCONFIG__");
755
78.6k
  if (HasPTWRITE)
756
2
    Builder.defineMacro("__PTWRITE__");
757
78.6k
  if (HasINVPCID)
758
35
    Builder.defineMacro("__INVPCID__");
759
78.6k
  if (HasENQCMD)
760
3
    Builder.defineMacro("__ENQCMD__");
761
78.6k
  if (HasHRESET)
762
9
    Builder.defineMacro("__HRESET__");
763
78.6k
  if (HasAMXTILE)
764
7
    Builder.defineMacro("__AMXTILE__");
765
78.6k
  if (HasAMXINT8)
766
5
    Builder.defineMacro("__AMXINT8__");
767
78.6k
  if (HasAMXBF16)
768
5
    Builder.defineMacro("__AMXBF16__");
769
78.6k
  if (HasAVXVNNI)
770
3
    Builder.defineMacro("__AVXVNNI__");
771
78.6k
  if (HasSERIALIZE)
772
3
    Builder.defineMacro("__SERIALIZE__");
773
78.6k
  if (HasTSXLDTRK)
774
3
    Builder.defineMacro("__TSXLDTRK__");
775
78.6k
  if (HasUINTR)
776
2
    Builder.defineMacro("__UINTR__");
777
78.6k
  if (HasCRC32)
778
319
    Builder.defineMacro("__CRC32__");
779
780
  // Each case falls through to the previous one here.
781
78.6k
  switch (SSELevel) {
782
139
  case AVX512F:
783
139
    Builder.defineMacro("__AVX512F__");
784
139
    LLVM_FALLTHROUGH;
785
172
  case AVX2:
786
172
    Builder.defineMacro("__AVX2__");
787
172
    LLVM_FALLTHROUGH;
788
270
  case AVX:
789
270
    Builder.defineMacro("__AVX__");
790
270
    LLVM_FALLTHROUGH;
791
307
  case SSE42:
792
307
    Builder.defineMacro("__SSE4_2__");
793
307
    LLVM_FALLTHROUGH;
794
17.2k
  case SSE41:
795
17.2k
    Builder.defineMacro("__SSE4_1__");
796
17.2k
    LLVM_FALLTHROUGH;
797
17.4k
  case SSSE3:
798
17.4k
    Builder.defineMacro("__SSSE3__");
799
17.4k
    LLVM_FALLTHROUGH;
800
17.5k
  case SSE3:
801
17.5k
    Builder.defineMacro("__SSE3__");
802
17.5k
    LLVM_FALLTHROUGH;
803
74.0k
  case SSE2:
804
74.0k
    Builder.defineMacro("__SSE2__");
805
74.0k
    Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
806
74.0k
    LLVM_FALLTHROUGH;
807
74.0k
  case SSE1:
808
74.0k
    Builder.defineMacro("__SSE__");
809
74.0k
    Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
810
74.0k
    LLVM_FALLTHROUGH;
811
78.6k
  case NoSSE:
812
78.6k
    break;
813
78.6k
  }
814
815
78.6k
  if (Opts.MicrosoftExt && 
getTriple().getArch() == llvm::Triple::x8611.1k
) {
816
346
    switch (SSELevel) {
817
2
    case AVX512F:
818
4
    case AVX2:
819
6
    case AVX:
820
6
    case SSE42:
821
6
    case SSE41:
822
6
    case SSSE3:
823
6
    case SSE3:
824
59
    case SSE2:
825
59
      Builder.defineMacro("_M_IX86_FP", Twine(2));
826
59
      break;
827
2
    case SSE1:
828
2
      Builder.defineMacro("_M_IX86_FP", Twine(1));
829
2
      break;
830
285
    default:
831
285
      Builder.defineMacro("_M_IX86_FP", Twine(0));
832
285
      break;
833
346
    }
834
346
  }
835
836
  // Each case falls through to the previous one here.
837
78.6k
  switch (MMX3DNowLevel) {
838
11
  case AMD3DNowAthlon:
839
11
    Builder.defineMacro("__3dNOW_A__");
840
11
    LLVM_FALLTHROUGH;
841
13
  case AMD3DNow:
842
13
    Builder.defineMacro("__3dNOW__");
843
13
    LLVM_FALLTHROUGH;
844
74.1k
  case MMX:
845
74.1k
    Builder.defineMacro("__MMX__");
846
74.1k
    LLVM_FALLTHROUGH;
847
78.6k
  case NoMMX3DNow:
848
78.6k
    break;
849
78.6k
  }
850
851
78.6k
  if (CPU >= CK_i486 || 
CPU == CK_None42.4k
) {
852
78.6k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
853
78.6k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
854
78.6k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
855
78.6k
  }
856
78.6k
  if (HasCX8)
857
78.6k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
858
78.6k
  if (HasCX16 && 
getTriple().getArch() == llvm::Triple::x86_6417.2k
)
859
17.2k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
860
861
78.6k
  if (HasFloat128)
862
4.05k
    Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
863
78.6k
}
864
865
1.53M
bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
866
1.53M
  return llvm::StringSwitch<bool>(Name)
867
1.53M
      .Case("3dnow", true)
868
1.53M
      .Case("3dnowa", true)
869
1.53M
      .Case("adx", true)
870
1.53M
      .Case("aes", true)
871
1.53M
      .Case("amx-bf16", true)
872
1.53M
      .Case("amx-int8", true)
873
1.53M
      .Case("amx-tile", true)
874
1.53M
      .Case("avx", true)
875
1.53M
      .Case("avx2", true)
876
1.53M
      .Case("avx512f", true)
877
1.53M
      .Case("avx512cd", true)
878
1.53M
      .Case("avx512vpopcntdq", true)
879
1.53M
      .Case("avx512vnni", true)
880
1.53M
      .Case("avx512bf16", true)
881
1.53M
      .Case("avx512er", true)
882
1.53M
      .Case("avx512fp16", true)
883
1.53M
      .Case("avx512pf", true)
884
1.53M
      .Case("avx512dq", true)
885
1.53M
      .Case("avx512bitalg", true)
886
1.53M
      .Case("avx512bw", true)
887
1.53M
      .Case("avx512vl", true)
888
1.53M
      .Case("avx512vbmi", true)
889
1.53M
      .Case("avx512vbmi2", true)
890
1.53M
      .Case("avx512ifma", true)
891
1.53M
      .Case("avx512vp2intersect", true)
892
1.53M
      .Case("avxvnni", true)
893
1.53M
      .Case("bmi", true)
894
1.53M
      .Case("bmi2", true)
895
1.53M
      .Case("cldemote", true)
896
1.53M
      .Case("clflushopt", true)
897
1.53M
      .Case("clwb", true)
898
1.53M
      .Case("clzero", true)
899
1.53M
      .Case("crc32", true)
900
1.53M
      .Case("cx16", true)
901
1.53M
      .Case("enqcmd", true)
902
1.53M
      .Case("f16c", true)
903
1.53M
      .Case("fma", true)
904
1.53M
      .Case("fma4", true)
905
1.53M
      .Case("fsgsbase", true)
906
1.53M
      .Case("fxsr", true)
907
1.53M
      .Case("general-regs-only", true)
908
1.53M
      .Case("gfni", true)
909
1.53M
      .Case("hreset", true)
910
1.53M
      .Case("invpcid", true)
911
1.53M
      .Case("kl", true)
912
1.53M
      .Case("widekl", true)
913
1.53M
      .Case("lwp", true)
914
1.53M
      .Case("lzcnt", true)
915
1.53M
      .Case("mmx", true)
916
1.53M
      .Case("movbe", true)
917
1.53M
      .Case("movdiri", true)
918
1.53M
      .Case("movdir64b", true)
919
1.53M
      .Case("mwaitx", true)
920
1.53M
      .Case("pclmul", true)
921
1.53M
      .Case("pconfig", true)
922
1.53M
      .Case("pku", true)
923
1.53M
      .Case("popcnt", true)
924
1.53M
      .Case("prefetchwt1", true)
925
1.53M
      .Case("prfchw", true)
926
1.53M
      .Case("ptwrite", true)
927
1.53M
      .Case("rdpid", true)
928
1.53M
      .Case("rdrnd", true)
929
1.53M
      .Case("rdseed", true)
930
1.53M
      .Case("rtm", true)
931
1.53M
      .Case("sahf", true)
932
1.53M
      .Case("serialize", true)
933
1.53M
      .Case("sgx", true)
934
1.53M
      .Case("sha", true)
935
1.53M
      .Case("shstk", true)
936
1.53M
      .Case("sse", true)
937
1.53M
      .Case("sse2", true)
938
1.53M
      .Case("sse3", true)
939
1.53M
      .Case("ssse3", true)
940
1.53M
      .Case("sse4", true)
941
1.53M
      .Case("sse4.1", true)
942
1.53M
      .Case("sse4.2", true)
943
1.53M
      .Case("sse4a", true)
944
1.53M
      .Case("tbm", true)
945
1.53M
      .Case("tsxldtrk", true)
946
1.53M
      .Case("uintr", true)
947
1.53M
      .Case("vaes", true)
948
1.53M
      .Case("vpclmulqdq", true)
949
1.53M
      .Case("wbnoinvd", true)
950
1.53M
      .Case("waitpkg", true)
951
1.53M
      .Case("x87", true)
952
1.53M
      .Case("xop", true)
953
1.53M
      .Case("xsave", true)
954
1.53M
      .Case("xsavec", true)
955
1.53M
      .Case("xsaves", true)
956
1.53M
      .Case("xsaveopt", true)
957
1.53M
      .Default(false);
958
1.53M
}
959
960
476k
bool X86TargetInfo::hasFeature(StringRef Feature) const {
961
476k
  return llvm::StringSwitch<bool>(Feature)
962
476k
      .Case("adx", HasADX)
963
476k
      .Case("aes", HasAES)
964
476k
      .Case("amx-bf16", HasAMXBF16)
965
476k
      .Case("amx-int8", HasAMXINT8)
966
476k
      .Case("amx-tile", HasAMXTILE)
967
476k
      .Case("avxvnni", HasAVXVNNI)
968
476k
      .Case("avx", SSELevel >= AVX)
969
476k
      .Case("avx2", SSELevel >= AVX2)
970
476k
      .Case("avx512f", SSELevel >= AVX512F)
971
476k
      .Case("avx512cd", HasAVX512CD)
972
476k
      .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
973
476k
      .Case("avx512vnni", HasAVX512VNNI)
974
476k
      .Case("avx512bf16", HasAVX512BF16)
975
476k
      .Case("avx512er", HasAVX512ER)
976
476k
      .Case("avx512fp16", HasAVX512FP16)
977
476k
      .Case("avx512pf", HasAVX512PF)
978
476k
      .Case("avx512dq", HasAVX512DQ)
979
476k
      .Case("avx512bitalg", HasAVX512BITALG)
980
476k
      .Case("avx512bw", HasAVX512BW)
981
476k
      .Case("avx512vl", HasAVX512VL)
982
476k
      .Case("avx512vbmi", HasAVX512VBMI)
983
476k
      .Case("avx512vbmi2", HasAVX512VBMI2)
984
476k
      .Case("avx512ifma", HasAVX512IFMA)
985
476k
      .Case("avx512vp2intersect", HasAVX512VP2INTERSECT)
986
476k
      .Case("bmi", HasBMI)
987
476k
      .Case("bmi2", HasBMI2)
988
476k
      .Case("cldemote", HasCLDEMOTE)
989
476k
      .Case("clflushopt", HasCLFLUSHOPT)
990
476k
      .Case("clwb", HasCLWB)
991
476k
      .Case("clzero", HasCLZERO)
992
476k
      .Case("crc32", HasCRC32)
993
476k
      .Case("cx8", HasCX8)
994
476k
      .Case("cx16", HasCX16)
995
476k
      .Case("enqcmd", HasENQCMD)
996
476k
      .Case("f16c", HasF16C)
997
476k
      .Case("fma", HasFMA)
998
476k
      .Case("fma4", XOPLevel >= FMA4)
999
476k
      .Case("fsgsbase", HasFSGSBASE)
1000
476k
      .Case("fxsr", HasFXSR)
1001
476k
      .Case("gfni", HasGFNI)
1002
476k
      .Case("hreset", HasHRESET)
1003
476k
      .Case("invpcid", HasINVPCID)
1004
476k
      .Case("kl", HasKL)
1005
476k
      .Case("widekl", HasWIDEKL)
1006
476k
      .Case("lwp", HasLWP)
1007
476k
      .Case("lzcnt", HasLZCNT)
1008
476k
      .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
1009
476k
      .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
1010
476k
      .Case("mmx", MMX3DNowLevel >= MMX)
1011
476k
      .Case("movbe", HasMOVBE)
1012
476k
      .Case("movdiri", HasMOVDIRI)
1013
476k
      .Case("movdir64b", HasMOVDIR64B)
1014
476k
      .Case("mwaitx", HasMWAITX)
1015
476k
      .Case("pclmul", HasPCLMUL)
1016
476k
      .Case("pconfig", HasPCONFIG)
1017
476k
      .Case("pku", HasPKU)
1018
476k
      .Case("popcnt", HasPOPCNT)
1019
476k
      .Case("prefetchwt1", HasPREFETCHWT1)
1020
476k
      .Case("prfchw", HasPRFCHW)
1021
476k
      .Case("ptwrite", HasPTWRITE)
1022
476k
      .Case("rdpid", HasRDPID)
1023
476k
      .Case("rdrnd", HasRDRND)
1024
476k
      .Case("rdseed", HasRDSEED)
1025
476k
      .Case("retpoline-external-thunk", HasRetpolineExternalThunk)
1026
476k
      .Case("rtm", HasRTM)
1027
476k
      .Case("sahf", HasLAHFSAHF)
1028
476k
      .Case("serialize", HasSERIALIZE)
1029
476k
      .Case("sgx", HasSGX)
1030
476k
      .Case("sha", HasSHA)
1031
476k
      .Case("shstk", HasSHSTK)
1032
476k
      .Case("sse", SSELevel >= SSE1)
1033
476k
      .Case("sse2", SSELevel >= SSE2)
1034
476k
      .Case("sse3", SSELevel >= SSE3)
1035
476k
      .Case("ssse3", SSELevel >= SSSE3)
1036
476k
      .Case("sse4.1", SSELevel >= SSE41)
1037
476k
      .Case("sse4.2", SSELevel >= SSE42)
1038
476k
      .Case("sse4a", XOPLevel >= SSE4A)
1039
476k
      .Case("tbm", HasTBM)
1040
476k
      .Case("tsxldtrk", HasTSXLDTRK)
1041
476k
      .Case("uintr", HasUINTR)
1042
476k
      .Case("vaes", HasVAES)
1043
476k
      .Case("vpclmulqdq", HasVPCLMULQDQ)
1044
476k
      .Case("wbnoinvd", HasWBNOINVD)
1045
476k
      .Case("waitpkg", HasWAITPKG)
1046
476k
      .Case("x86", true)
1047
476k
      .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
1048
476k
      .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
1049
476k
      .Case("x87", HasX87)
1050
476k
      .Case("xop", XOPLevel >= XOP)
1051
476k
      .Case("xsave", HasXSAVE)
1052
476k
      .Case("xsavec", HasXSAVEC)
1053
476k
      .Case("xsaves", HasXSAVES)
1054
476k
      .Case("xsaveopt", HasXSAVEOPT)
1055
476k
      .Default(false);
1056
476k
}
1057
1058
// We can't use a generic validation scheme for the features accepted here
1059
// versus subtarget features accepted in the target attribute because the
1060
// bitfield structure that's initialized in the runtime only supports the
1061
// below currently rather than the full range of subtarget features. (See
1062
// X86TargetInfo::hasFeature for a somewhat comprehensive list).
1063
1.06k
bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
1064
1.06k
  return llvm::StringSwitch<bool>(FeatureStr)
1065
40.3k
#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) .Case(STR, true)
1066
1.06k
#include "llvm/Support/X86TargetParser.def"
1067
1.06k
      .Default(false);
1068
1.06k
}
1069
1070
179
static llvm::X86::ProcessorFeatures getFeature(StringRef Name) {
1071
179
  return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name)
1072
179
#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY)                                \
1073
6.80k
  .Case(STR, llvm::X86::FEATURE_##ENUM)
1074
1075
179
#include "llvm/Support/X86TargetParser.def"
1076
179
      ;
1077
  // Note, this function should only be used after ensuring the value is
1078
  // correct, so it asserts if the value is out of range.
1079
179
}
1080
1081
467
unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const {
1082
  // Valid CPUs have a 'key feature' that compares just better than its key
1083
  // feature.
1084
467
  using namespace llvm::X86;
1085
467
  CPUKind Kind = parseArchX86(Name);
1086
467
  if (Kind != CK_None) {
1087
288
    ProcessorFeatures KeyFeature = getKeyFeature(Kind);
1088
288
    return (getFeaturePriority(KeyFeature) << 1) + 1;
1089
288
  }
1090
1091
  // Now we know we have a feature, so get its priority and shift it a few so
1092
  // that we have sufficient room for the CPUs (above).
1093
179
  return getFeaturePriority(getFeature(Name)) << 1;
1094
467
}
1095
1096
263
bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const {
1097
263
  return llvm::StringSwitch<bool>(Name)
1098
7.36k
#define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, true)
1099
1.57k
#define CPU_SPECIFIC_ALIAS(NEW_NAME, TUNE_NAME, NAME) .Case(NEW_NAME, true)
1100
263
#include "llvm/Support/X86TargetParser.def"
1101
263
      .Default(false);
1102
263
}
1103
1104
546
static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) {
1105
546
  return llvm::StringSwitch<StringRef>(Name)
1106
3.27k
#define CPU_SPECIFIC_ALIAS(NEW_NAME, TUNE_NAME, NAME) .Case(NEW_NAME, NAME)
1107
546
#include "llvm/Support/X86TargetParser.def"
1108
546
      .Default(Name);
1109
546
}
1110
1111
354
char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const {
1112
354
  return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name))
1113
9.91k
#define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, MANGLING)
1114
354
#include "llvm/Support/X86TargetParser.def"
1115
354
      .Default(0);
1116
354
}
1117
1118
void X86TargetInfo::getCPUSpecificCPUDispatchFeatures(
1119
192
    StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const {
1120
192
  StringRef WholeList =
1121
192
      llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name))
1122
5.37k
#define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, FEATURES)
1123
192
#include "llvm/Support/X86TargetParser.def"
1124
192
          .Default("");
1125
192
  WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false);
1126
192
}
1127
1128
92
StringRef X86TargetInfo::getCPUSpecificTuneName(StringRef Name) const {
1129
92
  return llvm::StringSwitch<StringRef>(Name)
1130
2.57k
#define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, TUNE_NAME)
1131
552
#define CPU_SPECIFIC_ALIAS(NEW_NAME, TUNE_NAME, NAME) .Case(NEW_NAME, TUNE_NAME)
1132
92
#include "llvm/Support/X86TargetParser.def"
1133
92
      .Default("");
1134
92
}
1135
1136
// We can't use a generic validation scheme for the cpus accepted here
1137
// versus subtarget cpus accepted in the target attribute because the
1138
// variables intitialized by the runtime only support the below currently
1139
// rather than the full range of cpus.
1140
194
bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
1141
194
  return llvm::StringSwitch<bool>(FeatureStr)
1142
388
#define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
1143
776
#define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true)
1144
2.91k
#define X86_CPU_TYPE(ENUM, STR) .Case(STR, true)
1145
5.23k
#define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true)
1146
194
#include "llvm/Support/X86TargetParser.def"
1147
194
      .Default(false);
1148
194
}
1149
1150
87
static unsigned matchAsmCCConstraint(const char *&Name) {
1151
87
  auto RV = llvm::StringSwitch<unsigned>(Name)
1152
87
                .Case("@cca", 4)
1153
87
                .Case("@ccae", 5)
1154
87
                .Case("@ccb", 4)
1155
87
                .Case("@ccbe", 5)
1156
87
                .Case("@ccc", 4)
1157
87
                .Case("@cce", 4)
1158
87
                .Case("@ccz", 4)
1159
87
                .Case("@ccg", 4)
1160
87
                .Case("@ccge", 5)
1161
87
                .Case("@ccl", 4)
1162
87
                .Case("@ccle", 5)
1163
87
                .Case("@ccna", 5)
1164
87
                .Case("@ccnae", 6)
1165
87
                .Case("@ccnb", 5)
1166
87
                .Case("@ccnbe", 6)
1167
87
                .Case("@ccnc", 5)
1168
87
                .Case("@ccne", 5)
1169
87
                .Case("@ccnz", 5)
1170
87
                .Case("@ccng", 5)
1171
87
                .Case("@ccnge", 6)
1172
87
                .Case("@ccnl", 5)
1173
87
                .Case("@ccnle", 6)
1174
87
                .Case("@ccno", 5)
1175
87
                .Case("@ccnp", 5)
1176
87
                .Case("@ccns", 5)
1177
87
                .Case("@cco", 4)
1178
87
                .Case("@ccp", 4)
1179
87
                .Case("@ccs", 4)
1180
87
                .Default(0);
1181
87
  return RV;
1182
87
}
1183
1184
bool X86TargetInfo::validateAsmConstraint(
1185
11.4k
    const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1186
11.4k
  switch (*Name) {
1187
2
  default:
1188
2
    return false;
1189
  // Constant constraints.
1190
9
  case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1191
            // instructions.
1192
17
  case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1193
            // x86_64 instructions.
1194
17
  case 's':
1195
17
    Info.setRequiresImmediate();
1196
17
    return true;
1197
28
  case 'I':
1198
28
    Info.setRequiresImmediate(0, 31);
1199
28
    return true;
1200
14
  case 'J':
1201
14
    Info.setRequiresImmediate(0, 63);
1202
14
    return true;
1203
14
  case 'K':
1204
14
    Info.setRequiresImmediate(-128, 127);
1205
14
    return true;
1206
30
  case 'L':
1207
30
    Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1208
30
    return true;
1209
14
  case 'M':
1210
14
    Info.setRequiresImmediate(0, 3);
1211
14
    return true;
1212
16
  case 'N':
1213
16
    Info.setRequiresImmediate(0, 255);
1214
16
    return true;
1215
6
  case 'O':
1216
6
    Info.setRequiresImmediate(0, 127);
1217
6
    return true;
1218
  // Register constraints.
1219
52
  case 'Y': // 'Y' is the first character for several 2-character constraints.
1220
    // Shift the pointer to the second character of the constraint.
1221
52
    Name++;
1222
52
    switch (*Name) {
1223
0
    default:
1224
0
      return false;
1225
20
    case 'z': // First SSE register.
1226
26
    case '2':
1227
32
    case 't': // Any SSE register, when SSE2 is enabled.
1228
42
    case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1229
44
    case 'm': // Any MMX register, when inter-unit moves enabled.
1230
52
    case 'k': // AVX512 arch mask registers: k1-k7.
1231
52
      Info.setAllowsRegister();
1232
52
      return true;
1233
52
    }
1234
3
  case 'f': // Any x87 floating point stack register.
1235
    // Constraint 'f' cannot be used for output operands.
1236
3
    if (Info.ConstraintStr[0] == '=')
1237
1
      return false;
1238
2
    Info.setAllowsRegister();
1239
2
    return true;
1240
2.97k
  case 'a': // eax.
1241
5.42k
  case 'b': // ebx.
1242
8.05k
  case 'c': // ecx.
1243
10.5k
  case 'd': // edx.
1244
10.6k
  case 'S': // esi.
1245
10.8k
  case 'D': // edi.
1246
10.8k
  case 'A': // edx:eax.
1247
10.8k
  case 't': // Top of floating point stack.
1248
10.8k
  case 'u': // Second from top of floating point stack.
1249
10.8k
  case 'q': // Any register accessible as [r]l: a, b, c, and d.
1250
10.8k
  case 'y': // Any MMX register.
1251
10.9k
  case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1252
11.0k
  case 'x': // Any SSE register.
1253
11.0k
  case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0
1254
            // for intermideate k reg operations).
1255
11.1k
  case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1256
11.1k
  case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1257
11.1k
  case 'l': // "Index" registers: any general register that can be used as an
1258
            // index in a base+index memory access.
1259
11.1k
    Info.setAllowsRegister();
1260
11.1k
    return true;
1261
  // Floating point constant constraints.
1262
8
  case 'C': // SSE floating point constant.
1263
16
  case 'G': // x87 floating point constant.
1264
16
    return true;
1265
58
  case '@':
1266
    // CC condition changes.
1267
58
    if (auto Len = matchAsmCCConstraint(Name)) {
1268
58
      Name += Len - 1;
1269
58
      Info.setAllowsRegister();
1270
58
      return true;
1271
58
    }
1272
0
    return false;
1273
11.4k
  }
1274
11.4k
}
1275
1276
// Below is based on the following information:
1277
// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1278
// |           Processor Name           | Cache Line Size (Bytes) |                                                                            Source                                                                            |
1279
// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1280
// | i386                               |                      64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf                                          |
1281
// | i486                               |                      16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) |
1282
// | i586/Pentium MMX                   |                      32 | https://www.7-cpu.com/cpu/P-MMX.html                                                                                                                         |
1283
// | i686/Pentium                       |                      32 | https://www.7-cpu.com/cpu/P6.html                                                                                                                            |
1284
// | Netburst/Pentium4                  |                      64 | https://www.7-cpu.com/cpu/P4-180.html                                                                                                                        |
1285
// | Atom                               |                      64 | https://www.7-cpu.com/cpu/Atom.html                                                                                                                          |
1286
// | Westmere                           |                      64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture"                                                             |
1287
// | Sandy Bridge                       |                      64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html                                                                    |
1288
// | Ivy Bridge                         |                      64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html                                                      |
1289
// | Haswell                            |                      64 | https://www.7-cpu.com/cpu/Haswell.html                                                                                                                       |
1290
// | Boadwell                           |                      64 | https://www.7-cpu.com/cpu/Broadwell.html                                                                                                                     |
1291
// | Skylake (including skylake-avx512) |                      64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy"                                                                       |
1292
// | Cascade Lake                       |                      64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy"                                                                  |
1293
// | Skylake                            |                      64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy"                                                                           |
1294
// | Ice Lake                           |                      64 | https://www.7-cpu.com/cpu/Ice_Lake.html                                                                                                                      |
1295
// | Knights Landing                    |                      64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" |
1296
// | Knights Mill                       |                      64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache "       |
1297
// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1298
0
Optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const {
1299
0
  using namespace llvm::X86;
1300
0
  switch (CPU) {
1301
    // i386
1302
0
    case CK_i386:
1303
    // i486
1304
0
    case CK_i486:
1305
0
    case CK_WinChipC6:
1306
0
    case CK_WinChip2:
1307
0
    case CK_C3:
1308
    // Lakemont
1309
0
    case CK_Lakemont:
1310
0
      return 16;
1311
1312
    // i586
1313
0
    case CK_i586:
1314
0
    case CK_Pentium:
1315
0
    case CK_PentiumMMX:
1316
    // i686
1317
0
    case CK_PentiumPro:
1318
0
    case CK_i686:
1319
0
    case CK_Pentium2:
1320
0
    case CK_Pentium3:
1321
0
    case CK_PentiumM:
1322
0
    case CK_C3_2:
1323
    // K6
1324
0
    case CK_K6:
1325
0
    case CK_K6_2:
1326
0
    case CK_K6_3:
1327
    // Geode
1328
0
    case CK_Geode:
1329
0
      return 32;
1330
1331
    // Netburst
1332
0
    case CK_Pentium4:
1333
0
    case CK_Prescott:
1334
0
    case CK_Nocona:
1335
    // Atom
1336
0
    case CK_Bonnell:
1337
0
    case CK_Silvermont:
1338
0
    case CK_Goldmont:
1339
0
    case CK_GoldmontPlus:
1340
0
    case CK_Tremont:
1341
1342
0
    case CK_Westmere:
1343
0
    case CK_SandyBridge:
1344
0
    case CK_IvyBridge:
1345
0
    case CK_Haswell:
1346
0
    case CK_Broadwell:
1347
0
    case CK_SkylakeClient:
1348
0
    case CK_SkylakeServer:
1349
0
    case CK_Cascadelake:
1350
0
    case CK_Nehalem:
1351
0
    case CK_Cooperlake:
1352
0
    case CK_Cannonlake:
1353
0
    case CK_Tigerlake:
1354
0
    case CK_SapphireRapids:
1355
0
    case CK_IcelakeClient:
1356
0
    case CK_Rocketlake:
1357
0
    case CK_IcelakeServer:
1358
0
    case CK_Alderlake:
1359
0
    case CK_KNL:
1360
0
    case CK_KNM:
1361
    // K7
1362
0
    case CK_Athlon:
1363
0
    case CK_AthlonXP:
1364
    // K8
1365
0
    case CK_K8:
1366
0
    case CK_K8SSE3:
1367
0
    case CK_AMDFAM10:
1368
    // Bobcat
1369
0
    case CK_BTVER1:
1370
0
    case CK_BTVER2:
1371
    // Bulldozer
1372
0
    case CK_BDVER1:
1373
0
    case CK_BDVER2:
1374
0
    case CK_BDVER3:
1375
0
    case CK_BDVER4:
1376
    // Zen
1377
0
    case CK_ZNVER1:
1378
0
    case CK_ZNVER2:
1379
0
    case CK_ZNVER3:
1380
    // Deprecated
1381
0
    case CK_x86_64:
1382
0
    case CK_x86_64_v2:
1383
0
    case CK_x86_64_v3:
1384
0
    case CK_x86_64_v4:
1385
0
    case CK_Yonah:
1386
0
    case CK_Penryn:
1387
0
    case CK_Core2:
1388
0
      return 64;
1389
1390
    // The following currently have unknown cache line sizes (but they are probably all 64):
1391
    // Core
1392
0
    case CK_None:
1393
0
      return None;
1394
0
  }
1395
0
  llvm_unreachable("Unknown CPU kind");
1396
0
}
1397
1398
bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap,
1399
                                       StringRef Constraint,
1400
6.05k
                                       unsigned Size) const {
1401
  // Strip off constraint modifiers.
1402
12.1k
  while (Constraint[0] == '=' || 
Constraint[0] == '+'6.63k
||
Constraint[0] == '&'6.06k
)
1403
6.06k
    Constraint = Constraint.substr(1);
1404
1405
6.05k
  return validateOperandSize(FeatureMap, Constraint, Size);
1406
6.05k
}
1407
1408
bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap,
1409
                                      StringRef Constraint,
1410
6.33k
                                      unsigned Size) const {
1411
6.33k
  return validateOperandSize(FeatureMap, Constraint, Size);
1412
6.33k
}
1413
1414
bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap,
1415
                                        StringRef Constraint,
1416
9.38k
                                        unsigned Size) const {
1417
9.38k
  switch (Constraint[0]) {
1418
9.21k
  default:
1419
9.21k
    break;
1420
9.21k
  case 'k':
1421
  // Registers k0-k7 (AVX512) size limit is 64 bit.
1422
30
  case 'y':
1423
30
    return Size <= 64;
1424
2
  case 'f':
1425
9
  case 't':
1426
14
  case 'u':
1427
14
    return Size <= 128;
1428
26
  case 'Y':
1429
    // 'Y' is the first character for several 2-character constraints.
1430
26
    switch (Constraint[1]) {
1431
0
    default:
1432
0
      return false;
1433
1
    case 'm':
1434
      // 'Ym' is synonymous with 'y'.
1435
5
    case 'k':
1436
5
      return Size <= 64;
1437
10
    case 'z':
1438
      // XMM0/YMM/ZMM0
1439
10
      if (hasFeatureEnabled(FeatureMap, "avx512f"))
1440
        // ZMM0 can be used if target supports AVX512F.
1441
7
        return Size <= 512U;
1442
3
      else if (hasFeatureEnabled(FeatureMap, "avx"))
1443
        // YMM0 can be used if target supports AVX.
1444
2
        return Size <= 256U;
1445
1
      else if (hasFeatureEnabled(FeatureMap, "sse"))
1446
1
        return Size <= 128U;
1447
0
      return false;
1448
5
    case 'i':
1449
8
    case 't':
1450
11
    case '2':
1451
      // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1452
11
      if (SSELevel < SSE2)
1453
0
        return false;
1454
11
      break;
1455
26
    }
1456
11
    break;
1457
30
  case 'v':
1458
101
  case 'x':
1459
101
    if (hasFeatureEnabled(FeatureMap, "avx512f"))
1460
      // 512-bit zmm registers can be used if target supports AVX512F.
1461
46
      return Size <= 512U;
1462
55
    else if (hasFeatureEnabled(FeatureMap, "avx"))
1463
      // 256-bit ymm registers can be used if target supports AVX.
1464
27
      return Size <= 256U;
1465
28
    return Size <= 128U;
1466
1467
9.38k
  }
1468
1469
9.22k
  return true;
1470
9.38k
}
1471
1472
1.99k
std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
1473
1.99k
  switch (*Constraint) {
1474
29
  case '@':
1475
29
    if (auto Len = matchAsmCCConstraint(Constraint)) {
1476
29
      std::string Converted = "{" + std::string(Constraint, Len) + "}";
1477
29
      Constraint += Len - 1;
1478
29
      return Converted;
1479
29
    }
1480
0
    return std::string(1, *Constraint);
1481
135
  case 'a':
1482
135
    return std::string("{ax}");
1483
84
  case 'b':
1484
84
    return std::string("{bx}");
1485
121
  case 'c':
1486
121
    return std::string("{cx}");
1487
84
  case 'd':
1488
84
    return std::string("{dx}");
1489
29
  case 'S':
1490
29
    return std::string("{si}");
1491
51
  case 'D':
1492
51
    return std::string("{di}");
1493
5
  case 'p': // Keep 'p' constraint (address).
1494
5
    return std::string("p");
1495
3
  case 't': // top of floating point stack.
1496
3
    return std::string("{st}");
1497
1
  case 'u':                        // second from top of floating point stack.
1498
1
    return std::string("{st(1)}"); // second from top of floating point stack.
1499
26
  case 'Y':
1500
26
    switch (Constraint[1]) {
1501
0
    default:
1502
      // Break from inner switch and fall through (copy single char),
1503
      // continue parsing after copying the current constraint into
1504
      // the return string.
1505
0
      break;
1506
4
    case 'k':
1507
5
    case 'm':
1508
10
    case 'i':
1509
13
    case 't':
1510
23
    case 'z':
1511
26
    case '2':
1512
      // "^" hints llvm that this is a 2 letter constraint.
1513
      // "Constraint++" is used to promote the string iterator
1514
      // to the next constraint.
1515
26
      return std::string("^") + std::string(Constraint++, 2);
1516
26
    }
1517
26
    
LLVM_FALLTHROUGH0
;0
1518
1.42k
  default:
1519
1.42k
    return std::string(1, *Constraint);
1520
1.99k
  }
1521
1.99k
}
1522
1523
2
void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
1524
2
  bool Only64Bit = getTriple().getArch() != llvm::Triple::x86;
1525
2
  llvm::X86::fillValidCPUArchList(Values, Only64Bit);
1526
2
}
1527
1528
5
void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const {
1529
5
  llvm::X86::fillValidTuneCPUList(Values);
1530
5
}
1531
1532
3.52k
ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const {
1533
3.52k
  return llvm::makeArrayRef(GCCRegNames);
1534
3.52k
}
1535
1536
3.04k
ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const {
1537
3.04k
  return llvm::makeArrayRef(AddlRegNames);
1538
3.04k
}
1539
1540
14.7k
ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const {
1541
14.7k
  return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin -
1542
14.7k
                                                Builtin::FirstTSBuiltin + 1);
1543
14.7k
}
1544
1545
64.5k
ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const {
1546
64.5k
  return llvm::makeArrayRef(BuiltinInfoX86,
1547
64.5k
                            X86::LastTSBuiltin - Builtin::FirstTSBuiltin);
1548
64.5k
}