Coverage Report

Created: 2022-07-16 07:03

/Users/buildslave/jenkins/workspace/coverage/llvm-project/clang/lib/Basic/Targets/X86.cpp
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Source (jump to first uncovered line)
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//===--- X86.cpp - Implement X86 target feature support -------------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file implements X86 TargetInfo objects.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "X86.h"
14
#include "clang/Basic/Builtins.h"
15
#include "clang/Basic/Diagnostic.h"
16
#include "clang/Basic/TargetBuiltins.h"
17
#include "llvm/ADT/StringExtras.h"
18
#include "llvm/ADT/StringRef.h"
19
#include "llvm/ADT/StringSwitch.h"
20
#include "llvm/Support/X86TargetParser.h"
21
22
namespace clang {
23
namespace targets {
24
25
const Builtin::Info BuiltinInfoX86[] = {
26
#define BUILTIN(ID, TYPE, ATTRS)                                               \
27
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
28
#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)                               \
29
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
30
#define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE)         \
31
  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
32
#include "clang/Basic/BuiltinsX86.def"
33
34
#define BUILTIN(ID, TYPE, ATTRS)                                               \
35
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
36
#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)                               \
37
  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
38
#define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE)         \
39
  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
40
#include "clang/Basic/BuiltinsX86_64.def"
41
};
42
43
static const char *const GCCRegNames[] = {
44
    "ax",    "dx",    "cx",    "bx",    "si",      "di",    "bp",    "sp",
45
    "st",    "st(1)", "st(2)", "st(3)", "st(4)",   "st(5)", "st(6)", "st(7)",
46
    "argp",  "flags", "fpcr",  "fpsr",  "dirflag", "frame", "xmm0",  "xmm1",
47
    "xmm2",  "xmm3",  "xmm4",  "xmm5",  "xmm6",    "xmm7",  "mm0",   "mm1",
48
    "mm2",   "mm3",   "mm4",   "mm5",   "mm6",     "mm7",   "r8",    "r9",
49
    "r10",   "r11",   "r12",   "r13",   "r14",     "r15",   "xmm8",  "xmm9",
50
    "xmm10", "xmm11", "xmm12", "xmm13", "xmm14",   "xmm15", "ymm0",  "ymm1",
51
    "ymm2",  "ymm3",  "ymm4",  "ymm5",  "ymm6",    "ymm7",  "ymm8",  "ymm9",
52
    "ymm10", "ymm11", "ymm12", "ymm13", "ymm14",   "ymm15", "xmm16", "xmm17",
53
    "xmm18", "xmm19", "xmm20", "xmm21", "xmm22",   "xmm23", "xmm24", "xmm25",
54
    "xmm26", "xmm27", "xmm28", "xmm29", "xmm30",   "xmm31", "ymm16", "ymm17",
55
    "ymm18", "ymm19", "ymm20", "ymm21", "ymm22",   "ymm23", "ymm24", "ymm25",
56
    "ymm26", "ymm27", "ymm28", "ymm29", "ymm30",   "ymm31", "zmm0",  "zmm1",
57
    "zmm2",  "zmm3",  "zmm4",  "zmm5",  "zmm6",    "zmm7",  "zmm8",  "zmm9",
58
    "zmm10", "zmm11", "zmm12", "zmm13", "zmm14",   "zmm15", "zmm16", "zmm17",
59
    "zmm18", "zmm19", "zmm20", "zmm21", "zmm22",   "zmm23", "zmm24", "zmm25",
60
    "zmm26", "zmm27", "zmm28", "zmm29", "zmm30",   "zmm31", "k0",    "k1",
61
    "k2",    "k3",    "k4",    "k5",    "k6",      "k7",
62
    "cr0",   "cr2",   "cr3",   "cr4",   "cr8",
63
    "dr0",   "dr1",   "dr2",   "dr3",   "dr6",     "dr7",
64
    "bnd0",  "bnd1",  "bnd2",  "bnd3",
65
    "tmm0",  "tmm1",  "tmm2",  "tmm3",  "tmm4",    "tmm5",  "tmm6",  "tmm7",
66
};
67
68
const TargetInfo::AddlRegName AddlRegNames[] = {
69
    {{"al", "ah", "eax", "rax"}, 0},
70
    {{"bl", "bh", "ebx", "rbx"}, 3},
71
    {{"cl", "ch", "ecx", "rcx"}, 2},
72
    {{"dl", "dh", "edx", "rdx"}, 1},
73
    {{"esi", "rsi"}, 4},
74
    {{"edi", "rdi"}, 5},
75
    {{"esp", "rsp"}, 7},
76
    {{"ebp", "rbp"}, 6},
77
    {{"r8d", "r8w", "r8b"}, 38},
78
    {{"r9d", "r9w", "r9b"}, 39},
79
    {{"r10d", "r10w", "r10b"}, 40},
80
    {{"r11d", "r11w", "r11b"}, 41},
81
    {{"r12d", "r12w", "r12b"}, 42},
82
    {{"r13d", "r13w", "r13b"}, 43},
83
    {{"r14d", "r14w", "r14b"}, 44},
84
    {{"r15d", "r15w", "r15b"}, 45},
85
};
86
87
} // namespace targets
88
} // namespace clang
89
90
using namespace clang;
91
using namespace clang::targets;
92
93
5
bool X86TargetInfo::setFPMath(StringRef Name) {
94
5
  if (Name == "387") {
95
2
    FPMath = FP_387;
96
2
    return true;
97
2
  }
98
3
  if (Name == "sse") {
99
2
    FPMath = FP_SSE;
100
2
    return true;
101
2
  }
102
1
  return false;
103
3
}
104
105
bool X86TargetInfo::initFeatureMap(
106
    llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
107
146k
    const std::vector<std::string> &FeaturesVec) const {
108
  // FIXME: This *really* should not be here.
109
  // X86_64 always has SSE2.
110
146k
  if (getTriple().getArch() == llvm::Triple::x86_64)
111
124k
    setFeatureEnabled(Features, "sse2", true);
112
113
146k
  using namespace llvm::X86;
114
115
146k
  SmallVector<StringRef, 16> CPUFeatures;
116
146k
  getFeaturesForCPU(CPU, CPUFeatures);
117
146k
  for (auto &F : CPUFeatures)
118
558k
    setFeatureEnabled(Features, F, true);
119
120
146k
  std::vector<std::string> UpdatedFeaturesVec;
121
146k
  for (const auto &Feature : FeaturesVec) {
122
    // Expand general-regs-only to -x86, -mmx and -sse
123
143k
    if (Feature == "+general-regs-only") {
124
30
      UpdatedFeaturesVec.push_back("-x87");
125
30
      UpdatedFeaturesVec.push_back("-mmx");
126
30
      UpdatedFeaturesVec.push_back("-sse");
127
30
      continue;
128
30
    }
129
130
143k
    UpdatedFeaturesVec.push_back(Feature);
131
143k
  }
132
133
146k
  if (!TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec))
134
0
    return false;
135
136
  // Can't do this earlier because we need to be able to explicitly enable
137
  // or disable these features and the things that they depend upon.
138
139
  // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
140
146k
  auto I = Features.find("sse4.2");
141
146k
  if (I != Features.end() && 
I->getValue()48.4k
&&
142
146k
      
!llvm::is_contained(UpdatedFeaturesVec, "-popcnt")48.3k
)
143
48.3k
    Features["popcnt"] = true;
144
145
  // Additionally, if SSE is enabled and mmx is not explicitly disabled,
146
  // then enable MMX.
147
146k
  I = Features.find("sse");
148
146k
  if (I != Features.end() && 
I->getValue()140k
&&
149
146k
      
!llvm::is_contained(UpdatedFeaturesVec, "-mmx")140k
)
150
140k
    Features["mmx"] = true;
151
152
  // Enable xsave if avx is enabled and xsave is not explicitly disabled.
153
146k
  I = Features.find("avx");
154
146k
  if (I != Features.end() && 
I->getValue()48.0k
&&
155
146k
      
!llvm::is_contained(UpdatedFeaturesVec, "-xsave")47.9k
)
156
47.9k
    Features["xsave"] = true;
157
158
  // Enable CRC32 if SSE4.2 is enabled and CRC32 is not explicitly disabled.
159
146k
  I = Features.find("sse4.2");
160
146k
  if (I != Features.end() && 
I->getValue()48.4k
&&
161
146k
      
!llvm::is_contained(UpdatedFeaturesVec, "-crc32")48.3k
)
162
48.3k
    Features["crc32"] = true;
163
164
146k
  return true;
165
146k
}
166
167
void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
168
4.55M
                                      StringRef Name, bool Enabled) const {
169
4.55M
  if (Name == "sse4") {
170
    // We can get here via the __target__ attribute since that's not controlled
171
    // via the -msse4/-mno-sse4 command line alias. Handle this the same way
172
    // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
173
    // disabled.
174
4
    if (Enabled)
175
2
      Name = "sse4.2";
176
2
    else
177
2
      Name = "sse4.1";
178
4
  }
179
180
4.55M
  Features[Name] = Enabled;
181
4.55M
  llvm::X86::updateImpliedFeatures(Name, Enabled, Features);
182
4.55M
}
183
184
/// handleTargetFeatures - Perform initialization based on the user
185
/// configured set of features.
186
bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
187
88.8k
                                         DiagnosticsEngine &Diags) {
188
566k
  for (const auto &Feature : Features) {
189
566k
    if (Feature[0] != '+')
190
2.68k
      continue;
191
192
563k
    if (Feature == "+aes") {
193
109
      HasAES = true;
194
563k
    } else if (Feature == "+vaes") {
195
20
      HasVAES = true;
196
563k
    } else if (Feature == "+pclmul") {
197
134
      HasPCLMUL = true;
198
563k
    } else if (Feature == "+vpclmulqdq") {
199
20
      HasVPCLMULQDQ = true;
200
563k
    } else if (Feature == "+lzcnt") {
201
121
      HasLZCNT = true;
202
563k
    } else if (Feature == "+rdrnd") {
203
92
      HasRDRND = true;
204
562k
    } else if (Feature == "+fsgsbase") {
205
90
      HasFSGSBASE = true;
206
562k
    } else if (Feature == "+bmi") {
207
109
      HasBMI = true;
208
562k
    } else if (Feature == "+bmi2") {
209
82
      HasBMI2 = true;
210
562k
    } else if (Feature == "+popcnt") {
211
386
      HasPOPCNT = true;
212
562k
    } else if (Feature == "+rtm") {
213
1
      HasRTM = true;
214
562k
    } else if (Feature == "+prfchw") {
215
124
      HasPRFCHW = true;
216
562k
    } else if (Feature == "+rdseed") {
217
78
      HasRDSEED = true;
218
562k
    } else if (Feature == "+adx") {
219
71
      HasADX = true;
220
562k
    } else if (Feature == "+tbm") {
221
11
      HasTBM = true;
222
562k
    } else if (Feature == "+lwp") {
223
15
      HasLWP = true;
224
561k
    } else if (Feature == "+fma") {
225
207
      HasFMA = true;
226
561k
    } else if (Feature == "+f16c") {
227
229
      HasF16C = true;
228
561k
    } else if (Feature == "+gfni") {
229
20
      HasGFNI = true;
230
561k
    } else if (Feature == "+avx512cd") {
231
48
      HasAVX512CD = true;
232
561k
    } else if (Feature == "+avx512vpopcntdq") {
233
17
      HasAVX512VPOPCNTDQ = true;
234
561k
    } else if (Feature == "+avx512vnni") {
235
19
      HasAVX512VNNI = true;
236
561k
    } else if (Feature == "+avx512bf16") {
237
8
      HasAVX512BF16 = true;
238
561k
    } else if (Feature == "+avx512er") {
239
12
      HasAVX512ER = true;
240
561k
    } else if (Feature == "+avx512fp16") {
241
10
      HasAVX512FP16 = true;
242
561k
    } else if (Feature == "+avx512pf") {
243
11
      HasAVX512PF = true;
244
561k
    } else if (Feature == "+avx512dq") {
245
53
      HasAVX512DQ = true;
246
561k
    } else if (Feature == "+avx512bitalg") {
247
15
      HasAVX512BITALG = true;
248
561k
    } else if (Feature == "+avx512bw") {
249
65
      HasAVX512BW = true;
250
561k
    } else if (Feature == "+avx512vl") {
251
72
      HasAVX512VL = true;
252
561k
    } else if (Feature == "+avx512vbmi") {
253
18
      HasAVX512VBMI = true;
254
561k
    } else if (Feature == "+avx512vbmi2") {
255
15
      HasAVX512VBMI2 = true;
256
561k
    } else if (Feature == "+avx512ifma") {
257
18
      HasAVX512IFMA = true;
258
561k
    } else if (Feature == "+avx512vp2intersect") {
259
9
      HasAVX512VP2INTERSECT = true;
260
561k
    } else if (Feature == "+sha") {
261
37
      HasSHA = true;
262
561k
    } else if (Feature == "+shstk") {
263
12
      HasSHSTK = true;
264
561k
    } else if (Feature == "+movbe") {
265
174
      HasMOVBE = true;
266
560k
    } else if (Feature == "+sgx") {
267
31
      HasSGX = true;
268
560k
    } else if (Feature == "+cx8") {
269
88.8k
      HasCX8 = true;
270
472k
    } else if (Feature == "+cx16") {
271
18.0k
      HasCX16 = true;
272
454k
    } else if (Feature == "+fxsr") {
273
37.0k
      HasFXSR = true;
274
416k
    } else if (Feature == "+xsave") {
275
358
      HasXSAVE = true;
276
416k
    } else if (Feature == "+xsaveopt") {
277
127
      HasXSAVEOPT = true;
278
416k
    } else if (Feature == "+xsavec") {
279
68
      HasXSAVEC = true;
280
416k
    } else if (Feature == "+xsaves") {
281
68
      HasXSAVES = true;
282
416k
    } else if (Feature == "+mwaitx") {
283
19
      HasMWAITX = true;
284
416k
    } else if (Feature == "+pku") {
285
41
      HasPKU = true;
286
416k
    } else if (Feature == "+clflushopt") {
287
62
      HasCLFLUSHOPT = true;
288
416k
    } else if (Feature == "+clwb") {
289
41
      HasCLWB = true;
290
416k
    } else if (Feature == "+wbnoinvd") {
291
18
      HasWBNOINVD = true;
292
416k
    } else if (Feature == "+prefetchwt1") {
293
11
      HasPREFETCHWT1 = true;
294
416k
    } else if (Feature == "+clzero") {
295
17
      HasCLZERO = true;
296
416k
    } else if (Feature == "+cldemote") {
297
9
      HasCLDEMOTE = true;
298
416k
    } else if (Feature == "+rdpid") {
299
29
      HasRDPID = true;
300
416k
    } else if (Feature == "+rdpru") {
301
12
      HasRDPRU = true;
302
416k
    } else if (Feature == "+kl") {
303
8
      HasKL = true;
304
416k
    } else if (Feature == "+widekl") {
305
7
      HasWIDEKL = true;
306
416k
    } else if (Feature == "+retpoline-external-thunk") {
307
0
      HasRetpolineExternalThunk = true;
308
416k
    } else if (Feature == "+sahf") {
309
18.0k
      HasLAHFSAHF = true;
310
397k
    } else if (Feature == "+waitpkg") {
311
6
      HasWAITPKG = true;
312
397k
    } else if (Feature == "+movdiri") {
313
9
      HasMOVDIRI = true;
314
397k
    } else if (Feature == "+movdir64b") {
315
9
      HasMOVDIR64B = true;
316
397k
    } else if (Feature == "+pconfig") {
317
15
      HasPCONFIG = true;
318
397k
    } else if (Feature == "+ptwrite") {
319
10
      HasPTWRITE = true;
320
397k
    } else if (Feature == "+invpcid") {
321
67
      HasINVPCID = true;
322
397k
    } else if (Feature == "+enqcmd") {
323
5
      HasENQCMD = true;
324
397k
    } else if (Feature == "+hreset") {
325
11
      HasHRESET = true;
326
397k
    } else if (Feature == "+amx-bf16") {
327
7
      HasAMXBF16 = true;
328
397k
    } else if (Feature == "+amx-int8") {
329
7
      HasAMXINT8 = true;
330
397k
    } else if (Feature == "+amx-tile") {
331
9
      HasAMXTILE = true;
332
397k
    } else if (Feature == "+avxvnni") {
333
7
      HasAVXVNNI = true;
334
397k
    } else if (Feature == "+serialize") {
335
7
      HasSERIALIZE = true;
336
397k
    } else if (Feature == "+tsxldtrk") {
337
5
      HasTSXLDTRK = true;
338
397k
    } else if (Feature == "+uintr") {
339
4
      HasUINTR = true;
340
397k
    } else if (Feature == "+crc32") {
341
383
      HasCRC32 = true;
342
397k
    } else if (Feature == "+x87") {
343
88.8k
      HasX87 = true;
344
88.8k
    }
345
346
563k
    X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
347
563k
                           .Case("+avx512f", AVX512F)
348
563k
                           .Case("+avx2", AVX2)
349
563k
                           .Case("+avx", AVX)
350
563k
                           .Case("+sse4.2", SSE42)
351
563k
                           .Case("+sse4.1", SSE41)
352
563k
                           .Case("+ssse3", SSSE3)
353
563k
                           .Case("+sse3", SSE3)
354
563k
                           .Case("+sse2", SSE2)
355
563k
                           .Case("+sse", SSE1)
356
563k
                           .Default(NoSSE);
357
563k
    SSELevel = std::max(SSELevel, Level);
358
359
563k
    HasFloat16 = SSELevel >= SSE2;
360
361
563k
    MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature)
362
563k
                                      .Case("+3dnowa", AMD3DNowAthlon)
363
563k
                                      .Case("+3dnow", AMD3DNow)
364
563k
                                      .Case("+mmx", MMX)
365
563k
                                      .Default(NoMMX3DNow);
366
563k
    MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
367
368
563k
    XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
369
563k
                         .Case("+xop", XOP)
370
563k
                         .Case("+fma4", FMA4)
371
563k
                         .Case("+sse4a", SSE4A)
372
563k
                         .Default(NoXOP);
373
563k
    XOPLevel = std::max(XOPLevel, XLevel);
374
563k
  }
375
376
  // LLVM doesn't have a separate switch for fpmath, so only accept it if it
377
  // matches the selected sse level.
378
88.8k
  if ((FPMath == FP_SSE && 
SSELevel < SSE12
) ||
379
88.8k
      (FPMath == FP_387 && 
SSELevel >= SSE12
)) {
380
2
    Diags.Report(diag::err_target_unsupported_fpmath)
381
2
        << (FPMath == FP_SSE ? 
"sse"1
:
"387"1
);
382
2
    return false;
383
2
  }
384
385
88.8k
  SimdDefaultAlign =
386
88.8k
      hasFeature("avx512f") ? 
512161
:
hasFeature("avx")88.7k
?
256163
:
12888.5k
;
387
388
  // FIXME: We should allow long double type on 32-bits to match with GCC.
389
  // This requires backend to be able to lower f80 without x87 first.
390
88.8k
  if (!HasX87 && 
LongDoubleFormat == &llvm::APFloat::x87DoubleExtended()33
)
391
33
    HasLongDouble = false;
392
393
88.8k
  return true;
394
88.8k
}
395
396
/// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
397
/// definitions for this particular subtarget.
398
void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
399
80.1k
                                     MacroBuilder &Builder) const {
400
  // Inline assembly supports X86 flag outputs.
401
80.1k
  Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__");
402
403
80.1k
  std::string CodeModel = getTargetOpts().CodeModel;
404
80.1k
  if (CodeModel == "default")
405
64.2k
    CodeModel = "small";
406
80.1k
  Builder.defineMacro("__code_model_" + CodeModel + "__");
407
408
  // Target identification.
409
80.1k
  if (getTriple().getArch() == llvm::Triple::x86_64) {
410
65.3k
    Builder.defineMacro("__amd64__");
411
65.3k
    Builder.defineMacro("__amd64");
412
65.3k
    Builder.defineMacro("__x86_64");
413
65.3k
    Builder.defineMacro("__x86_64__");
414
65.3k
    if (getTriple().getArchName() == "x86_64h") {
415
2
      Builder.defineMacro("__x86_64h");
416
2
      Builder.defineMacro("__x86_64h__");
417
2
    }
418
65.3k
  } else {
419
14.8k
    DefineStd(Builder, "i386", Opts);
420
14.8k
  }
421
422
80.1k
  Builder.defineMacro("__SEG_GS");
423
80.1k
  Builder.defineMacro("__SEG_FS");
424
80.1k
  Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))");
425
80.1k
  Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))");
426
427
  // Subtarget options.
428
  // FIXME: We are hard-coding the tune parameters based on the CPU, but they
429
  // truly should be based on -mtune options.
430
80.1k
  using namespace llvm::X86;
431
80.1k
  switch (CPU) {
432
43.4k
  case CK_None:
433
43.4k
    break;
434
33
  case CK_i386:
435
    // The rest are coming from the i386 define above.
436
33
    Builder.defineMacro("__tune_i386__");
437
33
    break;
438
5
  case CK_i486:
439
6
  case CK_WinChipC6:
440
7
  case CK_WinChip2:
441
8
  case CK_C3:
442
8
    defineCPUMacros(Builder, "i486");
443
8
    break;
444
1
  case CK_PentiumMMX:
445
1
    Builder.defineMacro("__pentium_mmx__");
446
1
    Builder.defineMacro("__tune_pentium_mmx__");
447
1
    LLVM_FALLTHROUGH;
448
3
  case CK_i586:
449
7
  case CK_Pentium:
450
7
    defineCPUMacros(Builder, "i586");
451
7
    defineCPUMacros(Builder, "pentium");
452
7
    break;
453
4
  case CK_Pentium3:
454
8
  case CK_PentiumM:
455
8
    Builder.defineMacro("__tune_pentium3__");
456
8
    LLVM_FALLTHROUGH;
457
9
  case CK_Pentium2:
458
10
  case CK_C3_2:
459
10
    Builder.defineMacro("__tune_pentium2__");
460
10
    LLVM_FALLTHROUGH;
461
20
  case CK_PentiumPro:
462
36
  case CK_i686:
463
36
    defineCPUMacros(Builder, "i686");
464
36
    defineCPUMacros(Builder, "pentiumpro");
465
36
    break;
466
10.0k
  case CK_Pentium4:
467
10.0k
    defineCPUMacros(Builder, "pentium4");
468
10.0k
    break;
469
10
  case CK_Yonah:
470
11
  case CK_Prescott:
471
14
  case CK_Nocona:
472
14
    defineCPUMacros(Builder, "nocona");
473
14
    break;
474
177
  case CK_Core2:
475
17.4k
  case CK_Penryn:
476
17.4k
    defineCPUMacros(Builder, "core2");
477
17.4k
    break;
478
61
  case CK_Bonnell:
479
61
    defineCPUMacros(Builder, "atom");
480
61
    break;
481
4
  case CK_Silvermont:
482
4
    defineCPUMacros(Builder, "slm");
483
4
    break;
484
2
  case CK_Goldmont:
485
2
    defineCPUMacros(Builder, "goldmont");
486
2
    break;
487
2
  case CK_GoldmontPlus:
488
2
    defineCPUMacros(Builder, "goldmont_plus");
489
2
    break;
490
2
  case CK_Tremont:
491
2
    defineCPUMacros(Builder, "tremont");
492
2
    break;
493
11
  case CK_Nehalem:
494
12
  case CK_Westmere:
495
20
  case CK_SandyBridge:
496
23
  case CK_IvyBridge:
497
29
  case CK_Haswell:
498
33
  case CK_Broadwell:
499
37
  case CK_SkylakeClient:
500
53
  case CK_SkylakeServer:
501
55
  case CK_Cascadelake:
502
57
  case CK_Cooperlake:
503
60
  case CK_Cannonlake:
504
63
  case CK_IcelakeClient:
505
65
  case CK_Rocketlake:
506
68
  case CK_IcelakeServer:
507
70
  case CK_Tigerlake:
508
72
  case CK_SapphireRapids:
509
74
  case CK_Alderlake:
510
    // FIXME: Historically, we defined this legacy name, it would be nice to
511
    // remove it at some point. We've never exposed fine-grained names for
512
    // recent primary x86 CPUs, and we should keep it that way.
513
74
    defineCPUMacros(Builder, "corei7");
514
74
    break;
515
8
  case CK_KNL:
516
8
    defineCPUMacros(Builder, "knl");
517
8
    break;
518
3
  case CK_KNM:
519
3
    break;
520
1
  case CK_Lakemont:
521
1
    defineCPUMacros(Builder, "i586", /*Tuning*/false);
522
1
    defineCPUMacros(Builder, "pentium", /*Tuning*/false);
523
1
    Builder.defineMacro("__tune_lakemont__");
524
1
    break;
525
1
  case CK_K6_2:
526
1
    Builder.defineMacro("__k6_2__");
527
1
    Builder.defineMacro("__tune_k6_2__");
528
1
    LLVM_FALLTHROUGH;
529
2
  case CK_K6_3:
530
2
    if (CPU != CK_K6_2) { // In case of fallthrough
531
      // FIXME: GCC may be enabling these in cases where some other k6
532
      // architecture is specified but -m3dnow is explicitly provided. The
533
      // exact semantics need to be determined and emulated here.
534
1
      Builder.defineMacro("__k6_3__");
535
1
      Builder.defineMacro("__tune_k6_3__");
536
1
    }
537
2
    LLVM_FALLTHROUGH;
538
3
  case CK_K6:
539
3
    defineCPUMacros(Builder, "k6");
540
3
    break;
541
2
  case CK_Athlon:
542
5
  case CK_AthlonXP:
543
5
    defineCPUMacros(Builder, "athlon");
544
5
    if (SSELevel != NoSSE) {
545
3
      Builder.defineMacro("__athlon_sse__");
546
3
      Builder.defineMacro("__tune_athlon_sse__");
547
3
    }
548
5
    break;
549
12
  case CK_K8:
550
21
  case CK_K8SSE3:
551
8.92k
  case CK_x86_64:
552
8.92k
    defineCPUMacros(Builder, "k8");
553
8.92k
    break;
554
1
  case CK_x86_64_v2:
555
2
  case CK_x86_64_v3:
556
3
  case CK_x86_64_v4:
557
3
    break;
558
4
  case CK_AMDFAM10:
559
4
    defineCPUMacros(Builder, "amdfam10");
560
4
    break;
561
4
  case CK_BTVER1:
562
4
    defineCPUMacros(Builder, "btver1");
563
4
    break;
564
19
  case CK_BTVER2:
565
19
    defineCPUMacros(Builder, "btver2");
566
19
    break;
567
4
  case CK_BDVER1:
568
4
    defineCPUMacros(Builder, "bdver1");
569
4
    break;
570
4
  case CK_BDVER2:
571
4
    defineCPUMacros(Builder, "bdver2");
572
4
    break;
573
3
  case CK_BDVER3:
574
3
    defineCPUMacros(Builder, "bdver3");
575
3
    break;
576
3
  case CK_BDVER4:
577
3
    defineCPUMacros(Builder, "bdver4");
578
3
    break;
579
4
  case CK_ZNVER1:
580
4
    defineCPUMacros(Builder, "znver1");
581
4
    break;
582
6
  case CK_ZNVER2:
583
6
    defineCPUMacros(Builder, "znver2");
584
6
    break;
585
3
  case CK_ZNVER3:
586
3
    defineCPUMacros(Builder, "znver3");
587
3
    break;
588
1
  case CK_Geode:
589
1
    defineCPUMacros(Builder, "geode");
590
1
    break;
591
80.1k
  }
592
593
  // Target properties.
594
80.1k
  Builder.defineMacro("__REGISTER_PREFIX__", "");
595
596
  // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
597
  // functions in glibc header files that use FP Stack inline asm which the
598
  // backend can't deal with (PR879).
599
80.1k
  Builder.defineMacro("__NO_MATH_INLINES");
600
601
80.1k
  if (HasAES)
602
107
    Builder.defineMacro("__AES__");
603
604
80.1k
  if (HasVAES)
605
20
    Builder.defineMacro("__VAES__");
606
607
80.1k
  if (HasPCLMUL)
608
132
    Builder.defineMacro("__PCLMUL__");
609
610
80.1k
  if (HasVPCLMULQDQ)
611
20
    Builder.defineMacro("__VPCLMULQDQ__");
612
613
  // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM,
614
  // the feature flag only applies to 64-bit mode.
615
80.1k
  if (HasLAHFSAHF || 
getTriple().getArch() == llvm::Triple::x8662.4k
)
616
32.3k
    Builder.defineMacro("__LAHF_SAHF__");
617
618
80.1k
  if (HasLZCNT)
619
119
    Builder.defineMacro("__LZCNT__");
620
621
80.1k
  if (HasRDRND)
622
92
    Builder.defineMacro("__RDRND__");
623
624
80.1k
  if (HasFSGSBASE)
625
90
    Builder.defineMacro("__FSGSBASE__");
626
627
80.1k
  if (HasBMI)
628
107
    Builder.defineMacro("__BMI__");
629
630
80.1k
  if (HasBMI2)
631
82
    Builder.defineMacro("__BMI2__");
632
633
80.1k
  if (HasPOPCNT)
634
384
    Builder.defineMacro("__POPCNT__");
635
636
80.1k
  if (HasRTM)
637
1
    Builder.defineMacro("__RTM__");
638
639
80.1k
  if (HasPRFCHW)
640
122
    Builder.defineMacro("__PRFCHW__");
641
642
80.1k
  if (HasRDSEED)
643
78
    Builder.defineMacro("__RDSEED__");
644
645
80.1k
  if (HasADX)
646
71
    Builder.defineMacro("__ADX__");
647
648
80.1k
  if (HasTBM)
649
11
    Builder.defineMacro("__TBM__");
650
651
80.1k
  if (HasLWP)
652
15
    Builder.defineMacro("__LWP__");
653
654
80.1k
  if (HasMWAITX)
655
19
    Builder.defineMacro("__MWAITX__");
656
657
80.1k
  if (HasMOVBE)
658
172
    Builder.defineMacro("__MOVBE__");
659
660
80.1k
  switch (XOPLevel) {
661
22
  case XOP:
662
22
    Builder.defineMacro("__XOP__");
663
22
    LLVM_FALLTHROUGH;
664
24
  case FMA4:
665
24
    Builder.defineMacro("__FMA4__");
666
24
    LLVM_FALLTHROUGH;
667
65
  case SSE4A:
668
65
    Builder.defineMacro("__SSE4A__");
669
65
    LLVM_FALLTHROUGH;
670
80.1k
  case NoXOP:
671
80.1k
    break;
672
80.1k
  }
673
674
80.1k
  if (HasFMA)
675
207
    Builder.defineMacro("__FMA__");
676
677
80.1k
  if (HasF16C)
678
227
    Builder.defineMacro("__F16C__");
679
680
80.1k
  if (HasGFNI)
681
20
    Builder.defineMacro("__GFNI__");
682
683
80.1k
  if (HasAVX512CD)
684
48
    Builder.defineMacro("__AVX512CD__");
685
80.1k
  if (HasAVX512VPOPCNTDQ)
686
17
    Builder.defineMacro("__AVX512VPOPCNTDQ__");
687
80.1k
  if (HasAVX512VNNI)
688
19
    Builder.defineMacro("__AVX512VNNI__");
689
80.1k
  if (HasAVX512BF16)
690
8
    Builder.defineMacro("__AVX512BF16__");
691
80.1k
  if (HasAVX512ER)
692
12
    Builder.defineMacro("__AVX512ER__");
693
80.1k
  if (HasAVX512FP16)
694
10
    Builder.defineMacro("__AVX512FP16__");
695
80.1k
  if (HasAVX512PF)
696
11
    Builder.defineMacro("__AVX512PF__");
697
80.1k
  if (HasAVX512DQ)
698
53
    Builder.defineMacro("__AVX512DQ__");
699
80.1k
  if (HasAVX512BITALG)
700
15
    Builder.defineMacro("__AVX512BITALG__");
701
80.1k
  if (HasAVX512BW)
702
65
    Builder.defineMacro("__AVX512BW__");
703
80.1k
  if (HasAVX512VL)
704
72
    Builder.defineMacro("__AVX512VL__");
705
80.1k
  if (HasAVX512VBMI)
706
18
    Builder.defineMacro("__AVX512VBMI__");
707
80.1k
  if (HasAVX512VBMI2)
708
15
    Builder.defineMacro("__AVX512VBMI2__");
709
80.1k
  if (HasAVX512IFMA)
710
18
    Builder.defineMacro("__AVX512IFMA__");
711
80.1k
  if (HasAVX512VP2INTERSECT)
712
9
    Builder.defineMacro("__AVX512VP2INTERSECT__");
713
80.1k
  if (HasSHA)
714
37
    Builder.defineMacro("__SHA__");
715
716
80.1k
  if (HasFXSR)
717
36.6k
    Builder.defineMacro("__FXSR__");
718
80.1k
  if (HasXSAVE)
719
356
    Builder.defineMacro("__XSAVE__");
720
80.1k
  if (HasXSAVEOPT)
721
125
    Builder.defineMacro("__XSAVEOPT__");
722
80.1k
  if (HasXSAVEC)
723
68
    Builder.defineMacro("__XSAVEC__");
724
80.1k
  if (HasXSAVES)
725
68
    Builder.defineMacro("__XSAVES__");
726
80.1k
  if (HasPKU)
727
41
    Builder.defineMacro("__PKU__");
728
80.1k
  if (HasCLFLUSHOPT)
729
62
    Builder.defineMacro("__CLFLUSHOPT__");
730
80.1k
  if (HasCLWB)
731
41
    Builder.defineMacro("__CLWB__");
732
80.1k
  if (HasWBNOINVD)
733
18
    Builder.defineMacro("__WBNOINVD__");
734
80.1k
  if (HasSHSTK)
735
12
    Builder.defineMacro("__SHSTK__");
736
80.1k
  if (HasSGX)
737
31
    Builder.defineMacro("__SGX__");
738
80.1k
  if (HasPREFETCHWT1)
739
11
    Builder.defineMacro("__PREFETCHWT1__");
740
80.1k
  if (HasCLZERO)
741
17
    Builder.defineMacro("__CLZERO__");
742
80.1k
  if (HasKL)
743
8
    Builder.defineMacro("__KL__");
744
80.1k
  if (HasWIDEKL)
745
7
    Builder.defineMacro("__WIDEKL__");
746
80.1k
  if (HasRDPID)
747
29
    Builder.defineMacro("__RDPID__");
748
80.1k
  if (HasRDPRU)
749
12
    Builder.defineMacro("__RDPRU__");
750
80.1k
  if (HasCLDEMOTE)
751
9
    Builder.defineMacro("__CLDEMOTE__");
752
80.1k
  if (HasWAITPKG)
753
6
    Builder.defineMacro("__WAITPKG__");
754
80.1k
  if (HasMOVDIRI)
755
9
    Builder.defineMacro("__MOVDIRI__");
756
80.1k
  if (HasMOVDIR64B)
757
9
    Builder.defineMacro("__MOVDIR64B__");
758
80.1k
  if (HasPCONFIG)
759
15
    Builder.defineMacro("__PCONFIG__");
760
80.1k
  if (HasPTWRITE)
761
10
    Builder.defineMacro("__PTWRITE__");
762
80.1k
  if (HasINVPCID)
763
67
    Builder.defineMacro("__INVPCID__");
764
80.1k
  if (HasENQCMD)
765
5
    Builder.defineMacro("__ENQCMD__");
766
80.1k
  if (HasHRESET)
767
11
    Builder.defineMacro("__HRESET__");
768
80.1k
  if (HasAMXTILE)
769
9
    Builder.defineMacro("__AMXTILE__");
770
80.1k
  if (HasAMXINT8)
771
7
    Builder.defineMacro("__AMXINT8__");
772
80.1k
  if (HasAMXBF16)
773
7
    Builder.defineMacro("__AMXBF16__");
774
80.1k
  if (HasAVXVNNI)
775
7
    Builder.defineMacro("__AVXVNNI__");
776
80.1k
  if (HasSERIALIZE)
777
7
    Builder.defineMacro("__SERIALIZE__");
778
80.1k
  if (HasTSXLDTRK)
779
5
    Builder.defineMacro("__TSXLDTRK__");
780
80.1k
  if (HasUINTR)
781
4
    Builder.defineMacro("__UINTR__");
782
80.1k
  if (HasCRC32)
783
381
    Builder.defineMacro("__CRC32__");
784
785
  // Each case falls through to the previous one here.
786
80.1k
  switch (SSELevel) {
787
161
  case AVX512F:
788
161
    Builder.defineMacro("__AVX512F__");
789
161
    LLVM_FALLTHROUGH;
790
211
  case AVX2:
791
211
    Builder.defineMacro("__AVX2__");
792
211
    LLVM_FALLTHROUGH;
793
322
  case AVX:
794
322
    Builder.defineMacro("__AVX__");
795
322
    LLVM_FALLTHROUGH;
796
369
  case SSE42:
797
369
    Builder.defineMacro("__SSE4_2__");
798
369
    LLVM_FALLTHROUGH;
799
17.6k
  case SSE41:
800
17.6k
    Builder.defineMacro("__SSE4_1__");
801
17.6k
    LLVM_FALLTHROUGH;
802
17.8k
  case SSSE3:
803
17.8k
    Builder.defineMacro("__SSSE3__");
804
17.8k
    LLVM_FALLTHROUGH;
805
17.8k
  case SSE3:
806
17.8k
    Builder.defineMacro("__SSE3__");
807
17.8k
    LLVM_FALLTHROUGH;
808
75.4k
  case SSE2:
809
75.4k
    Builder.defineMacro("__SSE2__");
810
75.4k
    Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
811
75.4k
    LLVM_FALLTHROUGH;
812
75.5k
  case SSE1:
813
75.5k
    Builder.defineMacro("__SSE__");
814
75.5k
    Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
815
75.5k
    LLVM_FALLTHROUGH;
816
80.1k
  case NoSSE:
817
80.1k
    break;
818
80.1k
  }
819
820
80.1k
  if (Opts.MicrosoftExt && 
getTriple().getArch() == llvm::Triple::x8611.1k
) {
821
347
    switch (SSELevel) {
822
2
    case AVX512F:
823
4
    case AVX2:
824
6
    case AVX:
825
6
    case SSE42:
826
6
    case SSE41:
827
6
    case SSSE3:
828
6
    case SSE3:
829
59
    case SSE2:
830
59
      Builder.defineMacro("_M_IX86_FP", Twine(2));
831
59
      break;
832
2
    case SSE1:
833
2
      Builder.defineMacro("_M_IX86_FP", Twine(1));
834
2
      break;
835
286
    default:
836
286
      Builder.defineMacro("_M_IX86_FP", Twine(0));
837
286
      break;
838
347
    }
839
347
  }
840
841
  // Each case falls through to the previous one here.
842
80.1k
  switch (MMX3DNowLevel) {
843
34
  case AMD3DNowAthlon:
844
34
    Builder.defineMacro("__3dNOW_A__");
845
34
    LLVM_FALLTHROUGH;
846
40
  case AMD3DNow:
847
40
    Builder.defineMacro("__3dNOW__");
848
40
    LLVM_FALLTHROUGH;
849
75.5k
  case MMX:
850
75.5k
    Builder.defineMacro("__MMX__");
851
75.5k
    LLVM_FALLTHROUGH;
852
80.1k
  case NoMMX3DNow:
853
80.1k
    break;
854
80.1k
  }
855
856
80.1k
  if (CPU >= CK_i486 || 
CPU == CK_None43.4k
) {
857
80.0k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
858
80.0k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
859
80.0k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
860
80.0k
  }
861
80.1k
  if (HasCX8)
862
80.0k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
863
80.1k
  if (HasCX16 && 
getTriple().getArch() == llvm::Triple::x86_6417.6k
)
864
17.5k
    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
865
866
80.1k
  if (HasFloat128)
867
4.24k
    Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
868
80.1k
}
869
870
1.55M
bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
871
1.55M
  return llvm::StringSwitch<bool>(Name)
872
1.55M
      .Case("3dnow", true)
873
1.55M
      .Case("3dnowa", true)
874
1.55M
      .Case("adx", true)
875
1.55M
      .Case("aes", true)
876
1.55M
      .Case("amx-bf16", true)
877
1.55M
      .Case("amx-int8", true)
878
1.55M
      .Case("amx-tile", true)
879
1.55M
      .Case("avx", true)
880
1.55M
      .Case("avx2", true)
881
1.55M
      .Case("avx512f", true)
882
1.55M
      .Case("avx512cd", true)
883
1.55M
      .Case("avx512vpopcntdq", true)
884
1.55M
      .Case("avx512vnni", true)
885
1.55M
      .Case("avx512bf16", true)
886
1.55M
      .Case("avx512er", true)
887
1.55M
      .Case("avx512fp16", true)
888
1.55M
      .Case("avx512pf", true)
889
1.55M
      .Case("avx512dq", true)
890
1.55M
      .Case("avx512bitalg", true)
891
1.55M
      .Case("avx512bw", true)
892
1.55M
      .Case("avx512vl", true)
893
1.55M
      .Case("avx512vbmi", true)
894
1.55M
      .Case("avx512vbmi2", true)
895
1.55M
      .Case("avx512ifma", true)
896
1.55M
      .Case("avx512vp2intersect", true)
897
1.55M
      .Case("avxvnni", true)
898
1.55M
      .Case("bmi", true)
899
1.55M
      .Case("bmi2", true)
900
1.55M
      .Case("cldemote", true)
901
1.55M
      .Case("clflushopt", true)
902
1.55M
      .Case("clwb", true)
903
1.55M
      .Case("clzero", true)
904
1.55M
      .Case("crc32", true)
905
1.55M
      .Case("cx16", true)
906
1.55M
      .Case("enqcmd", true)
907
1.55M
      .Case("f16c", true)
908
1.55M
      .Case("fma", true)
909
1.55M
      .Case("fma4", true)
910
1.55M
      .Case("fsgsbase", true)
911
1.55M
      .Case("fxsr", true)
912
1.55M
      .Case("general-regs-only", true)
913
1.55M
      .Case("gfni", true)
914
1.55M
      .Case("hreset", true)
915
1.55M
      .Case("invpcid", true)
916
1.55M
      .Case("kl", true)
917
1.55M
      .Case("widekl", true)
918
1.55M
      .Case("lwp", true)
919
1.55M
      .Case("lzcnt", true)
920
1.55M
      .Case("mmx", true)
921
1.55M
      .Case("movbe", true)
922
1.55M
      .Case("movdiri", true)
923
1.55M
      .Case("movdir64b", true)
924
1.55M
      .Case("mwaitx", true)
925
1.55M
      .Case("pclmul", true)
926
1.55M
      .Case("pconfig", true)
927
1.55M
      .Case("pku", true)
928
1.55M
      .Case("popcnt", true)
929
1.55M
      .Case("prefetchwt1", true)
930
1.55M
      .Case("prfchw", true)
931
1.55M
      .Case("ptwrite", true)
932
1.55M
      .Case("rdpid", true)
933
1.55M
      .Case("rdpru", true)
934
1.55M
      .Case("rdrnd", true)
935
1.55M
      .Case("rdseed", true)
936
1.55M
      .Case("rtm", true)
937
1.55M
      .Case("sahf", true)
938
1.55M
      .Case("serialize", true)
939
1.55M
      .Case("sgx", true)
940
1.55M
      .Case("sha", true)
941
1.55M
      .Case("shstk", true)
942
1.55M
      .Case("sse", true)
943
1.55M
      .Case("sse2", true)
944
1.55M
      .Case("sse3", true)
945
1.55M
      .Case("ssse3", true)
946
1.55M
      .Case("sse4", true)
947
1.55M
      .Case("sse4.1", true)
948
1.55M
      .Case("sse4.2", true)
949
1.55M
      .Case("sse4a", true)
950
1.55M
      .Case("tbm", true)
951
1.55M
      .Case("tsxldtrk", true)
952
1.55M
      .Case("uintr", true)
953
1.55M
      .Case("vaes", true)
954
1.55M
      .Case("vpclmulqdq", true)
955
1.55M
      .Case("wbnoinvd", true)
956
1.55M
      .Case("waitpkg", true)
957
1.55M
      .Case("x87", true)
958
1.55M
      .Case("xop", true)
959
1.55M
      .Case("xsave", true)
960
1.55M
      .Case("xsavec", true)
961
1.55M
      .Case("xsaves", true)
962
1.55M
      .Case("xsaveopt", true)
963
1.55M
      .Default(false);
964
1.55M
}
965
966
477k
bool X86TargetInfo::hasFeature(StringRef Feature) const {
967
477k
  return llvm::StringSwitch<bool>(Feature)
968
477k
      .Case("adx", HasADX)
969
477k
      .Case("aes", HasAES)
970
477k
      .Case("amx-bf16", HasAMXBF16)
971
477k
      .Case("amx-int8", HasAMXINT8)
972
477k
      .Case("amx-tile", HasAMXTILE)
973
477k
      .Case("avxvnni", HasAVXVNNI)
974
477k
      .Case("avx", SSELevel >= AVX)
975
477k
      .Case("avx2", SSELevel >= AVX2)
976
477k
      .Case("avx512f", SSELevel >= AVX512F)
977
477k
      .Case("avx512cd", HasAVX512CD)
978
477k
      .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
979
477k
      .Case("avx512vnni", HasAVX512VNNI)
980
477k
      .Case("avx512bf16", HasAVX512BF16)
981
477k
      .Case("avx512er", HasAVX512ER)
982
477k
      .Case("avx512fp16", HasAVX512FP16)
983
477k
      .Case("avx512pf", HasAVX512PF)
984
477k
      .Case("avx512dq", HasAVX512DQ)
985
477k
      .Case("avx512bitalg", HasAVX512BITALG)
986
477k
      .Case("avx512bw", HasAVX512BW)
987
477k
      .Case("avx512vl", HasAVX512VL)
988
477k
      .Case("avx512vbmi", HasAVX512VBMI)
989
477k
      .Case("avx512vbmi2", HasAVX512VBMI2)
990
477k
      .Case("avx512ifma", HasAVX512IFMA)
991
477k
      .Case("avx512vp2intersect", HasAVX512VP2INTERSECT)
992
477k
      .Case("bmi", HasBMI)
993
477k
      .Case("bmi2", HasBMI2)
994
477k
      .Case("cldemote", HasCLDEMOTE)
995
477k
      .Case("clflushopt", HasCLFLUSHOPT)
996
477k
      .Case("clwb", HasCLWB)
997
477k
      .Case("clzero", HasCLZERO)
998
477k
      .Case("crc32", HasCRC32)
999
477k
      .Case("cx8", HasCX8)
1000
477k
      .Case("cx16", HasCX16)
1001
477k
      .Case("enqcmd", HasENQCMD)
1002
477k
      .Case("f16c", HasF16C)
1003
477k
      .Case("fma", HasFMA)
1004
477k
      .Case("fma4", XOPLevel >= FMA4)
1005
477k
      .Case("fsgsbase", HasFSGSBASE)
1006
477k
      .Case("fxsr", HasFXSR)
1007
477k
      .Case("gfni", HasGFNI)
1008
477k
      .Case("hreset", HasHRESET)
1009
477k
      .Case("invpcid", HasINVPCID)
1010
477k
      .Case("kl", HasKL)
1011
477k
      .Case("widekl", HasWIDEKL)
1012
477k
      .Case("lwp", HasLWP)
1013
477k
      .Case("lzcnt", HasLZCNT)
1014
477k
      .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
1015
477k
      .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
1016
477k
      .Case("mmx", MMX3DNowLevel >= MMX)
1017
477k
      .Case("movbe", HasMOVBE)
1018
477k
      .Case("movdiri", HasMOVDIRI)
1019
477k
      .Case("movdir64b", HasMOVDIR64B)
1020
477k
      .Case("mwaitx", HasMWAITX)
1021
477k
      .Case("pclmul", HasPCLMUL)
1022
477k
      .Case("pconfig", HasPCONFIG)
1023
477k
      .Case("pku", HasPKU)
1024
477k
      .Case("popcnt", HasPOPCNT)
1025
477k
      .Case("prefetchwt1", HasPREFETCHWT1)
1026
477k
      .Case("prfchw", HasPRFCHW)
1027
477k
      .Case("ptwrite", HasPTWRITE)
1028
477k
      .Case("rdpid", HasRDPID)
1029
477k
      .Case("rdpru", HasRDPRU)
1030
477k
      .Case("rdrnd", HasRDRND)
1031
477k
      .Case("rdseed", HasRDSEED)
1032
477k
      .Case("retpoline-external-thunk", HasRetpolineExternalThunk)
1033
477k
      .Case("rtm", HasRTM)
1034
477k
      .Case("sahf", HasLAHFSAHF)
1035
477k
      .Case("serialize", HasSERIALIZE)
1036
477k
      .Case("sgx", HasSGX)
1037
477k
      .Case("sha", HasSHA)
1038
477k
      .Case("shstk", HasSHSTK)
1039
477k
      .Case("sse", SSELevel >= SSE1)
1040
477k
      .Case("sse2", SSELevel >= SSE2)
1041
477k
      .Case("sse3", SSELevel >= SSE3)
1042
477k
      .Case("ssse3", SSELevel >= SSSE3)
1043
477k
      .Case("sse4.1", SSELevel >= SSE41)
1044
477k
      .Case("sse4.2", SSELevel >= SSE42)
1045
477k
      .Case("sse4a", XOPLevel >= SSE4A)
1046
477k
      .Case("tbm", HasTBM)
1047
477k
      .Case("tsxldtrk", HasTSXLDTRK)
1048
477k
      .Case("uintr", HasUINTR)
1049
477k
      .Case("vaes", HasVAES)
1050
477k
      .Case("vpclmulqdq", HasVPCLMULQDQ)
1051
477k
      .Case("wbnoinvd", HasWBNOINVD)
1052
477k
      .Case("waitpkg", HasWAITPKG)
1053
477k
      .Case("x86", true)
1054
477k
      .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
1055
477k
      .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
1056
477k
      .Case("x87", HasX87)
1057
477k
      .Case("xop", XOPLevel >= XOP)
1058
477k
      .Case("xsave", HasXSAVE)
1059
477k
      .Case("xsavec", HasXSAVEC)
1060
477k
      .Case("xsaves", HasXSAVES)
1061
477k
      .Case("xsaveopt", HasXSAVEOPT)
1062
477k
      .Default(false);
1063
477k
}
1064
1065
// We can't use a generic validation scheme for the features accepted here
1066
// versus subtarget features accepted in the target attribute because the
1067
// bitfield structure that's initialized in the runtime only supports the
1068
// below currently rather than the full range of subtarget features. (See
1069
// X86TargetInfo::hasFeature for a somewhat comprehensive list).
1070
1.06k
bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
1071
1.06k
  return llvm::StringSwitch<bool>(FeatureStr)
1072
40.3k
#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) .Case(STR, true)
1073
1.06k
#include "llvm/Support/X86TargetParser.def"
1074
1.06k
      .Default(false);
1075
1.06k
}
1076
1077
182
static llvm::X86::ProcessorFeatures getFeature(StringRef Name) {
1078
182
  return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name)
1079
182
#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY)                                \
1080
6.91k
  .Case(STR, llvm::X86::FEATURE_##ENUM)
1081
1082
182
#include "llvm/Support/X86TargetParser.def"
1083
182
      ;
1084
  // Note, this function should only be used after ensuring the value is
1085
  // correct, so it asserts if the value is out of range.
1086
182
}
1087
1088
475
unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const {
1089
  // Valid CPUs have a 'key feature' that compares just better than its key
1090
  // feature.
1091
475
  using namespace llvm::X86;
1092
475
  CPUKind Kind = parseArchX86(Name);
1093
475
  if (Kind != CK_None) {
1094
293
    ProcessorFeatures KeyFeature = getKeyFeature(Kind);
1095
293
    return (getFeaturePriority(KeyFeature) << 1) + 1;
1096
293
  }
1097
1098
  // Now we know we have a feature, so get its priority and shift it a few so
1099
  // that we have sufficient room for the CPUs (above).
1100
182
  return getFeaturePriority(getFeature(Name)) << 1;
1101
475
}
1102
1103
263
bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const {
1104
263
  return llvm::StringSwitch<bool>(Name)
1105
7.36k
#define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, true)
1106
1.57k
#define CPU_SPECIFIC_ALIAS(NEW_NAME, TUNE_NAME, NAME) .Case(NEW_NAME, true)
1107
263
#include "llvm/Support/X86TargetParser.def"
1108
263
      .Default(false);
1109
263
}
1110
1111
546
static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) {
1112
546
  return llvm::StringSwitch<StringRef>(Name)
1113
3.27k
#define CPU_SPECIFIC_ALIAS(NEW_NAME, TUNE_NAME, NAME) .Case(NEW_NAME, NAME)
1114
546
#include "llvm/Support/X86TargetParser.def"
1115
546
      .Default(Name);
1116
546
}
1117
1118
354
char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const {
1119
354
  return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name))
1120
9.91k
#define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, MANGLING)
1121
354
#include "llvm/Support/X86TargetParser.def"
1122
354
      .Default(0);
1123
354
}
1124
1125
void X86TargetInfo::getCPUSpecificCPUDispatchFeatures(
1126
192
    StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const {
1127
192
  StringRef WholeList =
1128
192
      llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name))
1129
5.37k
#define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, FEATURES)
1130
192
#include "llvm/Support/X86TargetParser.def"
1131
192
          .Default("");
1132
192
  WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false);
1133
192
}
1134
1135
92
StringRef X86TargetInfo::getCPUSpecificTuneName(StringRef Name) const {
1136
92
  return llvm::StringSwitch<StringRef>(Name)
1137
2.57k
#define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, TUNE_NAME)
1138
552
#define CPU_SPECIFIC_ALIAS(NEW_NAME, TUNE_NAME, NAME) .Case(NEW_NAME, TUNE_NAME)
1139
92
#include "llvm/Support/X86TargetParser.def"
1140
92
      .Default("");
1141
92
}
1142
1143
// We can't use a generic validation scheme for the cpus accepted here
1144
// versus subtarget cpus accepted in the target attribute because the
1145
// variables intitialized by the runtime only support the below currently
1146
// rather than the full range of cpus.
1147
196
bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
1148
196
  return llvm::StringSwitch<bool>(FeatureStr)
1149
392
#define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
1150
784
#define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true)
1151
2.94k
#define X86_CPU_TYPE(ENUM, STR) .Case(STR, true)
1152
5.29k
#define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true)
1153
196
#include "llvm/Support/X86TargetParser.def"
1154
196
      .Default(false);
1155
196
}
1156
1157
87
static unsigned matchAsmCCConstraint(const char *&Name) {
1158
87
  auto RV = llvm::StringSwitch<unsigned>(Name)
1159
87
                .Case("@cca", 4)
1160
87
                .Case("@ccae", 5)
1161
87
                .Case("@ccb", 4)
1162
87
                .Case("@ccbe", 5)
1163
87
                .Case("@ccc", 4)
1164
87
                .Case("@cce", 4)
1165
87
                .Case("@ccz", 4)
1166
87
                .Case("@ccg", 4)
1167
87
                .Case("@ccge", 5)
1168
87
                .Case("@ccl", 4)
1169
87
                .Case("@ccle", 5)
1170
87
                .Case("@ccna", 5)
1171
87
                .Case("@ccnae", 6)
1172
87
                .Case("@ccnb", 5)
1173
87
                .Case("@ccnbe", 6)
1174
87
                .Case("@ccnc", 5)
1175
87
                .Case("@ccne", 5)
1176
87
                .Case("@ccnz", 5)
1177
87
                .Case("@ccng", 5)
1178
87
                .Case("@ccnge", 6)
1179
87
                .Case("@ccnl", 5)
1180
87
                .Case("@ccnle", 6)
1181
87
                .Case("@ccno", 5)
1182
87
                .Case("@ccnp", 5)
1183
87
                .Case("@ccns", 5)
1184
87
                .Case("@cco", 4)
1185
87
                .Case("@ccp", 4)
1186
87
                .Case("@ccs", 4)
1187
87
                .Default(0);
1188
87
  return RV;
1189
87
}
1190
1191
bool X86TargetInfo::validateAsmConstraint(
1192
11.5k
    const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1193
11.5k
  switch (*Name) {
1194
2
  default:
1195
2
    return false;
1196
  // Constant constraints.
1197
9
  case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1198
            // instructions.
1199
17
  case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1200
            // x86_64 instructions.
1201
17
  case 's':
1202
17
    Info.setRequiresImmediate();
1203
17
    return true;
1204
28
  case 'I':
1205
28
    Info.setRequiresImmediate(0, 31);
1206
28
    return true;
1207
14
  case 'J':
1208
14
    Info.setRequiresImmediate(0, 63);
1209
14
    return true;
1210
14
  case 'K':
1211
14
    Info.setRequiresImmediate(-128, 127);
1212
14
    return true;
1213
30
  case 'L':
1214
30
    Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1215
30
    return true;
1216
14
  case 'M':
1217
14
    Info.setRequiresImmediate(0, 3);
1218
14
    return true;
1219
16
  case 'N':
1220
16
    Info.setRequiresImmediate(0, 255);
1221
16
    return true;
1222
6
  case 'O':
1223
6
    Info.setRequiresImmediate(0, 127);
1224
6
    return true;
1225
  // Register constraints.
1226
52
  case 'Y': // 'Y' is the first character for several 2-character constraints.
1227
    // Shift the pointer to the second character of the constraint.
1228
52
    Name++;
1229
52
    switch (*Name) {
1230
0
    default:
1231
0
      return false;
1232
20
    case 'z': // First SSE register.
1233
26
    case '2':
1234
32
    case 't': // Any SSE register, when SSE2 is enabled.
1235
42
    case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1236
44
    case 'm': // Any MMX register, when inter-unit moves enabled.
1237
52
    case 'k': // AVX512 arch mask registers: k1-k7.
1238
52
      Info.setAllowsRegister();
1239
52
      return true;
1240
52
    }
1241
3
  case 'f': // Any x87 floating point stack register.
1242
    // Constraint 'f' cannot be used for output operands.
1243
3
    if (Info.ConstraintStr[0] == '=')
1244
1
      return false;
1245
2
    Info.setAllowsRegister();
1246
2
    return true;
1247
3.00k
  case 'a': // eax.
1248
5.47k
  case 'b': // ebx.
1249
8.13k
  case 'c': // ecx.
1250
10.6k
  case 'd': // edx.
1251
10.7k
  case 'S': // esi.
1252
10.8k
  case 'D': // edi.
1253
10.9k
  case 'A': // edx:eax.
1254
10.9k
  case 't': // Top of floating point stack.
1255
10.9k
  case 'u': // Second from top of floating point stack.
1256
10.9k
  case 'q': // Any register accessible as [r]l: a, b, c, and d.
1257
10.9k
  case 'y': // Any MMX register.
1258
11.0k
  case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1259
11.1k
  case 'x': // Any SSE register.
1260
11.1k
  case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0
1261
            // for intermideate k reg operations).
1262
11.2k
  case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1263
11.2k
  case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1264
11.2k
  case 'l': // "Index" registers: any general register that can be used as an
1265
            // index in a base+index memory access.
1266
11.2k
    Info.setAllowsRegister();
1267
11.2k
    return true;
1268
  // Floating point constant constraints.
1269
8
  case 'C': // SSE floating point constant.
1270
16
  case 'G': // x87 floating point constant.
1271
16
    return true;
1272
58
  case '@':
1273
    // CC condition changes.
1274
58
    if (auto Len = matchAsmCCConstraint(Name)) {
1275
58
      Name += Len - 1;
1276
58
      Info.setAllowsRegister();
1277
58
      return true;
1278
58
    }
1279
0
    return false;
1280
11.5k
  }
1281
11.5k
}
1282
1283
// Below is based on the following information:
1284
// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1285
// |           Processor Name           | Cache Line Size (Bytes) |                                                                            Source                                                                            |
1286
// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1287
// | i386                               |                      64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf                                          |
1288
// | i486                               |                      16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) |
1289
// | i586/Pentium MMX                   |                      32 | https://www.7-cpu.com/cpu/P-MMX.html                                                                                                                         |
1290
// | i686/Pentium                       |                      32 | https://www.7-cpu.com/cpu/P6.html                                                                                                                            |
1291
// | Netburst/Pentium4                  |                      64 | https://www.7-cpu.com/cpu/P4-180.html                                                                                                                        |
1292
// | Atom                               |                      64 | https://www.7-cpu.com/cpu/Atom.html                                                                                                                          |
1293
// | Westmere                           |                      64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture"                                                             |
1294
// | Sandy Bridge                       |                      64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html                                                                    |
1295
// | Ivy Bridge                         |                      64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html                                                      |
1296
// | Haswell                            |                      64 | https://www.7-cpu.com/cpu/Haswell.html                                                                                                                       |
1297
// | Boadwell                           |                      64 | https://www.7-cpu.com/cpu/Broadwell.html                                                                                                                     |
1298
// | Skylake (including skylake-avx512) |                      64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy"                                                                       |
1299
// | Cascade Lake                       |                      64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy"                                                                  |
1300
// | Skylake                            |                      64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy"                                                                           |
1301
// | Ice Lake                           |                      64 | https://www.7-cpu.com/cpu/Ice_Lake.html                                                                                                                      |
1302
// | Knights Landing                    |                      64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" |
1303
// | Knights Mill                       |                      64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache "       |
1304
// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1305
0
Optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const {
1306
0
  using namespace llvm::X86;
1307
0
  switch (CPU) {
1308
    // i386
1309
0
    case CK_i386:
1310
    // i486
1311
0
    case CK_i486:
1312
0
    case CK_WinChipC6:
1313
0
    case CK_WinChip2:
1314
0
    case CK_C3:
1315
    // Lakemont
1316
0
    case CK_Lakemont:
1317
0
      return 16;
1318
1319
    // i586
1320
0
    case CK_i586:
1321
0
    case CK_Pentium:
1322
0
    case CK_PentiumMMX:
1323
    // i686
1324
0
    case CK_PentiumPro:
1325
0
    case CK_i686:
1326
0
    case CK_Pentium2:
1327
0
    case CK_Pentium3:
1328
0
    case CK_PentiumM:
1329
0
    case CK_C3_2:
1330
    // K6
1331
0
    case CK_K6:
1332
0
    case CK_K6_2:
1333
0
    case CK_K6_3:
1334
    // Geode
1335
0
    case CK_Geode:
1336
0
      return 32;
1337
1338
    // Netburst
1339
0
    case CK_Pentium4:
1340
0
    case CK_Prescott:
1341
0
    case CK_Nocona:
1342
    // Atom
1343
0
    case CK_Bonnell:
1344
0
    case CK_Silvermont:
1345
0
    case CK_Goldmont:
1346
0
    case CK_GoldmontPlus:
1347
0
    case CK_Tremont:
1348
1349
0
    case CK_Westmere:
1350
0
    case CK_SandyBridge:
1351
0
    case CK_IvyBridge:
1352
0
    case CK_Haswell:
1353
0
    case CK_Broadwell:
1354
0
    case CK_SkylakeClient:
1355
0
    case CK_SkylakeServer:
1356
0
    case CK_Cascadelake:
1357
0
    case CK_Nehalem:
1358
0
    case CK_Cooperlake:
1359
0
    case CK_Cannonlake:
1360
0
    case CK_Tigerlake:
1361
0
    case CK_SapphireRapids:
1362
0
    case CK_IcelakeClient:
1363
0
    case CK_Rocketlake:
1364
0
    case CK_IcelakeServer:
1365
0
    case CK_Alderlake:
1366
0
    case CK_KNL:
1367
0
    case CK_KNM:
1368
    // K7
1369
0
    case CK_Athlon:
1370
0
    case CK_AthlonXP:
1371
    // K8
1372
0
    case CK_K8:
1373
0
    case CK_K8SSE3:
1374
0
    case CK_AMDFAM10:
1375
    // Bobcat
1376
0
    case CK_BTVER1:
1377
0
    case CK_BTVER2:
1378
    // Bulldozer
1379
0
    case CK_BDVER1:
1380
0
    case CK_BDVER2:
1381
0
    case CK_BDVER3:
1382
0
    case CK_BDVER4:
1383
    // Zen
1384
0
    case CK_ZNVER1:
1385
0
    case CK_ZNVER2:
1386
0
    case CK_ZNVER3:
1387
    // Deprecated
1388
0
    case CK_x86_64:
1389
0
    case CK_x86_64_v2:
1390
0
    case CK_x86_64_v3:
1391
0
    case CK_x86_64_v4:
1392
0
    case CK_Yonah:
1393
0
    case CK_Penryn:
1394
0
    case CK_Core2:
1395
0
      return 64;
1396
1397
    // The following currently have unknown cache line sizes (but they are probably all 64):
1398
    // Core
1399
0
    case CK_None:
1400
0
      return None;
1401
0
  }
1402
0
  llvm_unreachable("Unknown CPU kind");
1403
0
}
1404
1405
bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap,
1406
                                       StringRef Constraint,
1407
6.09k
                                       unsigned Size) const {
1408
  // Strip off constraint modifiers.
1409
12.2k
  while (Constraint[0] == '=' || 
Constraint[0] == '+'6.67k
||
Constraint[0] == '&'6.11k
)
1410
6.11k
    Constraint = Constraint.substr(1);
1411
1412
6.09k
  return validateOperandSize(FeatureMap, Constraint, Size);
1413
6.09k
}
1414
1415
bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap,
1416
                                      StringRef Constraint,
1417
6.38k
                                      unsigned Size) const {
1418
6.38k
  return validateOperandSize(FeatureMap, Constraint, Size);
1419
6.38k
}
1420
1421
bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap,
1422
                                        StringRef Constraint,
1423
9.44k
                                        unsigned Size) const {
1424
9.44k
  switch (Constraint[0]) {
1425
9.27k
  default:
1426
9.27k
    break;
1427
9.27k
  case 'k':
1428
  // Registers k0-k7 (AVX512) size limit is 64 bit.
1429
30
  case 'y':
1430
30
    return Size <= 64;
1431
2
  case 'f':
1432
9
  case 't':
1433
14
  case 'u':
1434
14
    return Size <= 128;
1435
26
  case 'Y':
1436
    // 'Y' is the first character for several 2-character constraints.
1437
26
    switch (Constraint[1]) {
1438
0
    default:
1439
0
      return false;
1440
1
    case 'm':
1441
      // 'Ym' is synonymous with 'y'.
1442
5
    case 'k':
1443
5
      return Size <= 64;
1444
10
    case 'z':
1445
      // XMM0/YMM/ZMM0
1446
10
      if (hasFeatureEnabled(FeatureMap, "avx512f"))
1447
        // ZMM0 can be used if target supports AVX512F.
1448
7
        return Size <= 512U;
1449
3
      else if (hasFeatureEnabled(FeatureMap, "avx"))
1450
        // YMM0 can be used if target supports AVX.
1451
2
        return Size <= 256U;
1452
1
      else if (hasFeatureEnabled(FeatureMap, "sse"))
1453
1
        return Size <= 128U;
1454
0
      return false;
1455
5
    case 'i':
1456
8
    case 't':
1457
11
    case '2':
1458
      // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1459
11
      if (SSELevel < SSE2)
1460
0
        return false;
1461
11
      break;
1462
26
    }
1463
11
    break;
1464
30
  case 'v':
1465
101
  case 'x':
1466
101
    if (hasFeatureEnabled(FeatureMap, "avx512f"))
1467
      // 512-bit zmm registers can be used if target supports AVX512F.
1468
46
      return Size <= 512U;
1469
55
    else if (hasFeatureEnabled(FeatureMap, "avx"))
1470
      // 256-bit ymm registers can be used if target supports AVX.
1471
27
      return Size <= 256U;
1472
28
    return Size <= 128U;
1473
1474
9.44k
  }
1475
1476
9.28k
  return true;
1477
9.44k
}
1478
1479
1.98k
std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
1480
1.98k
  switch (*Constraint) {
1481
29
  case '@':
1482
29
    if (auto Len = matchAsmCCConstraint(Constraint)) {
1483
29
      std::string Converted = "{" + std::string(Constraint, Len) + "}";
1484
29
      Constraint += Len - 1;
1485
29
      return Converted;
1486
29
    }
1487
0
    return std::string(1, *Constraint);
1488
135
  case 'a':
1489
135
    return std::string("{ax}");
1490
84
  case 'b':
1491
84
    return std::string("{bx}");
1492
121
  case 'c':
1493
121
    return std::string("{cx}");
1494
84
  case 'd':
1495
84
    return std::string("{dx}");
1496
29
  case 'S':
1497
29
    return std::string("{si}");
1498
51
  case 'D':
1499
51
    return std::string("{di}");
1500
5
  case 'p': // Keep 'p' constraint (address).
1501
5
    return std::string("p");
1502
3
  case 't': // top of floating point stack.
1503
3
    return std::string("{st}");
1504
1
  case 'u':                        // second from top of floating point stack.
1505
1
    return std::string("{st(1)}"); // second from top of floating point stack.
1506
26
  case 'Y':
1507
26
    switch (Constraint[1]) {
1508
0
    default:
1509
      // Break from inner switch and fall through (copy single char),
1510
      // continue parsing after copying the current constraint into
1511
      // the return string.
1512
0
      break;
1513
4
    case 'k':
1514
5
    case 'm':
1515
10
    case 'i':
1516
13
    case 't':
1517
23
    case 'z':
1518
26
    case '2':
1519
      // "^" hints llvm that this is a 2 letter constraint.
1520
      // "Constraint++" is used to promote the string iterator
1521
      // to the next constraint.
1522
26
      return std::string("^") + std::string(Constraint++, 2);
1523
26
    }
1524
26
    
LLVM_FALLTHROUGH0
;0
1525
1.42k
  default:
1526
1.42k
    return std::string(1, *Constraint);
1527
1.98k
  }
1528
1.98k
}
1529
1530
31
void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
1531
31
  bool Only64Bit = getTriple().getArch() != llvm::Triple::x86;
1532
31
  llvm::X86::fillValidCPUArchList(Values, Only64Bit);
1533
31
}
1534
1535
5
void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const {
1536
5
  llvm::X86::fillValidTuneCPUList(Values);
1537
5
}
1538
1539
3.52k
ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const {
1540
3.52k
  return llvm::makeArrayRef(GCCRegNames);
1541
3.52k
}
1542
1543
3.05k
ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const {
1544
3.05k
  return llvm::makeArrayRef(AddlRegNames);
1545
3.05k
}
1546
1547
14.8k
ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const {
1548
14.8k
  return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin -
1549
14.8k
                                                Builtin::FirstTSBuiltin + 1);
1550
14.8k
}
1551
1552
65.8k
ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const {
1553
65.8k
  return llvm::makeArrayRef(BuiltinInfoX86,
1554
65.8k
                            X86::LastTSBuiltin - Builtin::FirstTSBuiltin);
1555
65.8k
}