Coverage Report

Created: 2022-05-17 06:19

/Users/buildslave/jenkins/workspace/coverage/llvm-project/clang/lib/CodeGen/TargetInfo.cpp
Line
Count
Source (jump to first uncovered line)
1
//===---- TargetInfo.cpp - Encapsulate target details -----------*- C++ -*-===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// These classes wrap the information about a call or function
10
// definition used to handle ABI compliancy.
11
//
12
//===----------------------------------------------------------------------===//
13
14
#include "TargetInfo.h"
15
#include "ABIInfo.h"
16
#include "CGBlocks.h"
17
#include "CGCXXABI.h"
18
#include "CGValue.h"
19
#include "CodeGenFunction.h"
20
#include "clang/AST/Attr.h"
21
#include "clang/AST/RecordLayout.h"
22
#include "clang/Basic/Builtins.h"
23
#include "clang/Basic/CodeGenOptions.h"
24
#include "clang/Basic/DiagnosticFrontend.h"
25
#include "clang/CodeGen/CGFunctionInfo.h"
26
#include "clang/CodeGen/SwiftCallingConv.h"
27
#include "llvm/ADT/SmallBitVector.h"
28
#include "llvm/ADT/StringExtras.h"
29
#include "llvm/ADT/StringSwitch.h"
30
#include "llvm/ADT/Triple.h"
31
#include "llvm/ADT/Twine.h"
32
#include "llvm/IR/DataLayout.h"
33
#include "llvm/IR/IntrinsicsNVPTX.h"
34
#include "llvm/IR/IntrinsicsS390.h"
35
#include "llvm/IR/Type.h"
36
#include "llvm/Support/MathExtras.h"
37
#include "llvm/Support/raw_ostream.h"
38
#include <algorithm> // std::sort
39
40
using namespace clang;
41
using namespace CodeGen;
42
43
// Helper for coercing an aggregate argument or return value into an integer
44
// array of the same size (including padding) and alignment.  This alternate
45
// coercion happens only for the RenderScript ABI and can be removed after
46
// runtimes that rely on it are no longer supported.
47
//
48
// RenderScript assumes that the size of the argument / return value in the IR
49
// is the same as the size of the corresponding qualified type. This helper
50
// coerces the aggregate type into an array of the same size (including
51
// padding).  This coercion is used in lieu of expansion of struct members or
52
// other canonical coercions that return a coerced-type of larger size.
53
//
54
// Ty          - The argument / return value type
55
// Context     - The associated ASTContext
56
// LLVMContext - The associated LLVMContext
57
static ABIArgInfo coerceToIntArray(QualType Ty,
58
                                   ASTContext &Context,
59
19
                                   llvm::LLVMContext &LLVMContext) {
60
  // Alignment and Size are measured in bits.
61
19
  const uint64_t Size = Context.getTypeSize(Ty);
62
19
  const uint64_t Alignment = Context.getTypeAlign(Ty);
63
19
  llvm::Type *IntType = llvm::Type::getIntNTy(LLVMContext, Alignment);
64
19
  const uint64_t NumElements = (Size + Alignment - 1) / Alignment;
65
19
  return ABIArgInfo::getDirect(llvm::ArrayType::get(IntType, NumElements));
66
19
}
67
68
static void AssignToArrayRange(CodeGen::CGBuilderTy &Builder,
69
                               llvm::Value *Array,
70
                               llvm::Value *Value,
71
                               unsigned FirstIndex,
72
31
                               unsigned LastIndex) {
73
  // Alternatively, we could emit this as a loop in the source.
74
572
  for (unsigned I = FirstIndex; I <= LastIndex; 
++I541
) {
75
541
    llvm::Value *Cell =
76
541
        Builder.CreateConstInBoundsGEP1_32(Builder.getInt8Ty(), Array, I);
77
541
    Builder.CreateAlignedStore(Value, Cell, CharUnits::One());
78
541
  }
79
31
}
80
81
176k
static bool isAggregateTypeForABI(QualType T) {
82
176k
  return !CodeGenFunction::hasScalarEvaluationKind(T) ||
83
176k
         
T->isMemberFunctionPointerType()169k
;
84
176k
}
85
86
ABIArgInfo ABIInfo::getNaturalAlignIndirect(QualType Ty, bool ByVal,
87
                                            bool Realign,
88
3.59k
                                            llvm::Type *Padding) const {
89
3.59k
  return ABIArgInfo::getIndirect(getContext().getTypeAlignInChars(Ty), ByVal,
90
3.59k
                                 Realign, Padding);
91
3.59k
}
92
93
ABIArgInfo
94
25
ABIInfo::getNaturalAlignIndirectInReg(QualType Ty, bool Realign) const {
95
25
  return ABIArgInfo::getIndirectInReg(getContext().getTypeAlignInChars(Ty),
96
25
                                      /*ByVal*/ false, Realign);
97
25
}
98
99
Address ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
100
0
                             QualType Ty) const {
101
0
  return Address::invalid();
102
0
}
103
104
7
static llvm::Type *getVAListElementType(CodeGenFunction &CGF) {
105
7
  return CGF.ConvertTypeForMem(
106
7
      CGF.getContext().getBuiltinVaListType()->getPointeeType());
107
7
}
108
109
273k
bool ABIInfo::isPromotableIntegerTypeForABI(QualType Ty) const {
110
273k
  if (Ty->isPromotableIntegerType())
111
12.9k
    return true;
112
113
260k
  if (const auto *EIT = Ty->getAs<BitIntType>())
114
339
    if (EIT->getNumBits() < getContext().getTypeSize(getContext().IntTy))
115
134
      return true;
116
117
260k
  return false;
118
260k
}
119
120
35.8k
ABIInfo::~ABIInfo() {}
121
122
/// Does the given lowering require more than the given number of
123
/// registers when expanded?
124
///
125
/// This is intended to be the basis of a reasonable basic implementation
126
/// of should{Pass,Return}IndirectlyForSwift.
127
///
128
/// For most targets, a limit of four total registers is reasonable; this
129
/// limits the amount of code required in order to move around the value
130
/// in case it wasn't produced immediately prior to the call by the caller
131
/// (or wasn't produced in exactly the right registers) or isn't used
132
/// immediately within the callee.  But some targets may need to further
133
/// limit the register count due to an inability to support that many
134
/// return registers.
135
static bool occupiesMoreThan(CodeGenTypes &cgt,
136
                             ArrayRef<llvm::Type*> scalarTypes,
137
1.05k
                             unsigned maxAllRegisters) {
138
1.05k
  unsigned intCount = 0, fpCount = 0;
139
4.18k
  for (llvm::Type *type : scalarTypes) {
140
4.18k
    if (type->isPointerTy()) {
141
0
      intCount++;
142
4.18k
    } else if (auto intTy = dyn_cast<llvm::IntegerType>(type)) {
143
2.30k
      auto ptrWidth = cgt.getTarget().getPointerWidth(0);
144
2.30k
      intCount += (intTy->getBitWidth() + ptrWidth - 1) / ptrWidth;
145
2.30k
    } else {
146
1.88k
      assert(type->isVectorTy() || type->isFloatingPointTy());
147
0
      fpCount++;
148
1.88k
    }
149
4.18k
  }
150
151
1.05k
  return (intCount + fpCount > maxAllRegisters);
152
1.05k
}
153
154
bool SwiftABIInfo::isLegalVectorTypeForSwift(CharUnits vectorSize,
155
                                             llvm::Type *eltTy,
156
440
                                             unsigned numElts) const {
157
  // The default implementation of this assumes that the target guarantees
158
  // 128-bit SIMD support but nothing more.
159
440
  return (vectorSize.getQuantity() > 8 && 
vectorSize.getQuantity() <= 16432
);
160
440
}
161
162
static CGCXXABI::RecordArgABI getRecordArgABI(const RecordType *RT,
163
19.6k
                                              CGCXXABI &CXXABI) {
164
19.6k
  const CXXRecordDecl *RD = dyn_cast<CXXRecordDecl>(RT->getDecl());
165
19.6k
  if (!RD) {
166
3.90k
    if (!RT->getDecl()->canPassInRegisters())
167
16
      return CGCXXABI::RAA_Indirect;
168
3.88k
    return CGCXXABI::RAA_Default;
169
3.90k
  }
170
15.7k
  return CXXABI.getRecordArgABI(RD);
171
19.6k
}
172
173
static CGCXXABI::RecordArgABI getRecordArgABI(QualType T,
174
8.62k
                                              CGCXXABI &CXXABI) {
175
8.62k
  const RecordType *RT = T->getAs<RecordType>();
176
8.62k
  if (!RT)
177
3.61k
    return CGCXXABI::RAA_Default;
178
5.00k
  return getRecordArgABI(RT, CXXABI);
179
8.62k
}
180
181
static bool classifyReturnType(const CGCXXABI &CXXABI, CGFunctionInfo &FI,
182
213k
                               const ABIInfo &Info) {
183
213k
  QualType Ty = FI.getReturnType();
184
185
213k
  if (const auto *RT = Ty->getAs<RecordType>())
186
6.14k
    if (!isa<CXXRecordDecl>(RT->getDecl()) &&
187
6.14k
        
!RT->getDecl()->canPassInRegisters()1.27k
) {
188
12
      FI.getReturnInfo() = Info.getNaturalAlignIndirect(Ty);
189
12
      return true;
190
12
    }
191
192
213k
  return CXXABI.classifyReturnType(FI);
193
213k
}
194
195
/// Pass transparent unions as if they were the type of the first element. Sema
196
/// should ensure that all elements of the union have the same "machine type".
197
425k
static QualType useFirstFieldIfTransparentUnion(QualType Ty) {
198
425k
  if (const RecordType *UT = Ty->getAsUnionType()) {
199
141
    const RecordDecl *UD = UT->getDecl();
200
141
    if (UD->hasAttr<TransparentUnionAttr>()) {
201
18
      assert(!UD->field_empty() && "sema created an empty transparent union");
202
0
      return UD->field_begin()->getType();
203
18
    }
204
141
  }
205
425k
  return Ty;
206
425k
}
207
208
259k
CGCXXABI &ABIInfo::getCXXABI() const {
209
259k
  return CGT.getCXXABI();
210
259k
}
211
212
423k
ASTContext &ABIInfo::getContext() const {
213
423k
  return CGT.getContext();
214
423k
}
215
216
17.2k
llvm::LLVMContext &ABIInfo::getVMContext() const {
217
17.2k
  return CGT.getLLVMContext();
218
17.2k
}
219
220
22.1k
const llvm::DataLayout &ABIInfo::getDataLayout() const {
221
22.1k
  return CGT.getDataLayout();
222
22.1k
}
223
224
34.3k
const TargetInfo &ABIInfo::getTarget() const {
225
34.3k
  return CGT.getTarget();
226
34.3k
}
227
228
1.07k
const CodeGenOptions &ABIInfo::getCodeGenOpts() const {
229
1.07k
  return CGT.getCodeGenOpts();
230
1.07k
}
231
232
5.03k
bool ABIInfo::isAndroid() const { return getTarget().getTriple().isAndroid(); }
233
234
0
bool ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
235
0
  return false;
236
0
}
237
238
bool ABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base,
239
0
                                                uint64_t Members) const {
240
0
  return false;
241
0
}
242
243
0
LLVM_DUMP_METHOD void ABIArgInfo::dump() const {
244
0
  raw_ostream &OS = llvm::errs();
245
0
  OS << "(ABIArgInfo Kind=";
246
0
  switch (TheKind) {
247
0
  case Direct:
248
0
    OS << "Direct Type=";
249
0
    if (llvm::Type *Ty = getCoerceToType())
250
0
      Ty->print(OS);
251
0
    else
252
0
      OS << "null";
253
0
    break;
254
0
  case Extend:
255
0
    OS << "Extend";
256
0
    break;
257
0
  case Ignore:
258
0
    OS << "Ignore";
259
0
    break;
260
0
  case InAlloca:
261
0
    OS << "InAlloca Offset=" << getInAllocaFieldIndex();
262
0
    break;
263
0
  case Indirect:
264
0
    OS << "Indirect Align=" << getIndirectAlign().getQuantity()
265
0
       << " ByVal=" << getIndirectByVal()
266
0
       << " Realign=" << getIndirectRealign();
267
0
    break;
268
0
  case IndirectAliased:
269
0
    OS << "Indirect Align=" << getIndirectAlign().getQuantity()
270
0
       << " AadrSpace=" << getIndirectAddrSpace()
271
0
       << " Realign=" << getIndirectRealign();
272
0
    break;
273
0
  case Expand:
274
0
    OS << "Expand";
275
0
    break;
276
0
  case CoerceAndExpand:
277
0
    OS << "CoerceAndExpand Type=";
278
0
    getCoerceAndExpandType()->print(OS);
279
0
    break;
280
0
  }
281
0
  OS << ")\n";
282
0
}
283
284
// Dynamically round a pointer up to a multiple of the given alignment.
285
static llvm::Value *emitRoundPointerUpToAlignment(CodeGenFunction &CGF,
286
                                                  llvm::Value *Ptr,
287
123
                                                  CharUnits Align) {
288
123
  llvm::Value *PtrAsInt = Ptr;
289
  // OverflowArgArea = (OverflowArgArea + Align - 1) & -Align;
290
123
  PtrAsInt = CGF.Builder.CreatePtrToInt(PtrAsInt, CGF.IntPtrTy);
291
123
  PtrAsInt = CGF.Builder.CreateAdd(PtrAsInt,
292
123
        llvm::ConstantInt::get(CGF.IntPtrTy, Align.getQuantity() - 1));
293
123
  PtrAsInt = CGF.Builder.CreateAnd(PtrAsInt,
294
123
           llvm::ConstantInt::get(CGF.IntPtrTy, -Align.getQuantity()));
295
123
  PtrAsInt = CGF.Builder.CreateIntToPtr(PtrAsInt,
296
123
                                        Ptr->getType(),
297
123
                                        Ptr->getName() + ".aligned");
298
123
  return PtrAsInt;
299
123
}
300
301
/// Emit va_arg for a platform using the common void* representation,
302
/// where arguments are simply emitted in an array of slots on the stack.
303
///
304
/// This version implements the core direct-value passing rules.
305
///
306
/// \param SlotSize - The size and alignment of a stack slot.
307
///   Each argument will be allocated to a multiple of this number of
308
///   slots, and all the slots will be aligned to this value.
309
/// \param AllowHigherAlign - The slot alignment is not a cap;
310
///   an argument type with an alignment greater than the slot size
311
///   will be emitted on a higher-alignment address, potentially
312
///   leaving one or more empty slots behind as padding.  If this
313
///   is false, the returned address might be less-aligned than
314
///   DirectAlign.
315
static Address emitVoidPtrDirectVAArg(CodeGenFunction &CGF,
316
                                      Address VAListAddr,
317
                                      llvm::Type *DirectTy,
318
                                      CharUnits DirectSize,
319
                                      CharUnits DirectAlign,
320
                                      CharUnits SlotSize,
321
307
                                      bool AllowHigherAlign) {
322
  // Cast the element type to i8* if necessary.  Some platforms define
323
  // va_list as a struct containing an i8* instead of just an i8*.
324
307
  if (VAListAddr.getElementType() != CGF.Int8PtrTy)
325
59
    VAListAddr = CGF.Builder.CreateElementBitCast(VAListAddr, CGF.Int8PtrTy);
326
327
307
  llvm::Value *Ptr = CGF.Builder.CreateLoad(VAListAddr, "argp.cur");
328
329
  // If the CC aligns values higher than the slot size, do so if needed.
330
307
  Address Addr = Address::invalid();
331
307
  if (AllowHigherAlign && 
DirectAlign > SlotSize270
) {
332
104
    Addr = Address(emitRoundPointerUpToAlignment(CGF, Ptr, DirectAlign),
333
104
                   CGF.Int8Ty, DirectAlign);
334
203
  } else {
335
203
    Addr = Address(Ptr, CGF.Int8Ty, SlotSize);
336
203
  }
337
338
  // Advance the pointer past the argument, then store that back.
339
307
  CharUnits FullDirectSize = DirectSize.alignTo(SlotSize);
340
307
  Address NextPtr =
341
307
      CGF.Builder.CreateConstInBoundsByteGEP(Addr, FullDirectSize, "argp.next");
342
307
  CGF.Builder.CreateStore(NextPtr.getPointer(), VAListAddr);
343
344
  // If the argument is smaller than a slot, and this is a big-endian
345
  // target, the argument will be right-adjusted in its slot.
346
307
  if (DirectSize < SlotSize && 
CGF.CGM.getDataLayout().isBigEndian()41
&&
347
307
      
!DirectTy->isStructTy()6
) {
348
0
    Addr = CGF.Builder.CreateConstInBoundsByteGEP(Addr, SlotSize - DirectSize);
349
0
  }
350
351
307
  Addr = CGF.Builder.CreateElementBitCast(Addr, DirectTy);
352
307
  return Addr;
353
307
}
354
355
/// Emit va_arg for a platform using the common void* representation,
356
/// where arguments are simply emitted in an array of slots on the stack.
357
///
358
/// \param IsIndirect - Values of this type are passed indirectly.
359
/// \param ValueInfo - The size and alignment of this type, generally
360
///   computed with getContext().getTypeInfoInChars(ValueTy).
361
/// \param SlotSizeAndAlign - The size and alignment of a stack slot.
362
///   Each argument will be allocated to a multiple of this number of
363
///   slots, and all the slots will be aligned to this value.
364
/// \param AllowHigherAlign - The slot alignment is not a cap;
365
///   an argument type with an alignment greater than the slot size
366
///   will be emitted on a higher-alignment address, potentially
367
///   leaving one or more empty slots behind as padding.
368
static Address emitVoidPtrVAArg(CodeGenFunction &CGF, Address VAListAddr,
369
                                QualType ValueTy, bool IsIndirect,
370
                                TypeInfoChars ValueInfo,
371
                                CharUnits SlotSizeAndAlign,
372
307
                                bool AllowHigherAlign) {
373
  // The size and alignment of the value that was passed directly.
374
307
  CharUnits DirectSize, DirectAlign;
375
307
  if (IsIndirect) {
376
44
    DirectSize = CGF.getPointerSize();
377
44
    DirectAlign = CGF.getPointerAlign();
378
263
  } else {
379
263
    DirectSize = ValueInfo.Width;
380
263
    DirectAlign = ValueInfo.Align;
381
263
  }
382
383
  // Cast the address we've calculated to the right type.
384
307
  llvm::Type *DirectTy = CGF.ConvertTypeForMem(ValueTy), *ElementTy = DirectTy;
385
307
  if (IsIndirect)
386
44
    DirectTy = DirectTy->getPointerTo(0);
387
388
307
  Address Addr =
389
307
      emitVoidPtrDirectVAArg(CGF, VAListAddr, DirectTy, DirectSize, DirectAlign,
390
307
                             SlotSizeAndAlign, AllowHigherAlign);
391
392
307
  if (IsIndirect) {
393
44
    Addr = Address(CGF.Builder.CreateLoad(Addr), ElementTy, ValueInfo.Align);
394
44
  }
395
396
307
  return Addr;
397
307
}
398
399
static Address complexTempStructure(CodeGenFunction &CGF, Address VAListAddr,
400
                                    QualType Ty, CharUnits SlotSize,
401
0
                                    CharUnits EltSize, const ComplexType *CTy) {
402
0
  Address Addr =
403
0
      emitVoidPtrDirectVAArg(CGF, VAListAddr, CGF.Int8Ty, SlotSize * 2,
404
0
                             SlotSize, SlotSize, /*AllowHigher*/ true);
405
406
0
  Address RealAddr = Addr;
407
0
  Address ImagAddr = RealAddr;
408
0
  if (CGF.CGM.getDataLayout().isBigEndian()) {
409
0
    RealAddr =
410
0
        CGF.Builder.CreateConstInBoundsByteGEP(RealAddr, SlotSize - EltSize);
411
0
    ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(ImagAddr,
412
0
                                                      2 * SlotSize - EltSize);
413
0
  } else {
414
0
    ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(RealAddr, SlotSize);
415
0
  }
416
417
0
  llvm::Type *EltTy = CGF.ConvertTypeForMem(CTy->getElementType());
418
0
  RealAddr = CGF.Builder.CreateElementBitCast(RealAddr, EltTy);
419
0
  ImagAddr = CGF.Builder.CreateElementBitCast(ImagAddr, EltTy);
420
0
  llvm::Value *Real = CGF.Builder.CreateLoad(RealAddr, ".vareal");
421
0
  llvm::Value *Imag = CGF.Builder.CreateLoad(ImagAddr, ".vaimag");
422
423
0
  Address Temp = CGF.CreateMemTemp(Ty, "vacplx");
424
0
  CGF.EmitStoreOfComplex({Real, Imag}, CGF.MakeAddrLValue(Temp, Ty),
425
0
                         /*init*/ true);
426
0
  return Temp;
427
0
}
428
429
static Address emitMergePHI(CodeGenFunction &CGF,
430
                            Address Addr1, llvm::BasicBlock *Block1,
431
                            Address Addr2, llvm::BasicBlock *Block2,
432
409
                            const llvm::Twine &Name = "") {
433
409
  assert(Addr1.getType() == Addr2.getType());
434
0
  llvm::PHINode *PHI = CGF.Builder.CreatePHI(Addr1.getType(), 2, Name);
435
409
  PHI->addIncoming(Addr1.getPointer(), Block1);
436
409
  PHI->addIncoming(Addr2.getPointer(), Block2);
437
409
  CharUnits Align = std::min(Addr1.getAlignment(), Addr2.getAlignment());
438
409
  return Address(PHI, Addr1.getElementType(), Align);
439
409
}
440
441
35.5k
TargetCodeGenInfo::~TargetCodeGenInfo() = default;
442
443
// If someone can figure out a general rule for this, that would be great.
444
// It's probably just doomed to be platform-dependent, though.
445
5
unsigned TargetCodeGenInfo::getSizeOfUnwindException() const {
446
  // Verified for:
447
  //   x86-64     FreeBSD, Linux, Darwin
448
  //   x86-32     FreeBSD, Linux, Darwin
449
  //   PowerPC    Linux, Darwin
450
  //   ARM        Darwin (*not* EABI)
451
  //   AArch64    Linux
452
5
  return 32;
453
5
}
454
455
bool TargetCodeGenInfo::isNoProtoCallVariadic(const CallArgList &args,
456
103
                                     const FunctionNoProtoType *fnType) const {
457
  // The following conventions are known to require this to be false:
458
  //   x86_stdcall
459
  //   MIPS
460
  // For everything else, we just prefer false unless we opt out.
461
103
  return false;
462
103
}
463
464
void
465
TargetCodeGenInfo::getDependentLibraryOption(llvm::StringRef Lib,
466
2
                                             llvm::SmallString<24> &Opt) const {
467
  // This assumes the user is passing a library name like "rt" instead of a
468
  // filename like "librt.a/so", and that they don't care whether it's static or
469
  // dynamic.
470
2
  Opt = "-l";
471
2
  Opt += Lib;
472
2
}
473
474
59
unsigned TargetCodeGenInfo::getOpenCLKernelCallingConv() const {
475
  // OpenCL kernels are called via an explicit runtime API with arguments
476
  // set with clSetKernelArg(), not as normal sub-functions.
477
  // Return SPIR_KERNEL by default as the kernel calling convention to
478
  // ensure the fingerprint is fixed such way that each OpenCL argument
479
  // gets one matching argument in the produced kernel function argument
480
  // list to enable feasible implementation of clSetKernelArg() with
481
  // aggregates etc. In case we would use the default C calling conv here,
482
  // clSetKernelArg() might break depending on the target-specific
483
  // conventions; different targets might split structs passed as values
484
  // to multiple function arguments etc.
485
59
  return llvm::CallingConv::SPIR_KERNEL;
486
59
}
487
488
llvm::Constant *TargetCodeGenInfo::getNullPointer(const CodeGen::CodeGenModule &CGM,
489
34.4k
    llvm::PointerType *T, QualType QT) const {
490
34.4k
  return llvm::ConstantPointerNull::get(T);
491
34.4k
}
492
493
LangAS TargetCodeGenInfo::getGlobalVarAddressSpace(CodeGenModule &CGM,
494
70.5k
                                                   const VarDecl *D) const {
495
70.5k
  assert(!CGM.getLangOpts().OpenCL &&
496
70.5k
         !(CGM.getLangOpts().CUDA && CGM.getLangOpts().CUDAIsDevice) &&
497
70.5k
         "Address space agnostic languages only");
498
70.5k
  return D ? 
D->getType().getAddressSpace()68.5k
:
LangAS::Default1.97k
;
499
70.5k
}
500
501
llvm::Value *TargetCodeGenInfo::performAddrSpaceCast(
502
    CodeGen::CodeGenFunction &CGF, llvm::Value *Src, LangAS SrcAddr,
503
6.22k
    LangAS DestAddr, llvm::Type *DestTy, bool isNonNull) const {
504
  // Since target may map different address spaces in AST to the same address
505
  // space, an address space conversion may end up as a bitcast.
506
6.22k
  if (auto *C = dyn_cast<llvm::Constant>(Src))
507
56
    return performAddrSpaceCast(CGF.CGM, C, SrcAddr, DestAddr, DestTy);
508
  // Try to preserve the source's name to make IR more readable.
509
6.16k
  return CGF.Builder.CreatePointerBitCastOrAddrSpaceCast(
510
6.16k
      Src, DestTy, Src->hasName() ? 
Src->getName() + ".ascast"5.95k
:
""209
);
511
6.22k
}
512
513
llvm::Constant *
514
TargetCodeGenInfo::performAddrSpaceCast(CodeGenModule &CGM, llvm::Constant *Src,
515
                                        LangAS SrcAddr, LangAS DestAddr,
516
266
                                        llvm::Type *DestTy) const {
517
  // Since target may map different address spaces in AST to the same address
518
  // space, an address space conversion may end up as a bitcast.
519
266
  return llvm::ConstantExpr::getPointerCast(Src, DestTy);
520
266
}
521
522
llvm::SyncScope::ID
523
TargetCodeGenInfo::getLLVMSyncScopeID(const LangOptions &LangOpts,
524
                                      SyncScope Scope,
525
                                      llvm::AtomicOrdering Ordering,
526
0
                                      llvm::LLVMContext &Ctx) const {
527
0
  return Ctx.getOrInsertSyncScopeID(""); /* default sync scope */
528
0
}
529
530
static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays);
531
532
/// isEmptyField - Return true iff a the field is "empty", that is it
533
/// is an unnamed bit-field or an (array of) empty record(s).
534
static bool isEmptyField(ASTContext &Context, const FieldDecl *FD,
535
5.27k
                         bool AllowArrays) {
536
5.27k
  if (FD->isUnnamedBitfield())
537
127
    return true;
538
539
5.14k
  QualType FT = FD->getType();
540
541
  // Constant arrays of empty records count as empty, strip them off.
542
  // Constant arrays of zero length always count as empty.
543
5.14k
  bool WasArray = false;
544
5.14k
  if (AllowArrays)
545
6.85k
    
while (const ConstantArrayType *4.97k
AT = Context.getAsConstantArrayType(FT)) {
546
1.89k
      if (AT->getSize() == 0)
547
11
        return true;
548
1.88k
      FT = AT->getElementType();
549
      // The [[no_unique_address]] special case below does not apply to
550
      // arrays of C++ empty records, so we need to remember this fact.
551
1.88k
      WasArray = true;
552
1.88k
    }
553
554
5.13k
  const RecordType *RT = FT->getAs<RecordType>();
555
5.13k
  if (!RT)
556
4.72k
    return false;
557
558
  // C++ record fields are never empty, at least in the Itanium ABI.
559
  //
560
  // FIXME: We should use a predicate for whether this behavior is true in the
561
  // current ABI.
562
  //
563
  // The exception to the above rule are fields marked with the
564
  // [[no_unique_address]] attribute (since C++20).  Those do count as empty
565
  // according to the Itanium ABI.  The exception applies only to records,
566
  // not arrays of records, so we must also check whether we stripped off an
567
  // array type above.
568
410
  if (isa<CXXRecordDecl>(RT->getDecl()) &&
569
410
      
(85
WasArray85
||
!FD->hasAttr<NoUniqueAddressAttr>()68
))
570
78
    return false;
571
572
332
  return isEmptyRecord(Context, FT, AllowArrays);
573
410
}
574
575
/// isEmptyRecord - Return true iff a structure contains only empty
576
/// fields. Note that a structure with a flexible array member is not
577
/// considered empty.
578
9.27k
static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays) {
579
9.27k
  const RecordType *RT = T->getAs<RecordType>();
580
9.27k
  if (!RT)
581
4.61k
    return false;
582
4.66k
  const RecordDecl *RD = RT->getDecl();
583
4.66k
  if (RD->hasFlexibleArrayMember())
584
10
    return false;
585
586
  // If this is a C++ record, check the bases first.
587
4.65k
  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
588
1.02k
    for (const auto &I : CXXRD->bases())
589
115
      if (!isEmptyRecord(Context, I.getType(), true))
590
107
        return false;
591
592
4.54k
  for (const auto *I : RD->fields())
593
4.21k
    if (!isEmptyField(Context, I, AllowArrays))
594
3.92k
      return false;
595
617
  return true;
596
4.54k
}
597
598
/// isSingleElementStruct - Determine if a structure is a "single
599
/// element struct", i.e. it has exactly one non-empty field or
600
/// exactly one field which is itself a single element
601
/// struct. Structures with flexible array members are never
602
/// considered single element structs.
603
///
604
/// \return The field declaration for the single non-empty field, if
605
/// it exists.
606
66.3k
static const Type *isSingleElementStruct(QualType T, ASTContext &Context) {
607
66.3k
  const RecordType *RT = T->getAs<RecordType>();
608
66.3k
  if (!RT)
609
65.6k
    return nullptr;
610
611
728
  const RecordDecl *RD = RT->getDecl();
612
728
  if (RD->hasFlexibleArrayMember())
613
0
    return nullptr;
614
615
728
  const Type *Found = nullptr;
616
617
  // If this is a C++ record, check the bases first.
618
728
  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
619
272
    for (const auto &I : CXXRD->bases()) {
620
      // Ignore empty records.
621
49
      if (isEmptyRecord(Context, I.getType(), true))
622
6
        continue;
623
624
      // If we already found an element then this isn't a single-element struct.
625
43
      if (Found)
626
11
        return nullptr;
627
628
      // If this is non-empty and not a single element struct, the composite
629
      // cannot be a single element struct.
630
32
      Found = isSingleElementStruct(I.getType(), Context);
631
32
      if (!Found)
632
9
        return nullptr;
633
32
    }
634
272
  }
635
636
  // Check for single element.
637
948
  
for (const auto *FD : RD->fields())708
{
638
948
    QualType FT = FD->getType();
639
640
    // Ignore empty fields.
641
948
    if (isEmptyField(Context, FD, true))
642
19
      continue;
643
644
    // If we already found an element then this isn't a single-element
645
    // struct.
646
929
    if (Found)
647
258
      return nullptr;
648
649
    // Treat single element arrays as the element.
650
685
    
while (const ConstantArrayType *671
AT = Context.getAsConstantArrayType(FT)) {
651
188
      if (AT->getSize().getZExtValue() != 1)
652
174
        break;
653
14
      FT = AT->getElementType();
654
14
    }
655
656
671
    if (!isAggregateTypeForABI(FT)) {
657
479
      Found = FT.getTypePtr();
658
479
    } else {
659
192
      Found = isSingleElementStruct(FT, Context);
660
192
      if (!Found)
661
190
        return nullptr;
662
192
    }
663
671
  }
664
665
  // We don't consider a struct a single-element struct if it has
666
  // padding beyond the element type.
667
260
  if (Found && 
Context.getTypeSize(Found) != Context.getTypeSize(T)235
)
668
3
    return nullptr;
669
670
257
  return Found;
671
260
}
672
673
namespace {
674
Address EmitVAArgInstr(CodeGenFunction &CGF, Address VAListAddr, QualType Ty,
675
10
                       const ABIArgInfo &AI) {
676
  // This default implementation defers to the llvm backend's va_arg
677
  // instruction. It can handle only passing arguments directly
678
  // (typically only handled in the backend for primitive types), or
679
  // aggregates passed indirectly by pointer (NOTE: if the "byval"
680
  // flag has ABI impact in the callee, this implementation cannot
681
  // work.)
682
683
  // Only a few cases are covered here at the moment -- those needed
684
  // by the default abi.
685
10
  llvm::Value *Val;
686
687
10
  if (AI.isIndirect()) {
688
1
    assert(!AI.getPaddingType() &&
689
1
           "Unexpected PaddingType seen in arginfo in generic VAArg emitter!");
690
0
    assert(
691
1
        !AI.getIndirectRealign() &&
692
1
        "Unexpected IndirectRealign seen in arginfo in generic VAArg emitter!");
693
694
0
    auto TyInfo = CGF.getContext().getTypeInfoInChars(Ty);
695
1
    CharUnits TyAlignForABI = TyInfo.Align;
696
697
1
    llvm::Type *ElementTy = CGF.ConvertTypeForMem(Ty);
698
1
    llvm::Type *BaseTy = llvm::PointerType::getUnqual(ElementTy);
699
1
    llvm::Value *Addr =
700
1
        CGF.Builder.CreateVAArg(VAListAddr.getPointer(), BaseTy);
701
1
    return Address(Addr, ElementTy, TyAlignForABI);
702
9
  } else {
703
9
    assert((AI.isDirect() || AI.isExtend()) &&
704
9
           "Unexpected ArgInfo Kind in generic VAArg emitter!");
705
706
0
    assert(!AI.getInReg() &&
707
9
           "Unexpected InReg seen in arginfo in generic VAArg emitter!");
708
0
    assert(!AI.getPaddingType() &&
709
9
           "Unexpected PaddingType seen in arginfo in generic VAArg emitter!");
710
0
    assert(!AI.getDirectOffset() &&
711
9
           "Unexpected DirectOffset seen in arginfo in generic VAArg emitter!");
712
0
    assert(!AI.getCoerceToType() &&
713
9
           "Unexpected CoerceToType seen in arginfo in generic VAArg emitter!");
714
715
0
    Address Temp = CGF.CreateMemTemp(Ty, "varet");
716
9
    Val = CGF.Builder.CreateVAArg(VAListAddr.getPointer(),
717
9
                                  CGF.ConvertTypeForMem(Ty));
718
9
    CGF.Builder.CreateStore(Val, Temp);
719
9
    return Temp;
720
9
  }
721
10
}
722
723
/// DefaultABIInfo - The default implementation for ABI specific
724
/// details. This implementation provides information which results in
725
/// self-consistent and sensible LLVM IR generation, but does not
726
/// conform to any particular ABI.
727
class DefaultABIInfo : public ABIInfo {
728
public:
729
775
  DefaultABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}
730
731
  ABIArgInfo classifyReturnType(QualType RetTy) const;
732
  ABIArgInfo classifyArgumentType(QualType RetTy) const;
733
734
643
  void computeInfo(CGFunctionInfo &FI) const override {
735
643
    if (!getCXXABI().classifyReturnType(FI))
736
642
      FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
737
643
    for (auto &I : FI.arguments())
738
892
      I.info = classifyArgumentType(I.type);
739
643
  }
740
741
  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
742
3
                    QualType Ty) const override {
743
3
    return EmitVAArgInstr(CGF, VAListAddr, Ty, classifyArgumentType(Ty));
744
3
  }
745
};
746
747
class DefaultTargetCodeGenInfo : public TargetCodeGenInfo {
748
public:
749
  DefaultTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
750
21
      : TargetCodeGenInfo(std::make_unique<DefaultABIInfo>(CGT)) {}
751
};
752
753
2.14k
ABIArgInfo DefaultABIInfo::classifyArgumentType(QualType Ty) const {
754
2.14k
  Ty = useFirstFieldIfTransparentUnion(Ty);
755
756
2.14k
  if (isAggregateTypeForABI(Ty)) {
757
    // Records with non-trivial destructors/copy-constructors should not be
758
    // passed by value.
759
106
    if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
760
2
      return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
761
762
104
    return getNaturalAlignIndirect(Ty);
763
106
  }
764
765
  // Treat an enum type as its underlying type.
766
2.04k
  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
767
8
    Ty = EnumTy->getDecl()->getIntegerType();
768
769
2.04k
  ASTContext &Context = getContext();
770
2.04k
  if (const auto *EIT = Ty->getAs<BitIntType>())
771
48
    if (EIT->getNumBits() >
772
48
        Context.getTypeSize(Context.getTargetInfo().hasInt128Type()
773
48
                                ? 
Context.Int128Ty12
774
48
                                : 
Context.LongLongTy36
))
775
12
      return getNaturalAlignIndirect(Ty);
776
777
2.02k
  return (isPromotableIntegerTypeForABI(Ty) ? 
ABIArgInfo::getExtend(Ty)70
778
2.02k
                                            : 
ABIArgInfo::getDirect()1.95k
);
779
2.04k
}
780
781
1.86k
ABIArgInfo DefaultABIInfo::classifyReturnType(QualType RetTy) const {
782
1.86k
  if (RetTy->isVoidType())
783
1.01k
    return ABIArgInfo::getIgnore();
784
785
846
  if (isAggregateTypeForABI(RetTy))
786
55
    return getNaturalAlignIndirect(RetTy);
787
788
  // Treat an enum type as its underlying type.
789
791
  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
790
0
    RetTy = EnumTy->getDecl()->getIntegerType();
791
792
791
  if (const auto *EIT = RetTy->getAs<BitIntType>())
793
40
    if (EIT->getNumBits() >
794
40
        getContext().getTypeSize(getContext().getTargetInfo().hasInt128Type()
795
40
                                     ? 
getContext().Int128Ty8
796
40
                                     : 
getContext().LongLongTy32
))
797
16
      return getNaturalAlignIndirect(RetTy);
798
799
775
  return (isPromotableIntegerTypeForABI(RetTy) ? 
ABIArgInfo::getExtend(RetTy)82
800
775
                                               : 
ABIArgInfo::getDirect()693
);
801
791
}
802
803
//===----------------------------------------------------------------------===//
804
// WebAssembly ABI Implementation
805
//
806
// This is a very simple ABI that relies a lot on DefaultABIInfo.
807
//===----------------------------------------------------------------------===//
808
809
class WebAssemblyABIInfo final : public SwiftABIInfo {
810
public:
811
  enum ABIKind {
812
    MVP = 0,
813
    ExperimentalMV = 1,
814
  };
815
816
private:
817
  DefaultABIInfo defaultInfo;
818
  ABIKind Kind;
819
820
public:
821
  explicit WebAssemblyABIInfo(CodeGen::CodeGenTypes &CGT, ABIKind Kind)
822
38
      : SwiftABIInfo(CGT), defaultInfo(CGT), Kind(Kind) {}
823
824
private:
825
  ABIArgInfo classifyReturnType(QualType RetTy) const;
826
  ABIArgInfo classifyArgumentType(QualType Ty) const;
827
828
  // DefaultABIInfo's classifyReturnType and classifyArgumentType are
829
  // non-virtual, but computeInfo and EmitVAArg are virtual, so we
830
  // overload them.
831
350
  void computeInfo(CGFunctionInfo &FI) const override {
832
350
    if (!getCXXABI().classifyReturnType(FI))
833
342
      FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
834
350
    for (auto &Arg : FI.arguments())
835
336
      Arg.info = classifyArgumentType(Arg.type);
836
350
  }
837
838
  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
839
                    QualType Ty) const override;
840
841
  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
842
0
                                    bool asReturnValue) const override {
843
0
    return occupiesMoreThan(CGT, scalars, /*total*/ 4);
844
0
  }
845
846
0
  bool isSwiftErrorInRegister() const override {
847
0
    return false;
848
0
  }
849
};
850
851
class WebAssemblyTargetCodeGenInfo final : public TargetCodeGenInfo {
852
public:
853
  explicit WebAssemblyTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
854
                                        WebAssemblyABIInfo::ABIKind K)
855
38
      : TargetCodeGenInfo(std::make_unique<WebAssemblyABIInfo>(CGT, K)) {}
856
857
  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
858
1.20k
                           CodeGen::CodeGenModule &CGM) const override {
859
1.20k
    TargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
860
1.20k
    if (const auto *FD = dyn_cast_or_null<FunctionDecl>(D)) {
861
1.03k
      if (const auto *Attr = FD->getAttr<WebAssemblyImportModuleAttr>()) {
862
1
        llvm::Function *Fn = cast<llvm::Function>(GV);
863
1
        llvm::AttrBuilder B(GV->getContext());
864
1
        B.addAttribute("wasm-import-module", Attr->getImportModule());
865
1
        Fn->addFnAttrs(B);
866
1
      }
867
1.03k
      if (const auto *Attr = FD->getAttr<WebAssemblyImportNameAttr>()) {
868
1
        llvm::Function *Fn = cast<llvm::Function>(GV);
869
1
        llvm::AttrBuilder B(GV->getContext());
870
1
        B.addAttribute("wasm-import-name", Attr->getImportName());
871
1
        Fn->addFnAttrs(B);
872
1
      }
873
1.03k
      if (const auto *Attr = FD->getAttr<WebAssemblyExportNameAttr>()) {
874
2
        llvm::Function *Fn = cast<llvm::Function>(GV);
875
2
        llvm::AttrBuilder B(GV->getContext());
876
2
        B.addAttribute("wasm-export-name", Attr->getExportName());
877
2
        Fn->addFnAttrs(B);
878
2
      }
879
1.03k
    }
880
881
1.20k
    if (auto *FD = dyn_cast_or_null<FunctionDecl>(D)) {
882
1.03k
      llvm::Function *Fn = cast<llvm::Function>(GV);
883
1.03k
      if (!FD->doesThisDeclarationHaveABody() && 
!FD->hasPrototype()68
)
884
0
        Fn->addFnAttr("no-prototype");
885
1.03k
    }
886
1.20k
  }
887
};
888
889
/// Classify argument of given type \p Ty.
890
336
ABIArgInfo WebAssemblyABIInfo::classifyArgumentType(QualType Ty) const {
891
336
  Ty = useFirstFieldIfTransparentUnion(Ty);
892
893
336
  if (isAggregateTypeForABI(Ty)) {
894
    // Records with non-trivial destructors/copy-constructors should not be
895
    // passed by value.
896
42
    if (auto RAA = getRecordArgABI(Ty, getCXXABI()))
897
8
      return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
898
    // Ignore empty structs/unions.
899
34
    if (isEmptyRecord(getContext(), Ty, true))
900
4
      return ABIArgInfo::getIgnore();
901
    // Lower single-element structs to just pass a regular value. TODO: We
902
    // could do reasonable-size multiple-element structs too, using getExpand(),
903
    // though watch out for things like bitfields.
904
30
    if (const Type *SeltTy = isSingleElementStruct(Ty, getContext()))
905
11
      return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
906
    // For the experimental multivalue ABI, fully expand all other aggregates
907
19
    if (Kind == ABIKind::ExperimentalMV) {
908
3
      const RecordType *RT = Ty->getAs<RecordType>();
909
3
      assert(RT);
910
0
      bool HasBitField = false;
911
5
      for (auto *Field : RT->getDecl()->fields()) {
912
5
        if (Field->isBitField()) {
913
1
          HasBitField = true;
914
1
          break;
915
1
        }
916
5
      }
917
3
      if (!HasBitField)
918
2
        return ABIArgInfo::getExpand();
919
3
    }
920
19
  }
921
922
  // Otherwise just do the default thing.
923
311
  return defaultInfo.classifyArgumentType(Ty);
924
336
}
925
926
342
ABIArgInfo WebAssemblyABIInfo::classifyReturnType(QualType RetTy) const {
927
342
  if (isAggregateTypeForABI(RetTy)) {
928
    // Records with non-trivial destructors/copy-constructors should not be
929
    // returned by value.
930
30
    if (!getRecordArgABI(RetTy, getCXXABI())) {
931
      // Ignore empty structs/unions.
932
30
      if (isEmptyRecord(getContext(), RetTy, true))
933
4
        return ABIArgInfo::getIgnore();
934
      // Lower single-element structs to just return a regular value. TODO: We
935
      // could do reasonable-size multiple-element structs too, using
936
      // ABIArgInfo::getDirect().
937
26
      if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
938
11
        return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
939
      // For the experimental multivalue ABI, return all other aggregates
940
15
      if (Kind == ABIKind::ExperimentalMV)
941
3
        return ABIArgInfo::getDirect();
942
15
    }
943
30
  }
944
945
  // Otherwise just do the default thing.
946
324
  return defaultInfo.classifyReturnType(RetTy);
947
342
}
948
949
Address WebAssemblyABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
950
5
                                      QualType Ty) const {
951
5
  bool IsIndirect = isAggregateTypeForABI(Ty) &&
952
5
                    
!isEmptyRecord(getContext(), Ty, true)3
&&
953
5
                    
!isSingleElementStruct(Ty, getContext())2
;
954
5
  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect,
955
5
                          getContext().getTypeInfoInChars(Ty),
956
5
                          CharUnits::fromQuantity(4),
957
5
                          /*AllowHigherAlign=*/true);
958
5
}
959
960
//===----------------------------------------------------------------------===//
961
// le32/PNaCl bitcode ABI Implementation
962
//
963
// This is a simplified version of the x86_32 ABI.  Arguments and return values
964
// are always passed on the stack.
965
//===----------------------------------------------------------------------===//
966
967
class PNaClABIInfo : public ABIInfo {
968
 public:
969
3
  PNaClABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}
970
971
  ABIArgInfo classifyReturnType(QualType RetTy) const;
972
  ABIArgInfo classifyArgumentType(QualType RetTy) const;
973
974
  void computeInfo(CGFunctionInfo &FI) const override;
975
  Address EmitVAArg(CodeGenFunction &CGF,
976
                    Address VAListAddr, QualType Ty) const override;
977
};
978
979
class PNaClTargetCodeGenInfo : public TargetCodeGenInfo {
980
 public:
981
   PNaClTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
982
3
       : TargetCodeGenInfo(std::make_unique<PNaClABIInfo>(CGT)) {}
983
};
984
985
2
void PNaClABIInfo::computeInfo(CGFunctionInfo &FI) const {
986
2
  if (!getCXXABI().classifyReturnType(FI))
987
2
    FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
988
989
2
  for (auto &I : FI.arguments())
990
0
    I.info = classifyArgumentType(I.type);
991
2
}
992
993
Address PNaClABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
994
0
                                QualType Ty) const {
995
  // The PNaCL ABI is a bit odd, in that varargs don't use normal
996
  // function classification. Structs get passed directly for varargs
997
  // functions, through a rewriting transform in
998
  // pnacl-llvm/lib/Transforms/NaCl/ExpandVarArgs.cpp, which allows
999
  // this target to actually support a va_arg instructions with an
1000
  // aggregate type, unlike other targets.
1001
0
  return EmitVAArgInstr(CGF, VAListAddr, Ty, ABIArgInfo::getDirect());
1002
0
}
1003
1004
/// Classify argument of given type \p Ty.
1005
0
ABIArgInfo PNaClABIInfo::classifyArgumentType(QualType Ty) const {
1006
0
  if (isAggregateTypeForABI(Ty)) {
1007
0
    if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
1008
0
      return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
1009
0
    return getNaturalAlignIndirect(Ty);
1010
0
  } else if (const EnumType *EnumTy = Ty->getAs<EnumType>()) {
1011
    // Treat an enum type as its underlying type.
1012
0
    Ty = EnumTy->getDecl()->getIntegerType();
1013
0
  } else if (Ty->isFloatingType()) {
1014
    // Floating-point types don't go inreg.
1015
0
    return ABIArgInfo::getDirect();
1016
0
  } else if (const auto *EIT = Ty->getAs<BitIntType>()) {
1017
    // Treat bit-precise integers as integers if <= 64, otherwise pass
1018
    // indirectly.
1019
0
    if (EIT->getNumBits() > 64)
1020
0
      return getNaturalAlignIndirect(Ty);
1021
0
    return ABIArgInfo::getDirect();
1022
0
  }
1023
1024
0
  return (isPromotableIntegerTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
1025
0
                                            : ABIArgInfo::getDirect());
1026
0
}
1027
1028
2
ABIArgInfo PNaClABIInfo::classifyReturnType(QualType RetTy) const {
1029
2
  if (RetTy->isVoidType())
1030
2
    return ABIArgInfo::getIgnore();
1031
1032
  // In the PNaCl ABI we always return records/structures on the stack.
1033
0
  if (isAggregateTypeForABI(RetTy))
1034
0
    return getNaturalAlignIndirect(RetTy);
1035
1036
  // Treat bit-precise integers as integers if <= 64, otherwise pass indirectly.
1037
0
  if (const auto *EIT = RetTy->getAs<BitIntType>()) {
1038
0
    if (EIT->getNumBits() > 64)
1039
0
      return getNaturalAlignIndirect(RetTy);
1040
0
    return ABIArgInfo::getDirect();
1041
0
  }
1042
1043
  // Treat an enum type as its underlying type.
1044
0
  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
1045
0
    RetTy = EnumTy->getDecl()->getIntegerType();
1046
1047
0
  return (isPromotableIntegerTypeForABI(RetTy) ? ABIArgInfo::getExtend(RetTy)
1048
0
                                               : ABIArgInfo::getDirect());
1049
0
}
1050
1051
/// IsX86_MMXType - Return true if this is an MMX type.
1052
699
bool IsX86_MMXType(llvm::Type *IRType) {
1053
  // Return true if the type is an MMX type <2 x i32>, <4 x i16>, or <8 x i8>.
1054
699
  return IRType->isVectorTy() && IRType->getPrimitiveSizeInBits() == 64 &&
1055
699
    
cast<llvm::VectorType>(IRType)->getElementType()->isIntegerTy()18
&&
1056
699
    
IRType->getScalarSizeInBits() != 6416
;
1057
699
}
1058
1059
static llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
1060
                                          StringRef Constraint,
1061
1.57k
                                          llvm::Type* Ty) {
1062
1.57k
  bool IsMMXCons = llvm::StringSwitch<bool>(Constraint)
1063
1.57k
                     .Cases("y", "&y", "^Ym", true)
1064
1.57k
                     .Default(false);
1065
1.57k
  if (IsMMXCons && 
Ty->isVectorTy()18
) {
1066
14
    if (cast<llvm::VectorType>(Ty)->getPrimitiveSizeInBits().getFixedSize() !=
1067
14
        64) {
1068
      // Invalid MMX constraint
1069
0
      return nullptr;
1070
0
    }
1071
1072
14
    return llvm::Type::getX86_MMXTy(CGF.getLLVMContext());
1073
14
  }
1074
1075
  // No operation needed
1076
1.56k
  return Ty;
1077
1.57k
}
1078
1079
/// Returns true if this type can be passed in SSE registers with the
1080
/// X86_VectorCall calling convention. Shared between x86_32 and x86_64.
1081
777
static bool isX86VectorTypeForVectorCall(ASTContext &Context, QualType Ty) {
1082
777
  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
1083
477
    if (BT->isFloatingPoint() && 
BT->getKind() != BuiltinType::Half282
) {
1084
282
      if (BT->getKind() == BuiltinType::LongDouble) {
1085
6
        if (&Context.getTargetInfo().getLongDoubleFormat() ==
1086
6
            &llvm::APFloat::x87DoubleExtended())
1087
2
          return false;
1088
6
      }
1089
280
      return true;
1090
282
    }
1091
477
  } else 
if (const VectorType *300
VT300
= Ty->getAs<VectorType>()) {
1092
    // vectorcall can pass XMM, YMM, and ZMM vectors. We don't pass SSE1 MMX
1093
    // registers specially.
1094
267
    unsigned VecSize = Context.getTypeSize(VT);
1095
267
    if (VecSize == 128 || 
VecSize == 2564
||
VecSize == 5124
)
1096
267
      return true;
1097
267
  }
1098
228
  return false;
1099
777
}
1100
1101
/// Returns true if this aggregate is small enough to be passed in SSE registers
1102
/// in the X86_VectorCall calling convention. Shared between x86_32 and x86_64.
1103
741
static bool isX86VectorCallAggregateSmallEnough(uint64_t NumMembers) {
1104
741
  return NumMembers <= 4;
1105
741
}
1106
1107
/// Returns a Homogeneous Vector Aggregate ABIArgInfo, used in X86.
1108
30
static ABIArgInfo getDirectX86Hva(llvm::Type* T = nullptr) {
1109
30
  auto AI = ABIArgInfo::getDirect(T);
1110
30
  AI.setInReg(true);
1111
30
  AI.setCanBeFlattened(false);
1112
30
  return AI;
1113
30
}
1114
1115
//===----------------------------------------------------------------------===//
1116
// X86-32 ABI Implementation
1117
//===----------------------------------------------------------------------===//
1118
1119
/// Similar to llvm::CCState, but for Clang.
1120
struct CCState {
1121
  CCState(CGFunctionInfo &FI)
1122
19.1k
      : IsPreassigned(FI.arg_size()), CC(FI.getCallingConvention()) {}
1123
1124
  llvm::SmallBitVector IsPreassigned;
1125
  unsigned CC = CallingConv::CC_C;
1126
  unsigned FreeRegs = 0;
1127
  unsigned FreeSSERegs = 0;
1128
};
1129
1130
/// X86_32ABIInfo - The X86-32 ABI information.
1131
class X86_32ABIInfo : public SwiftABIInfo {
1132
  enum Class {
1133
    Integer,
1134
    Float
1135
  };
1136
1137
  static const unsigned MinABIStackAlignInBytes = 4;
1138
1139
  bool IsDarwinVectorABI;
1140
  bool IsRetSmallStructInRegABI;
1141
  bool IsWin32StructABI;
1142
  bool IsSoftFloatABI;
1143
  bool IsMCUABI;
1144
  bool IsLinuxABI;
1145
  unsigned DefaultNumRegisterParameters;
1146
1147
521
  static bool isRegisterSize(unsigned Size) {
1148
521
    return (Size == 8 || 
Size == 16490
||
Size == 32471
||
Size == 64231
);
1149
521
  }
1150
1151
400
  bool isHomogeneousAggregateBaseType(QualType Ty) const override {
1152
    // FIXME: Assumes vectorcall is in use.
1153
400
    return isX86VectorTypeForVectorCall(getContext(), Ty);
1154
400
  }
1155
1156
  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
1157
322
                                         uint64_t NumMembers) const override {
1158
    // FIXME: Assumes vectorcall is in use.
1159
322
    return isX86VectorCallAggregateSmallEnough(NumMembers);
1160
322
  }
1161
1162
  bool shouldReturnTypeInRegister(QualType Ty, ASTContext &Context) const;
1163
1164
  /// getIndirectResult - Give a source type \arg Ty, return a suitable result
1165
  /// such that the argument will be passed in memory.
1166
  ABIArgInfo getIndirectResult(QualType Ty, bool ByVal, CCState &State) const;
1167
1168
  ABIArgInfo getIndirectReturnResult(QualType Ty, CCState &State) const;
1169
1170
  /// Return the alignment to use for the given type on the stack.
1171
  unsigned getTypeStackAlignInBytes(QualType Ty, unsigned Align) const;
1172
1173
  Class classify(QualType Ty) const;
1174
  ABIArgInfo classifyReturnType(QualType RetTy, CCState &State) const;
1175
  ABIArgInfo classifyArgumentType(QualType RetTy, CCState &State) const;
1176
1177
  /// Updates the number of available free registers, returns
1178
  /// true if any registers were allocated.
1179
  bool updateFreeRegs(QualType Ty, CCState &State) const;
1180
1181
  bool shouldAggregateUseDirect(QualType Ty, CCState &State, bool &InReg,
1182
                                bool &NeedsPadding) const;
1183
  bool shouldPrimitiveUseInReg(QualType Ty, CCState &State) const;
1184
1185
  bool canExpandIndirectArgument(QualType Ty) const;
1186
1187
  /// Rewrite the function info so that all memory arguments use
1188
  /// inalloca.
1189
  void rewriteWithInAlloca(CGFunctionInfo &FI) const;
1190
1191
  void addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
1192
                           CharUnits &StackOffset, ABIArgInfo &Info,
1193
                           QualType Type) const;
1194
  void runVectorCallFirstPass(CGFunctionInfo &FI, CCState &State) const;
1195
1196
public:
1197
1198
  void computeInfo(CGFunctionInfo &FI) const override;
1199
  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
1200
                    QualType Ty) const override;
1201
1202
  X86_32ABIInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
1203
                bool RetSmallStructInRegABI, bool Win32StructABI,
1204
                unsigned NumRegisterParameters, bool SoftFloatABI)
1205
    : SwiftABIInfo(CGT), IsDarwinVectorABI(DarwinVectorABI),
1206
      IsRetSmallStructInRegABI(RetSmallStructInRegABI),
1207
      IsWin32StructABI(Win32StructABI), IsSoftFloatABI(SoftFloatABI),
1208
      IsMCUABI(CGT.getTarget().getTriple().isOSIAMCU()),
1209
      IsLinuxABI(CGT.getTarget().getTriple().isOSLinux() ||
1210
                 CGT.getTarget().getTriple().isOSCygMing()),
1211
3.14k
      DefaultNumRegisterParameters(NumRegisterParameters) {}
1212
1213
  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
1214
0
                                    bool asReturnValue) const override {
1215
    // LLVM's x86-32 lowering currently only assigns up to three
1216
    // integer registers and three fp registers.  Oddly, it'll use up to
1217
    // four vector registers for vectors, but those can overlap with the
1218
    // scalar registers.
1219
0
    return occupiesMoreThan(CGT, scalars, /*total*/ 3);
1220
0
  }
1221
1222
0
  bool isSwiftErrorInRegister() const override {
1223
    // x86-32 lowering does not support passing swifterror in a register.
1224
0
    return false;
1225
0
  }
1226
};
1227
1228
class X86_32TargetCodeGenInfo : public TargetCodeGenInfo {
1229
public:
1230
  X86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
1231
                          bool RetSmallStructInRegABI, bool Win32StructABI,
1232
                          unsigned NumRegisterParameters, bool SoftFloatABI)
1233
      : TargetCodeGenInfo(std::make_unique<X86_32ABIInfo>(
1234
            CGT, DarwinVectorABI, RetSmallStructInRegABI, Win32StructABI,
1235
3.14k
            NumRegisterParameters, SoftFloatABI)) {}
1236
1237
  static bool isStructReturnInRegABI(
1238
      const llvm::Triple &Triple, const CodeGenOptions &Opts);
1239
1240
  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
1241
                           CodeGen::CodeGenModule &CGM) const override;
1242
1243
0
  int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
1244
    // Darwin uses different dwarf register numbers for EH.
1245
0
    if (CGM.getTarget().getTriple().isOSDarwin()) return 5;
1246
0
    return 4;
1247
0
  }
1248
1249
  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
1250
                               llvm::Value *Address) const override;
1251
1252
  llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
1253
                                  StringRef Constraint,
1254
672
                                  llvm::Type* Ty) const override {
1255
672
    return X86AdjustInlineAsmType(CGF, Constraint, Ty);
1256
672
  }
1257
1258
  void addReturnRegisterOutputs(CodeGenFunction &CGF, LValue ReturnValue,
1259
                                std::string &Constraints,
1260
                                std::vector<llvm::Type *> &ResultRegTypes,
1261
                                std::vector<llvm::Type *> &ResultTruncRegTypes,
1262
                                std::vector<LValue> &ResultRegDests,
1263
                                std::string &AsmString,
1264
                                unsigned NumOutputs) const override;
1265
1266
  llvm::Constant *
1267
37
  getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override {
1268
37
    unsigned Sig = (0xeb << 0) |  // jmp rel8
1269
37
                   (0x06 << 8) |  //           .+0x08
1270
37
                   ('v' << 16) |
1271
37
                   ('2' << 24);
1272
37
    return llvm::ConstantInt::get(CGM.Int32Ty, Sig);
1273
37
  }
1274
1275
7
  StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
1276
7
    return "movl\t%ebp, %ebp"
1277
7
           "\t\t// marker for objc_retainAutoreleaseReturnValue";
1278
7
  }
1279
};
1280
1281
}
1282
1283
/// Rewrite input constraint references after adding some output constraints.
1284
/// In the case where there is one output and one input and we add one output,
1285
/// we need to replace all operand references greater than or equal to 1:
1286
///     mov $0, $1
1287
///     mov eax, $1
1288
/// The result will be:
1289
///     mov $0, $2
1290
///     mov eax, $2
1291
static void rewriteInputConstraintReferences(unsigned FirstIn,
1292
                                             unsigned NumNewOuts,
1293
27
                                             std::string &AsmString) {
1294
27
  std::string Buf;
1295
27
  llvm::raw_string_ostream OS(Buf);
1296
27
  size_t Pos = 0;
1297
88
  while (Pos < AsmString.size()) {
1298
61
    size_t DollarStart = AsmString.find('$', Pos);
1299
61
    if (DollarStart == std::string::npos)
1300
19
      DollarStart = AsmString.size();
1301
61
    size_t DollarEnd = AsmString.find_first_not_of('$', DollarStart);
1302
61
    if (DollarEnd == std::string::npos)
1303
19
      DollarEnd = AsmString.size();
1304
61
    OS << StringRef(&AsmString[Pos], DollarEnd - Pos);
1305
61
    Pos = DollarEnd;
1306
61
    size_t NumDollars = DollarEnd - DollarStart;
1307
61
    if (NumDollars % 2 != 0 && 
Pos < AsmString.size()19
) {
1308
      // We have an operand reference.
1309
19
      size_t DigitStart = Pos;
1310
19
      if (AsmString[DigitStart] == '{') {
1311
3
        OS << '{';
1312
3
        ++DigitStart;
1313
3
      }
1314
19
      size_t DigitEnd = AsmString.find_first_not_of("0123456789", DigitStart);
1315
19
      if (DigitEnd == std::string::npos)
1316
6
        DigitEnd = AsmString.size();
1317
19
      StringRef OperandStr(&AsmString[DigitStart], DigitEnd - DigitStart);
1318
19
      unsigned OperandIndex;
1319
19
      if (!OperandStr.getAsInteger(10, OperandIndex)) {
1320
19
        if (OperandIndex >= FirstIn)
1321
14
          OperandIndex += NumNewOuts;
1322
19
        OS << OperandIndex;
1323
19
      } else {
1324
0
        OS << OperandStr;
1325
0
      }
1326
19
      Pos = DigitEnd;
1327
19
    }
1328
61
  }
1329
27
  AsmString = std::move(OS.str());
1330
27
}
1331
1332
/// Add output constraints for EAX:EDX because they are return registers.
1333
void X86_32TargetCodeGenInfo::addReturnRegisterOutputs(
1334
    CodeGenFunction &CGF, LValue ReturnSlot, std::string &Constraints,
1335
    std::vector<llvm::Type *> &ResultRegTypes,
1336
    std::vector<llvm::Type *> &ResultTruncRegTypes,
1337
    std::vector<LValue> &ResultRegDests, std::string &AsmString,
1338
27
    unsigned NumOutputs) const {
1339
27
  uint64_t RetWidth = CGF.getContext().getTypeSize(ReturnSlot.getType());
1340
1341
  // Use the EAX constraint if the width is 32 or smaller and EAX:EDX if it is
1342
  // larger.
1343
27
  if (!Constraints.empty())
1344
4
    Constraints += ',';
1345
27
  if (RetWidth <= 32) {
1346
22
    Constraints += "={eax}";
1347
22
    ResultRegTypes.push_back(CGF.Int32Ty);
1348
22
  } else {
1349
    // Use the 'A' constraint for EAX:EDX.
1350
5
    Constraints += "=A";
1351
5
    ResultRegTypes.push_back(CGF.Int64Ty);
1352
5
  }
1353
1354
  // Truncate EAX or EAX:EDX to an integer of the appropriate size.
1355
27
  llvm::Type *CoerceTy = llvm::IntegerType::get(CGF.getLLVMContext(), RetWidth);
1356
27
  ResultTruncRegTypes.push_back(CoerceTy);
1357
1358
  // Coerce the integer by bitcasting the return slot pointer.
1359
27
  ReturnSlot.setAddress(
1360
27
      CGF.Builder.CreateElementBitCast(ReturnSlot.getAddress(CGF), CoerceTy));
1361
27
  ResultRegDests.push_back(ReturnSlot);
1362
1363
27
  rewriteInputConstraintReferences(NumOutputs, 1, AsmString);
1364
27
}
1365
1366
/// shouldReturnTypeInRegister - Determine if the given type should be
1367
/// returned in a register (for the Darwin and MCU ABI).
1368
bool X86_32ABIInfo::shouldReturnTypeInRegister(QualType Ty,
1369
535
                                               ASTContext &Context) const {
1370
535
  uint64_t Size = Context.getTypeSize(Ty);
1371
1372
  // For i386, type must be register sized.
1373
  // For the MCU ABI, it only needs to be <= 8-byte
1374
535
  if ((IsMCUABI && 
Size > 6414
) ||
(533
!IsMCUABI533
&&
!isRegisterSize(Size)521
))
1375
69
   return false;
1376
1377
466
  if (Ty->isVectorType()) {
1378
    // 64- and 128- bit vectors inside structures are not returned in
1379
    // registers.
1380
4
    if (Size == 64 || 
Size == 1281
)
1381
3
      return false;
1382
1383
1
    return true;
1384
4
  }
1385
1386
  // If this is a builtin, pointer, enum, complex type, member pointer, or
1387
  // member function pointer it is ok.
1388
462
  if (Ty->getAs<BuiltinType>() || 
Ty->hasPointerRepresentation()376
||
1389
462
      
Ty->isAnyComplexType()371
||
Ty->isEnumeralType()348
||
1390
462
      
Ty->isBlockPointerType()346
||
Ty->isMemberPointerType()346
)
1391
378
    return true;
1392
1393
  // Arrays are treated like records.
1394
84
  if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty))
1395
6
    return shouldReturnTypeInRegister(AT->getElementType(), Context);
1396
1397
  // Otherwise, it must be a record type.
1398
78
  const RecordType *RT = Ty->getAs<RecordType>();
1399
78
  if (!RT) 
return false0
;
1400
1401
  // FIXME: Traverse bases here too.
1402
1403
  // Structure types are passed in register if all fields would be
1404
  // passed in a register.
1405
112
  
for (const auto *FD : RT->getDecl()->fields())78
{
1406
    // Empty fields are ignored.
1407
112
    if (isEmptyField(Context, FD, true))
1408
11
      continue;
1409
1410
    // Check fields recursively.
1411
101
    if (!shouldReturnTypeInRegister(FD->getType(), Context))
1412
4
      return false;
1413
101
  }
1414
74
  return true;
1415
78
}
1416
1417
209
static bool is32Or64BitBasicType(QualType Ty, ASTContext &Context) {
1418
  // Treat complex types as the element type.
1419
209
  if (const ComplexType *CTy = Ty->getAs<ComplexType>())
1420
2
    Ty = CTy->getElementType();
1421
1422
  // Check for a type which we know has a simple scalar argument-passing
1423
  // convention without any padding.  (We're specifically looking for 32
1424
  // and 64-bit integer and integer-equivalents, float, and double.)
1425
209
  if (!Ty->getAs<BuiltinType>() && 
!Ty->hasPointerRepresentation()38
&&
1426
209
      
!Ty->isEnumeralType()31
&&
!Ty->isBlockPointerType()28
)
1427
28
    return false;
1428
1429
181
  uint64_t Size = Context.getTypeSize(Ty);
1430
181
  return Size == 32 || 
Size == 6429
;
1431
209
}
1432
1433
static bool addFieldSizes(ASTContext &Context, const RecordDecl *RD,
1434
249
                          uint64_t &Size) {
1435
249
  for (const auto *FD : RD->fields()) {
1436
    // Scalar arguments on the stack get 4 byte alignment on x86. If the
1437
    // argument is smaller than 32-bits, expanding the struct will create
1438
    // alignment padding.
1439
209
    if (!is32Or64BitBasicType(FD->getType(), Context))
1440
50
      return false;
1441
1442
    // FIXME: Reject bit-fields wholesale; there are two problems, we don't know
1443
    // how to expand them yet, and the predicate for telling if a bitfield still
1444
    // counts as "basic" is more complicated than what we were doing previously.
1445
159
    if (FD->isBitField())
1446
2
      return false;
1447
1448
157
    Size += Context.getTypeSize(FD->getType());
1449
157
  }
1450
197
  return true;
1451
249
}
1452
1453
static bool addBaseAndFieldSizes(ASTContext &Context, const CXXRecordDecl *RD,
1454
147
                                 uint64_t &Size) {
1455
  // Don't do this if there are any non-empty bases.
1456
147
  for (const CXXBaseSpecifier &Base : RD->bases()) {
1457
1
    if (!addBaseAndFieldSizes(Context, Base.getType()->getAsCXXRecordDecl(),
1458
1
                              Size))
1459
0
      return false;
1460
1
  }
1461
147
  if (!addFieldSizes(Context, RD, Size))
1462
10
    return false;
1463
137
  return true;
1464
147
}
1465
1466
/// Test whether an argument type which is to be passed indirectly (on the
1467
/// stack) would have the equivalent layout if it was expanded into separate
1468
/// arguments. If so, we prefer to do the latter to avoid inhibiting
1469
/// optimizations.
1470
337
bool X86_32ABIInfo::canExpandIndirectArgument(QualType Ty) const {
1471
  // We can only expand structure types.
1472
337
  const RecordType *RT = Ty->getAs<RecordType>();
1473
337
  if (!RT)
1474
76
    return false;
1475
261
  const RecordDecl *RD = RT->getDecl();
1476
261
  uint64_t Size = 0;
1477
261
  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
1478
159
    if (!IsWin32StructABI) {
1479
      // On non-Windows, we have to conservatively match our old bitcode
1480
      // prototypes in order to be ABI-compatible at the bitcode level.
1481
35
      if (!CXXRD->isCLike())
1482
13
        return false;
1483
124
    } else {
1484
      // Don't do this for dynamic classes.
1485
124
      if (CXXRD->isDynamicClass())
1486
0
        return false;
1487
124
    }
1488
146
    if (!addBaseAndFieldSizes(getContext(), CXXRD, Size))
1489
10
      return false;
1490
146
  } else {
1491
102
    if (!addFieldSizes(getContext(), RD, Size))
1492
42
      return false;
1493
102
  }
1494
1495
  // We can do this if there was no alignment padding.
1496
196
  return Size == getContext().getTypeSize(Ty);
1497
261
}
1498
1499
353
ABIArgInfo X86_32ABIInfo::getIndirectReturnResult(QualType RetTy, CCState &State) const {
1500
  // If the return value is indirect, then the hidden argument is consuming one
1501
  // integer register.
1502
353
  if (State.FreeRegs) {
1503
5
    --State.FreeRegs;
1504
5
    if (!IsMCUABI)
1505
3
      return getNaturalAlignIndirectInReg(RetTy);
1506
5
  }
1507
350
  return getNaturalAlignIndirect(RetTy, /*ByVal=*/false);
1508
353
}
1509
1510
ABIArgInfo X86_32ABIInfo::classifyReturnType(QualType RetTy,
1511
19.0k
                                             CCState &State) const {
1512
19.0k
  if (RetTy->isVoidType())
1513
12.5k
    return ABIArgInfo::getIgnore();
1514
1515
6.48k
  const Type *Base = nullptr;
1516
6.48k
  uint64_t NumElts = 0;
1517
6.48k
  if ((State.CC == llvm::CallingConv::X86_VectorCall ||
1518
6.48k
       
State.CC == llvm::CallingConv::X86_RegCall6.46k
) &&
1519
6.48k
      
isHomogeneousAggregate(RetTy, Base, NumElts)26
) {
1520
    // The LLVM struct type for such an aggregate should lower properly.
1521
17
    return ABIArgInfo::getDirect();
1522
17
  }
1523
1524
6.46k
  if (const VectorType *VT = RetTy->getAs<VectorType>()) {
1525
    // On Darwin, some vectors are returned in registers.
1526
477
    if (IsDarwinVectorABI) {
1527
463
      uint64_t Size = getContext().getTypeSize(RetTy);
1528
1529
      // 128-bit vectors are a special case; they are returned in
1530
      // registers and we need to make sure to pick a type the LLVM
1531
      // backend will like.
1532
463
      if (Size == 128)
1533
237
        return ABIArgInfo::getDirect(llvm::FixedVectorType::get(
1534
237
            llvm::Type::getInt64Ty(getVMContext()), 2));
1535
1536
      // Always return in register if it fits in a general purpose
1537
      // register, or if it is 64 bits and has a single element.
1538
226
      if ((Size == 8 || Size == 16 || Size == 32) ||
1539
226
          
(223
Size == 64223
&&
VT->getNumElements() == 19
))
1540
9
        return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
1541
9
                                                            Size));
1542
1543
217
      return getIndirectReturnResult(RetTy, State);
1544
226
    }
1545
1546
14
    return ABIArgInfo::getDirect();
1547
477
  }
1548
1549
5.98k
  if (isAggregateTypeForABI(RetTy)) {
1550
521
    if (const RecordType *RT = RetTy->getAs<RecordType>()) {
1551
      // Structures with flexible arrays are always indirect.
1552
190
      if (RT->getDecl()->hasFlexibleArrayMember())
1553
1
        return getIndirectReturnResult(RetTy, State);
1554
190
    }
1555
1556
    // If specified, structs and unions are always indirect.
1557
520
    if (!IsRetSmallStructInRegABI && 
!RetTy->isAnyComplexType()112
)
1558
59
      return getIndirectReturnResult(RetTy, State);
1559
1560
    // Ignore empty structs/unions.
1561
461
    if (isEmptyRecord(getContext(), RetTy, true))
1562
32
      return ABIArgInfo::getIgnore();
1563
1564
    // Return complex of _Float16 as <2 x half> so the backend will use xmm0.
1565
429
    if (const ComplexType *CT = RetTy->getAs<ComplexType>()) {
1566
64
      QualType ET = getContext().getCanonicalType(CT->getElementType());
1567
64
      if (ET->isFloat16Type())
1568
1
        return ABIArgInfo::getDirect(llvm::FixedVectorType::get(
1569
1
            llvm::Type::getHalfTy(getVMContext()), 2));
1570
64
    }
1571
1572
    // Small structures which are register sized are generally returned
1573
    // in a register.
1574
428
    if (shouldReturnTypeInRegister(RetTy, getContext())) {
1575
356
      uint64_t Size = getContext().getTypeSize(RetTy);
1576
1577
      // As a special-case, if the struct is a "single-element" struct, and
1578
      // the field is of type "float" or "double", return it in a
1579
      // floating-point register. (MSVC does not apply this special case.)
1580
      // We apply a similar transformation for pointer types to improve the
1581
      // quality of the generated IR.
1582
356
      if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
1583
47
        if ((!IsWin32StructABI && 
SeltTy->isRealFloatingType()34
)
1584
47
            || 
SeltTy->hasPointerRepresentation()31
)
1585
19
          return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
1586
1587
      // FIXME: We should be able to narrow this integer in cases with dead
1588
      // padding.
1589
337
      return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),Size));
1590
356
    }
1591
1592
72
    return getIndirectReturnResult(RetTy, State);
1593
428
  }
1594
1595
  // Treat an enum type as its underlying type.
1596
5.46k
  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
1597
35
    RetTy = EnumTy->getDecl()->getIntegerType();
1598
1599
5.46k
  if (const auto *EIT = RetTy->getAs<BitIntType>())
1600
22
    if (EIT->getNumBits() > 64)
1601
4
      return getIndirectReturnResult(RetTy, State);
1602
1603
5.46k
  return (isPromotableIntegerTypeForABI(RetTy) ? 
ABIArgInfo::getExtend(RetTy)126
1604
5.46k
                                               : 
ABIArgInfo::getDirect()5.33k
);
1605
5.46k
}
1606
1607
39
static bool isSIMDVectorType(ASTContext &Context, QualType Ty) {
1608
39
  return Ty->getAs<VectorType>() && 
Context.getTypeSize(Ty) == 12812
;
1609
39
}
1610
1611
34
static bool isRecordWithSIMDVectorType(ASTContext &Context, QualType Ty) {
1612
34
  const RecordType *RT = Ty->getAs<RecordType>();
1613
34
  if (!RT)
1614
15
    return false;
1615
19
  const RecordDecl *RD = RT->getDecl();
1616
1617
  // If this is a C++ record, check the bases first.
1618
19
  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
1619
0
    for (const auto &I : CXXRD->bases())
1620
0
      if (!isRecordWithSIMDVectorType(Context, I.getType()))
1621
0
        return false;
1622
1623
22
  
for (const auto *i : RD->fields())19
{
1624
22
    QualType FT = i->getType();
1625
1626
22
    if (isSIMDVectorType(Context, FT))
1627
7
      return true;
1628
1629
15
    if (isRecordWithSIMDVectorType(Context, FT))
1630
0
      return true;
1631
15
  }
1632
1633
12
  return false;
1634
19
}
1635
1636
unsigned X86_32ABIInfo::getTypeStackAlignInBytes(QualType Ty,
1637
342
                                                 unsigned Align) const {
1638
  // Otherwise, if the alignment is less than or equal to the minimum ABI
1639
  // alignment, just use the default; the backend will handle this.
1640
342
  if (Align <= MinABIStackAlignInBytes)
1641
270
    return 0; // Use default alignment.
1642
1643
72
  if (IsLinuxABI) {
1644
    // Exclude other System V OS (e.g Darwin, PS4 and FreeBSD) since we don't
1645
    // want to spend any effort dealing with the ramifications of ABI breaks.
1646
    //
1647
    // If the vector type is __m128/__m256/__m512, return the default alignment.
1648
30
    if (Ty->isVectorType() && 
(18
Align == 1618
||
Align == 3212
||
Align == 646
))
1649
18
      return Align;
1650
30
  }
1651
  // On non-Darwin, the stack type alignment is always 4.
1652
54
  if (!IsDarwinVectorABI) {
1653
    // Set explicit alignment, since we may need to realign the top.
1654
27
    return MinABIStackAlignInBytes;
1655
27
  }
1656
1657
  // Otherwise, if the type contains an SSE vector type, the alignment is 16.
1658
27
  if (Align >= 16 && 
(17
isSIMDVectorType(getContext(), Ty)17
||
1659
17
                      
isRecordWithSIMDVectorType(getContext(), Ty)16
))
1660
8
    return 16;
1661
1662
19
  return MinABIStackAlignInBytes;
1663
27
}
1664
1665
ABIArgInfo X86_32ABIInfo::getIndirectResult(QualType Ty, bool ByVal,
1666
463
                                            CCState &State) const {
1667
463
  if (!ByVal) {
1668
163
    if (State.FreeRegs) {
1669
22
      --State.FreeRegs; // Non-byval indirects just use one pointer.
1670
22
      if (!IsMCUABI)
1671
22
        return getNaturalAlignIndirectInReg(Ty);
1672
22
    }
1673
141
    return getNaturalAlignIndirect(Ty, false);
1674
163
  }
1675
1676
  // Compute the byval alignment.
1677
300
  unsigned TypeAlign = getContext().getTypeAlign(Ty) / 8;
1678
300
  unsigned StackAlign = getTypeStackAlignInBytes(Ty, TypeAlign);
1679
300
  if (StackAlign == 0)
1680
250
    return ABIArgInfo::getIndirect(CharUnits::fromQuantity(4), /*ByVal=*/true);
1681
1682
  // If the stack alignment is less than the type alignment, realign the
1683
  // argument.
1684
50
  bool Realign = TypeAlign > StackAlign;
1685
50
  return ABIArgInfo::getIndirect(CharUnits::fromQuantity(StackAlign),
1686
50
                                 /*ByVal=*/true, Realign);
1687
300
}
1688
1689
32.4k
X86_32ABIInfo::Class X86_32ABIInfo::classify(QualType Ty) const {
1690
32.4k
  const Type *T = isSingleElementStruct(Ty, getContext());
1691
32.4k
  if (!T)
1692
32.3k
    T = Ty.getTypePtr();
1693
1694
32.4k
  if (const BuiltinType *BT = T->getAs<BuiltinType>()) {
1695
11.2k
    BuiltinType::Kind K = BT->getKind();
1696
11.2k
    if (K == BuiltinType::Float || 
K == BuiltinType::Double10.8k
)
1697
595
      return Float;
1698
11.2k
  }
1699
31.8k
  return Integer;
1700
32.4k
}
1701
1702
32.4k
bool X86_32ABIInfo::updateFreeRegs(QualType Ty, CCState &State) const {
1703
32.4k
  if (!IsSoftFloatABI) {
1704
32.4k
    Class C = classify(Ty);
1705
32.4k
    if (C == Float)
1706
595
      return false;
1707
32.4k
  }
1708
1709
31.8k
  unsigned Size = getContext().getTypeSize(Ty);
1710
31.8k
  unsigned SizeInRegs = (Size + 31) / 32;
1711
1712
31.8k
  if (SizeInRegs == 0)
1713
2
    return false;
1714
1715
31.8k
  if (!IsMCUABI) {
1716
31.8k
    if (SizeInRegs > State.FreeRegs) {
1717
31.6k
      State.FreeRegs = 0;
1718
31.6k
      return false;
1719
31.6k
    }
1720
31.8k
  } else {
1721
    // The MCU psABI allows passing parameters in-reg even if there are
1722
    // earlier parameters that are passed on the stack. Also,
1723
    // it does not allow passing >8-byte structs in-register,
1724
    // even if there are 3 free registers available.
1725
42
    if (SizeInRegs > State.FreeRegs || 
SizeInRegs > 234
)
1726
9
      return false;
1727
42
  }
1728
1729
240
  State.FreeRegs -= SizeInRegs;
1730
240
  return true;
1731
31.8k
}
1732
1733
bool X86_32ABIInfo::shouldAggregateUseDirect(QualType Ty, CCState &State,
1734
                                             bool &InReg,
1735
404
                                             bool &NeedsPadding) const {
1736
  // On Windows, aggregates other than HFAs are never passed in registers, and
1737
  // they do not consume register slots. Homogenous floating-point aggregates
1738
  // (HFAs) have already been dealt with at this point.
1739
404
  if (IsWin32StructABI && 
isAggregateTypeForABI(Ty)175
)
1740
175
    return false;
1741
1742
229
  NeedsPadding = false;
1743
229
  InReg = !IsMCUABI;
1744
1745
229
  if (!updateFreeRegs(Ty, State))
1746
209
    return false;
1747
1748
20
  if (IsMCUABI)
1749
7
    return true;
1750
1751
13
  if (State.CC == llvm::CallingConv::X86_FastCall ||
1752
13
      
State.CC == llvm::CallingConv::X86_VectorCall10
||
1753
13
      
State.CC == llvm::CallingConv::X86_RegCall10
) {
1754
4
    if (getContext().getTypeSize(Ty) <= 32 && State.FreeRegs)
1755
3
      NeedsPadding = true;
1756
1757
4
    return false;
1758
4
  }
1759
1760
9
  return true;
1761
13
}
1762
1763
32.2k
bool X86_32ABIInfo::shouldPrimitiveUseInReg(QualType Ty, CCState &State) const {
1764
32.2k
  if (!updateFreeRegs(Ty, State))
1765
31.9k
    return false;
1766
1767
220
  if (IsMCUABI)
1768
26
    return false;
1769
1770
194
  if (State.CC == llvm::CallingConv::X86_FastCall ||
1771
194
      
State.CC == llvm::CallingConv::X86_VectorCall137
||
1772
194
      
State.CC == llvm::CallingConv::X86_RegCall94
) {
1773
143
    if (getContext().getTypeSize(Ty) > 32)
1774
13
      return false;
1775
1776
130
    return (Ty->isIntegralOrEnumerationType() || 
Ty->isPointerType()27
||
1777
130
        
Ty->isReferenceType()7
);
1778
143
  }
1779
1780
51
  return true;
1781
194
}
1782
1783
57
void X86_32ABIInfo::runVectorCallFirstPass(CGFunctionInfo &FI, CCState &State) const {
1784
  // Vectorcall x86 works subtly different than in x64, so the format is
1785
  // a bit different than the x64 version.  First, all vector types (not HVAs)
1786
  // are assigned, with the first 6 ending up in the [XYZ]MM0-5 registers.
1787
  // This differs from the x64 implementation, where the first 6 by INDEX get
1788
  // registers.
1789
  // In the second pass over the arguments, HVAs are passed in the remaining
1790
  // vector registers if possible, or indirectly by address. The address will be
1791
  // passed in ECX/EDX if available. Any other arguments are passed according to
1792
  // the usual fastcall rules.
1793
57
  MutableArrayRef<CGFunctionInfoArgInfo> Args = FI.arguments();
1794
171
  for (int I = 0, E = Args.size(); I < E; 
++I114
) {
1795
114
    const Type *Base = nullptr;
1796
114
    uint64_t NumElts = 0;
1797
114
    const QualType &Ty = Args[I].type;
1798
114
    if ((Ty->isVectorType() || 
Ty->isBuiltinType()93
) &&
1799
114
        
isHomogeneousAggregate(Ty, Base, NumElts)84
) {
1800
42
      if (State.FreeSSERegs >= NumElts) {
1801
38
        State.FreeSSERegs -= NumElts;
1802
38
        Args[I].info = ABIArgInfo::getDirectInReg();
1803
38
        State.IsPreassigned.set(I);
1804
38
      }
1805
42
    }
1806
114
  }
1807
57
}
1808
1809
ABIArgInfo X86_32ABIInfo::classifyArgumentType(QualType Ty,
1810
33.6k
                                               CCState &State) const {
1811
  // FIXME: Set alignment on indirect arguments.
1812
33.6k
  bool IsFastCall = State.CC == llvm::CallingConv::X86_FastCall;
1813
33.6k
  bool IsRegCall = State.CC == llvm::CallingConv::X86_RegCall;
1814
33.6k
  bool IsVectorCall = State.CC == llvm::CallingConv::X86_VectorCall;
1815
1816
33.6k
  Ty = useFirstFieldIfTransparentUnion(Ty);
1817
33.6k
  TypeInfo TI = getContext().getTypeInfo(Ty);
1818
1819
  // Check with the C++ ABI first.
1820
33.6k
  const RecordType *RT = Ty->getAs<RecordType>();
1821
33.6k
  if (RT) {
1822
579
    CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI());
1823
579
    if (RAA == CGCXXABI::RAA_Indirect) {
1824
103
      return getIndirectResult(Ty, false, State);
1825
476
    } else if (RAA == CGCXXABI::RAA_DirectInMemory) {
1826
      // The field index doesn't matter, we'll fix it up later.
1827
86
      return ABIArgInfo::getInAlloca(/*FieldIndex=*/0);
1828
86
    }
1829
579
  }
1830
1831
  // Regcall uses the concept of a homogenous vector aggregate, similar
1832
  // to other targets.
1833
33.4k
  const Type *Base = nullptr;
1834
33.4k
  uint64_t NumElts = 0;
1835
33.4k
  if ((IsRegCall || 
IsVectorCall33.3k
) &&
1836
33.4k
      
isHomogeneousAggregate(Ty, Base, NumElts)179
) {
1837
79
    if (State.FreeSSERegs >= NumElts) {
1838
57
      State.FreeSSERegs -= NumElts;
1839
1840
      // Vectorcall passes HVAs directly and does not flatten them, but regcall
1841
      // does.
1842
57
      if (IsVectorCall)
1843
12
        return getDirectX86Hva();
1844
1845
45
      if (Ty->isBuiltinType() || 
Ty->isVectorType()35
)
1846
20
        return ABIArgInfo::getDirect();
1847
25
      return ABIArgInfo::getExpand();
1848
45
    }
1849
22
    return getIndirectResult(Ty, /*ByVal=*/false, State);
1850
79
  }
1851
1852
33.4k
  if (isAggregateTypeForABI(Ty)) {
1853
    // Structures with flexible arrays are always indirect.
1854
    // FIXME: This should not be byval!
1855
429
    if (RT && 
RT->getDecl()->hasFlexibleArrayMember()342
)
1856
1
      return getIndirectResult(Ty, true, State);
1857
1858
    // Ignore empty structs/unions on non-Windows.
1859
428
    if (!IsWin32StructABI && 
isEmptyRecord(getContext(), Ty, true)253
)
1860
24
      return ABIArgInfo::getIgnore();
1861
1862
404
    llvm::LLVMContext &LLVMContext = getVMContext();
1863
404
    llvm::IntegerType *Int32 = llvm::Type::getInt32Ty(LLVMContext);
1864
404
    bool NeedsPadding = false;
1865
404
    bool InReg;
1866
404
    if (shouldAggregateUseDirect(Ty, State, InReg, NeedsPadding)) {
1867
16
      unsigned SizeInRegs = (TI.Width + 31) / 32;
1868
16
      SmallVector<llvm::Type*, 3> Elements(SizeInRegs, Int32);
1869
16
      llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements);
1870
16
      if (InReg)
1871
9
        return ABIArgInfo::getDirectInReg(Result);
1872
7
      else
1873
7
        return ABIArgInfo::getDirect(Result);
1874
16
    }
1875
388
    llvm::IntegerType *PaddingType = NeedsPadding ? 
Int323
:
nullptr385
;
1876
1877
    // Pass over-aligned aggregates on Windows indirectly. This behavior was
1878
    // added in MSVC 2015.
1879
388
    if (IsWin32StructABI && 
TI.isAlignRequired()175
&&
TI.Align > 321
)
1880
1
      return getIndirectResult(Ty, /*ByVal=*/false, State);
1881
1882
    // Expand small (<= 128-bit) record types when we know that the stack layout
1883
    // of those arguments will match the struct. This is important because the
1884
    // LLVM backend isn't smart enough to remove byval, which inhibits many
1885
    // optimizations.
1886
    // Don't do this for the MCU if there are still free integer registers
1887
    // (see X86_64 ABI for full explanation).
1888
387
    if (TI.Width <= 4 * 32 && 
(340
!IsMCUABI340
||
State.FreeRegs == 05
) &&
1889
387
        
canExpandIndirectArgument(Ty)337
)
1890
88
      return ABIArgInfo::getExpandWithPadding(
1891
88
          IsFastCall || 
IsVectorCall84
||
IsRegCall83
, PaddingType);
1892
1893
299
    return getIndirectResult(Ty, true, State);
1894
387
  }
1895
1896
32.9k
  if (const VectorType *VT = Ty->getAs<VectorType>()) {
1897
    // On Windows, vectors are passed directly if registers are available, or
1898
    // indirectly if not. This avoids the need to align argument memory. Pass
1899
    // user-defined vector types larger than 512 bits indirectly for simplicity.
1900
757
    if (IsWin32StructABI) {
1901
45
      if (TI.Width <= 512 && 
State.FreeSSERegs > 040
) {
1902
28
        --State.FreeSSERegs;
1903
28
        return ABIArgInfo::getDirectInReg();
1904
28
      }
1905
17
      return getIndirectResult(Ty, /*ByVal=*/false, State);
1906
45
    }
1907
1908
    // On Darwin, some vectors are passed in memory, we handle this by passing
1909
    // it as an i8/i16/i32/i64.
1910
712
    if (IsDarwinVectorABI) {
1911
651
      if ((TI.Width == 8 || TI.Width == 16 || TI.Width == 32) ||
1912
651
          
(649
TI.Width == 64649
&&
VT->getNumElements() == 116
))
1913
13
        return ABIArgInfo::getDirect(
1914
13
            llvm::IntegerType::get(getVMContext(), TI.Width));
1915
651
    }
1916
1917
699
    if (IsX86_MMXType(CGT.ConvertType(Ty)))
1918
8
      return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 64));
1919
1920
691
    return ABIArgInfo::getDirect();
1921
699
  }
1922
1923
1924
32.2k
  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
1925
25
    Ty = EnumTy->getDecl()->getIntegerType();
1926
1927
32.2k
  bool InReg = shouldPrimitiveUseInReg(Ty, State);
1928
1929
32.2k
  if (isPromotableIntegerTypeForABI(Ty)) {
1930
444
    if (InReg)
1931
25
      return ABIArgInfo::getExtendInReg(Ty);
1932
419
    return ABIArgInfo::getExtend(Ty);
1933
444
  }
1934
1935
31.7k
  if (const auto *EIT = Ty->getAs<BitIntType>()) {
1936
42
    if (EIT->getNumBits() <= 64) {
1937
22
      if (InReg)
1938
0
        return ABIArgInfo::getDirectInReg();
1939
22
      return ABIArgInfo::getDirect();
1940
22
    }
1941
20
    return getIndirectResult(Ty, /*ByVal=*/false, State);
1942
42
  }
1943
1944
31.7k
  if (InReg)
1945
156
    return ABIArgInfo::getDirectInReg();
1946
31.5k
  return ABIArgInfo::getDirect();
1947
31.7k
}
1948
1949
19.1k
void X86_32ABIInfo::computeInfo(CGFunctionInfo &FI) const {
1950
19.1k
  CCState State(FI);
1951
19.1k
  if (IsMCUABI)
1952
28
    State.FreeRegs = 3;
1953
19.0k
  else if (State.CC == llvm::CallingConv::X86_FastCall) {
1954
74
    State.FreeRegs = 2;
1955
74
    State.FreeSSERegs = 3;
1956
19.0k
  } else if (State.CC == llvm::CallingConv::X86_VectorCall) {
1957
57
    State.FreeRegs = 2;
1958
57
    State.FreeSSERegs = 6;
1959
18.9k
  } else if (FI.getHasRegParm())
1960
31
    State.FreeRegs = FI.getRegParm();
1961
18.9k
  else if (State.CC == llvm::CallingConv::X86_RegCall) {
1962
54
    State.FreeRegs = 5;
1963
54
    State.FreeSSERegs = 8;
1964
18.8k
  } else if (IsWin32StructABI) {
1965
    // Since MSVC 2015, the first three SSE vectors have been passed in
1966
    // registers. The rest are passed indirectly.
1967
4.02k
    State.FreeRegs = DefaultNumRegisterParameters;
1968
4.02k
    State.FreeSSERegs = 3;
1969
4.02k
  } else
1970
14.8k
    State.FreeRegs = DefaultNumRegisterParameters;
1971
1972
19.1k
  if (!::classifyReturnType(getCXXABI(), FI, *this)) {
1973
19.0k
    FI.getReturnInfo() = classifyReturnType(FI.getReturnType(), State);
1974
19.0k
  } else 
if (88
FI.getReturnInfo().isIndirect()88
) {
1975
    // The C++ ABI is not aware of register usage, so we have to check if the
1976
    // return value was sret and put it in a register ourselves if appropriate.
1977
88
    if (State.FreeRegs) {
1978
4
      --State.FreeRegs;  // The sret parameter consumes a register.
1979
4
      if (!IsMCUABI)
1980
4
        FI.getReturnInfo().setInReg(true);
1981
4
    }
1982
88
  }
1983
1984
  // The chain argument effectively gives us another free register.
1985
19.1k
  if (FI.isChainCall())
1986
4
    ++State.FreeRegs;
1987
1988
  // For vectorcall, do a first pass over the arguments, assigning FP and vector
1989
  // arguments to XMM registers as available.
1990
19.1k
  if (State.CC == llvm::CallingConv::X86_VectorCall)
1991
57
    runVectorCallFirstPass(FI, State);
1992
1993
19.1k
  bool UsedInAlloca = false;
1994
19.1k
  MutableArrayRef<CGFunctionInfoArgInfo> Args = FI.arguments();
1995
52.8k
  for (int I = 0, E = Args.size(); I < E; 
++I33.7k
) {
1996
    // Skip arguments that have already been assigned.
1997
33.7k
    if (State.IsPreassigned.test(I))
1998
38
      continue;
1999
2000
33.6k
    Args[I].info = classifyArgumentType(Args[I].type, State);
2001
33.6k
    UsedInAlloca |= (Args[I].info.getKind() == ABIArgInfo::InAlloca);
2002
33.6k
  }
2003
2004
  // If we needed to use inalloca for any argument, do a second pass and rewrite
2005
  // all the memory arguments to use inalloca.
2006
19.1k
  if (UsedInAlloca)
2007
73
    rewriteWithInAlloca(FI);
2008
19.1k
}
2009
2010
void
2011
X86_32ABIInfo::addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
2012
                                   CharUnits &StackOffset, ABIArgInfo &Info,
2013
167
                                   QualType Type) const {
2014
  // Arguments are always 4-byte-aligned.
2015
167
  CharUnits WordSize = CharUnits::fromQuantity(4);
2016
167
  assert(StackOffset.isMultipleOf(WordSize) && "unaligned inalloca struct");
2017
2018
  // sret pointers and indirect things will require an extra pointer
2019
  // indirection, unless they are byval. Most things are byval, and will not
2020
  // require this indirection.
2021
0
  bool IsIndirect = false;
2022
167
  if (Info.isIndirect() && 
!Info.getIndirectByVal()17
)
2023
14
    IsIndirect = true;
2024
167
  Info = ABIArgInfo::getInAlloca(FrameFields.size(), IsIndirect);
2025
167
  llvm::Type *LLTy = CGT.ConvertTypeForMem(Type);
2026
167
  if (IsIndirect)
2027
14
    LLTy = LLTy->getPointerTo(0);
2028
167
  FrameFields.push_back(LLTy);
2029
167
  StackOffset += IsIndirect ? 
WordSize14
:
getContext().getTypeSizeInChars(Type)153
;
2030
2031
  // Insert padding bytes to respect alignment.
2032
167
  CharUnits FieldEnd = StackOffset;
2033
167
  StackOffset = FieldEnd.alignTo(WordSize);
2034
167
  if (StackOffset != FieldEnd) {
2035
40
    CharUnits NumBytes = StackOffset - FieldEnd;
2036
40
    llvm::Type *Ty = llvm::Type::getInt8Ty(getVMContext());
2037
40
    Ty = llvm::ArrayType::get(Ty, NumBytes.getQuantity());
2038
40
    FrameFields.push_back(Ty);
2039
40
  }
2040
167
}
2041
2042
177
static bool isArgInAlloca(const ABIArgInfo &Info) {
2043
  // Leave ignored and inreg arguments alone.
2044
177
  switch (Info.getKind()) {
2045
86
  case ABIArgInfo::InAlloca:
2046
86
    return true;
2047
0
  case ABIArgInfo::Ignore:
2048
0
  case ABIArgInfo::IndirectAliased:
2049
0
    return false;
2050
11
  case ABIArgInfo::Indirect:
2051
84
  case ABIArgInfo::Direct:
2052
90
  case ABIArgInfo::Extend:
2053
90
    return !Info.getInReg();
2054
1
  case ABIArgInfo::Expand:
2055
1
  case ABIArgInfo::CoerceAndExpand:
2056
    // These are aggregate types which are never passed in registers when
2057
    // inalloca is involved.
2058
1
    return true;
2059
177
  }
2060
0
  llvm_unreachable("invalid enum");
2061
0
}
2062
2063
73
void X86_32ABIInfo::rewriteWithInAlloca(CGFunctionInfo &FI) const {
2064
73
  assert(IsWin32StructABI && "inalloca only supported on win32");
2065
2066
  // Build a packed struct type for all of the arguments in memory.
2067
0
  SmallVector<llvm::Type *, 6> FrameFields;
2068
2069
  // The stack alignment is always 4.
2070
73
  CharUnits StackAlign = CharUnits::fromQuantity(4);
2071
2072
73
  CharUnits StackOffset;
2073
73
  CGFunctionInfo::arg_iterator I = FI.arg_begin(), E = FI.arg_end();
2074
2075
  // Put 'this' into the struct before 'sret', if necessary.
2076
73
  bool IsThisCall =
2077
73
      FI.getCallingConvention() == llvm::CallingConv::X86_ThisCall;
2078
73
  ABIArgInfo &Ret = FI.getReturnInfo();
2079
73
  if (Ret.isIndirect() && 
Ret.isSRetAfterThis()9
&&
!IsThisCall7
&&
2080
73
      
isArgInAlloca(I->info)6
) {
2081
5
    addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
2082
5
    ++I;
2083
5
  }
2084
2085
  // Put the sret parameter into the inalloca struct if it's in memory.
2086
73
  if (Ret.isIndirect() && 
!Ret.getInReg()9
) {
2087
8
    addFieldToArgStruct(FrameFields, StackOffset, Ret, FI.getReturnType());
2088
    // On Windows, the hidden sret parameter is always returned in eax.
2089
8
    Ret.setInAllocaSRet(IsWin32StructABI);
2090
8
  }
2091
2092
  // Skip the 'this' parameter in ecx.
2093
73
  if (IsThisCall)
2094
17
    ++I;
2095
2096
  // Put arguments passed in memory into the struct.
2097
244
  for (; I != E; 
++I171
) {
2098
171
    if (isArgInAlloca(I->info))
2099
154
      addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
2100
171
  }
2101
2102
73
  FI.setArgStruct(llvm::StructType::get(getVMContext(), FrameFields,
2103
73
                                        /*isPacked=*/true),
2104
73
                  StackAlign);
2105
73
}
2106
2107
Address X86_32ABIInfo::EmitVAArg(CodeGenFunction &CGF,
2108
42
                                 Address VAListAddr, QualType Ty) const {
2109
2110
42
  auto TypeInfo = getContext().getTypeInfoInChars(Ty);
2111
2112
  // x86-32 changes the alignment of certain arguments on the stack.
2113
  //
2114
  // Just messing with TypeInfo like this works because we never pass
2115
  // anything indirectly.
2116
42
  TypeInfo.Align = CharUnits::fromQuantity(
2117
42
                getTypeStackAlignInBytes(Ty, TypeInfo.Align.getQuantity()));
2118
2119
42
  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false,
2120
42
                          TypeInfo, CharUnits::fromQuantity(4),
2121
42
                          /*AllowHigherAlign*/ true);
2122
42
}
2123
2124
bool X86_32TargetCodeGenInfo::isStructReturnInRegABI(
2125
3.14k
    const llvm::Triple &Triple, const CodeGenOptions &Opts) {
2126
3.14k
  assert(Triple.getArch() == llvm::Triple::x86);
2127
2128
0
  switch (Opts.getStructReturnConvention()) {
2129
3.13k
  case CodeGenOptions::SRCK_Default:
2130
3.13k
    break;
2131
3
  case CodeGenOptions::SRCK_OnStack:  // -fpcc-struct-return
2132
3
    return false;
2133
3
  case CodeGenOptions::SRCK_InRegs:  // -freg-struct-return
2134
3
    return true;
2135
3.14k
  }
2136
2137
3.13k
  if (Triple.isOSDarwin() || 
Triple.isOSIAMCU()2.93k
)
2138
207
    return true;
2139
2140
2.93k
  switch (Triple.getOS()) {
2141
1
  case llvm::Triple::DragonFly:
2142
1
  case llvm::Triple::FreeBSD:
2143
2
  case llvm::Triple::OpenBSD:
2144
450
  case llvm::Triple::Win32:
2145
450
    return true;
2146
2.48k
  default:
2147
2.48k
    return false;
2148
2.93k
  }
2149
2.93k
}
2150
2151
static void addX86InterruptAttrs(const FunctionDecl *FD, llvm::GlobalValue *GV,
2152
194k
                                 CodeGen::CodeGenModule &CGM) {
2153
194k
  if (!FD->hasAttr<AnyX86InterruptAttr>())
2154
194k
    return;
2155
2156
25
  llvm::Function *Fn = cast<llvm::Function>(GV);
2157
25
  Fn->setCallingConv(llvm::CallingConv::X86_INTR);
2158
25
  if (FD->getNumParams() == 0)
2159
0
    return;
2160
2161
25
  auto PtrTy = cast<PointerType>(FD->getParamDecl(0)->getType());
2162
25
  llvm::Type *ByValTy = CGM.getTypes().ConvertType(PtrTy->getPointeeType());
2163
25
  llvm::Attribute NewAttr = llvm::Attribute::getWithByValType(
2164
25
    Fn->getContext(), ByValTy);
2165
25
  Fn->addParamAttr(0, NewAttr);
2166
25
}
2167
2168
void X86_32TargetCodeGenInfo::setTargetAttributes(
2169
80.4k
    const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
2170
80.4k
  if (GV->isDeclaration())
2171
46.2k
    return;
2172
34.1k
  if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
2173
24.9k
    if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
2174
2
      llvm::Function *Fn = cast<llvm::Function>(GV);
2175
2
      Fn->addFnAttr("stackrealign");
2176
2
    }
2177
2178
24.9k
    addX86InterruptAttrs(FD, GV, CGM);
2179
24.9k
  }
2180
34.1k
}
2181
2182
bool X86_32TargetCodeGenInfo::initDwarfEHRegSizeTable(
2183
                                               CodeGen::CodeGenFunction &CGF,
2184
0
                                               llvm::Value *Address) const {
2185
0
  CodeGen::CGBuilderTy &Builder = CGF.Builder;
2186
2187
0
  llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
2188
2189
  // 0-7 are the eight integer registers;  the order is different
2190
  //   on Darwin (for EH), but the range is the same.
2191
  // 8 is %eip.
2192
0
  AssignToArrayRange(Builder, Address, Four8, 0, 8);
2193
2194
0
  if (CGF.CGM.getTarget().getTriple().isOSDarwin()) {
2195
    // 12-16 are st(0..4).  Not sure why we stop at 4.
2196
    // These have size 16, which is sizeof(long double) on
2197
    // platforms with 8-byte alignment for that type.
2198
0
    llvm::Value *Sixteen8 = llvm::ConstantInt::get(CGF.Int8Ty, 16);
2199
0
    AssignToArrayRange(Builder, Address, Sixteen8, 12, 16);
2200
2201
0
  } else {
2202
    // 9 is %eflags, which doesn't get a size on Darwin for some
2203
    // reason.
2204
0
    Builder.CreateAlignedStore(
2205
0
        Four8, Builder.CreateConstInBoundsGEP1_32(CGF.Int8Ty, Address, 9),
2206
0
                               CharUnits::One());
2207
2208
    // 11-16 are st(0..5).  Not sure why we stop at 5.
2209
    // These have size 12, which is sizeof(long double) on
2210
    // platforms with 4-byte alignment for that type.
2211
0
    llvm::Value *Twelve8 = llvm::ConstantInt::get(CGF.Int8Ty, 12);
2212
0
    AssignToArrayRange(Builder, Address, Twelve8, 11, 16);
2213
0
  }
2214
2215
0
  return false;
2216
0
}
2217
2218
//===----------------------------------------------------------------------===//
2219
// X86-64 ABI Implementation
2220
//===----------------------------------------------------------------------===//
2221
2222
2223
namespace {
2224
/// The AVX ABI level for X86 targets.
2225
enum class X86AVXABILevel {
2226
  None,
2227
  AVX,
2228
  AVX512
2229
};
2230
2231
/// \p returns the size in bits of the largest (native) vector for \p AVXLevel.
2232
3.99k
static unsigned getNativeVectorSizeForAVXABI(X86AVXABILevel AVXLevel) {
2233
3.99k
  switch (AVXLevel) {
2234
3.06k
  case X86AVXABILevel::AVX512:
2235
3.06k
    return 512;
2236
699
  case X86AVXABILevel::AVX:
2237
699
    return 256;
2238
230
  case X86AVXABILevel::None:
2239
230
    return 128;
2240
3.99k
  }
2241
0
  llvm_unreachable("Unknown AVXLevel");
2242
0
}
2243
2244
/// X86_64ABIInfo - The X86_64 ABI information.
2245
class X86_64ABIInfo : public SwiftABIInfo {
2246
  enum Class {
2247
    Integer = 0,
2248
    SSE,
2249
    SSEUp,
2250
    X87,
2251
    X87Up,
2252
    ComplexX87,
2253
    NoClass,
2254
    Memory
2255
  };
2256
2257
  /// merge - Implement the X86_64 ABI merging algorithm.
2258
  ///
2259
  /// Merge an accumulating classification \arg Accum with a field
2260
  /// classification \arg Field.
2261
  ///
2262
  /// \param Accum - The accumulating classification. This should
2263
  /// always be either NoClass or the result of a previous merge
2264
  /// call. In addition, this should never be Memory (the caller
2265
  /// should just return Memory for the aggregate).
2266
  static Class merge(Class Accum, Class Field);
2267
2268
  /// postMerge - Implement the X86_64 ABI post merging algorithm.
2269
  ///
2270
  /// Post merger cleanup, reduces a malformed Hi and Lo pair to
2271
  /// final MEMORY or SSE classes when necessary.
2272
  ///
2273
  /// \param AggregateSize - The size of the current aggregate in
2274
  /// the classification process.
2275
  ///
2276
  /// \param Lo - The classification for the parts of the type
2277
  /// residing in the low word of the containing object.
2278
  ///
2279
  /// \param Hi - The classification for the parts of the type
2280
  /// residing in the higher words of the containing object.
2281
  ///
2282
  void postMerge(unsigned AggregateSize, Class &Lo, Class &Hi) const;
2283
2284
  /// classify - Determine the x86_64 register classes in which the
2285
  /// given type T should be passed.
2286
  ///
2287
  /// \param Lo - The classification for the parts of the type
2288
  /// residing in the low word of the containing object.
2289
  ///
2290
  /// \param Hi - The classification for the parts of the type
2291
  /// residing in the high word of the containing object.
2292
  ///
2293
  /// \param OffsetBase - The bit offset of this type in the
2294
  /// containing object.  Some parameters are classified different
2295
  /// depending on whether they straddle an eightbyte boundary.
2296
  ///
2297
  /// \param isNamedArg - Whether the argument in question is a "named"
2298
  /// argument, as used in AMD64-ABI 3.5.7.
2299
  ///
2300
  /// \param IsRegCall - Whether the calling conversion is regcall.
2301
  ///
2302
  /// If a word is unused its result will be NoClass; if a type should
2303
  /// be passed in Memory then at least the classification of \arg Lo
2304
  /// will be Memory.
2305
  ///
2306
  /// The \arg Lo class will be NoClass iff the argument is ignored.
2307
  ///
2308
  /// If the \arg Lo class is ComplexX87, then the \arg Hi class will
2309
  /// also be ComplexX87.
2310
  void classify(QualType T, uint64_t OffsetBase, Class &Lo, Class &Hi,
2311
                bool isNamedArg, bool IsRegCall = false) const;
2312
2313
  llvm::Type *GetByteVectorType(QualType Ty) const;
2314
  llvm::Type *GetSSETypeAtOffset(llvm::Type *IRType,
2315
                                 unsigned IROffset, QualType SourceTy,
2316
                                 unsigned SourceOffset) const;
2317
  llvm::Type *GetINTEGERTypeAtOffset(llvm::Type *IRType,
2318
                                     unsigned IROffset, QualType SourceTy,
2319
                                     unsigned SourceOffset) const;
2320
2321
  /// getIndirectResult - Give a source type \arg Ty, return a suitable result
2322
  /// such that the argument will be returned in memory.
2323
  ABIArgInfo getIndirectReturnResult(QualType Ty) const;
2324
2325
  /// getIndirectResult - Give a source type \arg Ty, return a suitable result
2326
  /// such that the argument will be passed in memory.
2327
  ///
2328
  /// \param freeIntRegs - The number of free integer registers remaining
2329
  /// available.
2330
  ABIArgInfo getIndirectResult(QualType Ty, unsigned freeIntRegs) const;
2331
2332
  ABIArgInfo classifyReturnType(QualType RetTy) const;
2333
2334
  ABIArgInfo classifyArgumentType(QualType Ty, unsigned freeIntRegs,
2335
                                  unsigned &neededInt, unsigned &neededSSE,
2336
                                  bool isNamedArg,
2337
                                  bool IsRegCall = false) const;
2338
2339
  ABIArgInfo classifyRegCallStructType(QualType Ty, unsigned &NeededInt,
2340
                                       unsigned &NeededSSE,
2341
                                       unsigned &MaxVectorWidth) const;
2342
2343
  ABIArgInfo classifyRegCallStructTypeImpl(QualType Ty, unsigned &NeededInt,
2344
                                           unsigned &NeededSSE,
2345
                                           unsigned &MaxVectorWidth) const;
2346
2347
  bool IsIllegalVectorType(QualType Ty) const;
2348
2349
  /// The 0.98 ABI revision clarified a lot of ambiguities,
2350
  /// unfortunately in ways that were not always consistent with
2351
  /// certain previous compilers.  In particular, platforms which
2352
  /// required strict binary compatibility with older versions of GCC
2353
  /// may need to exempt themselves.
2354
17
  bool honorsRevision0_98() const {
2355
17
    return !getTarget().getTriple().isOSDarwin();
2356
17
  }
2357
2358
  /// GCC classifies <1 x long long> as SSE but some platform ABIs choose to
2359
  /// classify it as INTEGER (for compatibility with older clang compilers).
2360
187
  bool classifyIntegerMMXAsSSE() const {
2361
    // Clang <= 3.8 did not do this.
2362
187
    if (getContext().getLangOpts().getClangABICompat() <=
2363
187
        LangOptions::ClangABI::Ver3_8)
2364
3
      return false;
2365
2366
184
    const llvm::Triple &Triple = getTarget().getTriple();
2367
184
    if (Triple.isOSDarwin() || 
Triple.getOS() == llvm::Triple::PS467
)
2368
122
      return false;
2369
62
    if (Triple.isOSFreeBSD() && 
Triple.getOSMajorVersion() >= 100
)
2370
0
      return false;
2371
62
    return true;
2372
62
  }
2373
2374
  // GCC classifies vectors of __int128 as memory.
2375
12.3k
  bool passInt128VectorsInMem() const {
2376
    // Clang <= 9.0 did not do this.
2377
12.3k
    if (getContext().getLangOpts().getClangABICompat() <=
2378
12.3k
        LangOptions::ClangABI::Ver9)
2379
36
      return false;
2380
2381
12.2k
    const llvm::Triple &T = getTarget().getTriple();
2382
12.2k
    return T.isOSLinux() || 
T.isOSNetBSD()11.2k
;
2383
12.3k
  }
2384
2385
  X86AVXABILevel AVXLevel;
2386
  // Some ABIs (e.g. X32 ABI and Native Client OS) use 32 bit pointers on
2387
  // 64-bit hardware.
2388
  bool Has64BitPointers;
2389
2390
public:
2391
  X86_64ABIInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel) :
2392
      SwiftABIInfo(CGT), AVXLevel(AVXLevel),
2393
25.2k
      Has64BitPointers(CGT.getDataLayout().getPointerSize(0) == 8) {
2394
25.2k
  }
2395
2396
76
  bool isPassedUsingAVXType(QualType type) const {
2397
76
    unsigned neededInt, neededSSE;
2398
    // The freeIntRegs argument doesn't matter here.
2399
76
    ABIArgInfo info = classifyArgumentType(type, 0, neededInt, neededSSE,
2400
76
                                           /*isNamedArg*/true);
2401
76
    if (info.isDirect()) {
2402
73
      llvm::Type *ty = info.getCoerceToType();
2403
73
      if (llvm::VectorType *vectorTy = dyn_cast_or_null<llvm::VectorType>(ty))
2404
2
        return vectorTy->getPrimitiveSizeInBits().getFixedSize() > 128;
2405
73
    }
2406
74
    return false;
2407
76
  }
2408
2409
  void computeInfo(CGFunctionInfo &FI) const override;
2410
2411
  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
2412
                    QualType Ty) const override;
2413
  Address EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
2414
                      QualType Ty) const override;
2415
2416
0
  bool has64BitPointers() const {
2417
0
    return Has64BitPointers;
2418
0
  }
2419
2420
  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
2421
302
                                    bool asReturnValue) const override {
2422
302
    return occupiesMoreThan(CGT, scalars, /*total*/ 4);
2423
302
  }
2424
0
  bool isSwiftErrorInRegister() const override {
2425
0
    return true;
2426
0
  }
2427
};
2428
2429
/// WinX86_64ABIInfo - The Windows X86_64 ABI information.
2430
class WinX86_64ABIInfo : public SwiftABIInfo {
2431
public:
2432
  WinX86_64ABIInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel)
2433
      : SwiftABIInfo(CGT), AVXLevel(AVXLevel),
2434
421
        IsMingw64(getTarget().getTriple().isWindowsGNUEnvironment()) {}
2435
2436
  void computeInfo(CGFunctionInfo &FI) const override;
2437
2438
  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
2439
                    QualType Ty) const override;
2440
2441
377
  bool isHomogeneousAggregateBaseType(QualType Ty) const override {
2442
    // FIXME: Assumes vectorcall is in use.
2443
377
    return isX86VectorTypeForVectorCall(getContext(), Ty);
2444
377
  }
2445
2446
  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
2447
419
                                         uint64_t NumMembers) const override {
2448
    // FIXME: Assumes vectorcall is in use.
2449
419
    return isX86VectorCallAggregateSmallEnough(NumMembers);
2450
419
  }
2451
2452
  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type *> scalars,
2453
25
                                    bool asReturnValue) const override {
2454
25
    return occupiesMoreThan(CGT, scalars, /*total*/ 4);
2455
25
  }
2456
2457
0
  bool isSwiftErrorInRegister() const override {
2458
0
    return true;
2459
0
  }
2460
2461
private:
2462
  ABIArgInfo classify(QualType Ty, unsigned &FreeSSERegs, bool IsReturnType,
2463
                      bool IsVectorCall, bool IsRegCall) const;
2464
  ABIArgInfo reclassifyHvaArgForVectorCall(QualType Ty, unsigned &FreeSSERegs,
2465
                                           const ABIArgInfo &current) const;
2466
2467
  X86AVXABILevel AVXLevel;
2468
2469
  bool IsMingw64;
2470
};
2471
2472
class X86_64TargetCodeGenInfo : public TargetCodeGenInfo {
2473
public:
2474
  X86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel)
2475
25.2k
      : TargetCodeGenInfo(std::make_unique<X86_64ABIInfo>(CGT, AVXLevel)) {}
2476
2477
76
  const X86_64ABIInfo &getABIInfo() const {
2478
76
    return static_cast<const X86_64ABIInfo&>(TargetCodeGenInfo::getABIInfo());
2479
76
  }
2480
2481
  /// Disable tail call on x86-64. The epilogue code before the tail jump blocks
2482
  /// autoreleaseRV/retainRV and autoreleaseRV/unsafeClaimRV optimizations.
2483
161
  bool markARCOptimizedReturnCallsAsNoTail() const override { return true; }
2484
2485
0
  int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
2486
0
    return 7;
2487
0
  }
2488
2489
  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
2490
0
                               llvm::Value *Address) const override {
2491
0
    llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);
2492
2493
    // 0-15 are the 16 integer registers.
2494
    // 16 is %rip.
2495
0
    AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16);
2496
0
    return false;
2497
0
  }
2498
2499
  llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
2500
                                  StringRef Constraint,
2501
907
                                  llvm::Type* Ty) const override {
2502
907
    return X86AdjustInlineAsmType(CGF, Constraint, Ty);
2503
907
  }
2504
2505
  bool isNoProtoCallVariadic(const CallArgList &args,
2506
424
                             const FunctionNoProtoType *fnType) const override {
2507
    // The default CC on x86-64 sets %al to the number of SSA
2508
    // registers used, and GCC sets this when calling an unprototyped
2509
    // function, so we override the default behavior.  However, don't do
2510
    // that when AVX types are involved: the ABI explicitly states it is
2511
    // undefined, and it doesn't work in practice because of how the ABI
2512
    // defines varargs anyway.
2513
424
    if (fnType->getCallConv() == CC_C) {
2514
424
      bool HasAVXType = false;
2515
424
      for (CallArgList::const_iterator
2516
498
             it = args.begin(), ie = args.end(); it != ie; 
++it74
) {
2517
76
        if (getABIInfo().isPassedUsingAVXType(it->Ty)) {
2518
2
          HasAVXType = true;
2519
2
          break;
2520
2
        }
2521
76
      }
2522
2523
424
      if (!HasAVXType)
2524
422
        return true;
2525
424
    }
2526
2527
2
    return TargetCodeGenInfo::isNoProtoCallVariadic(args, fnType);
2528
424
  }
2529
2530
  llvm::Constant *
2531
82
  getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override {
2532
82
    unsigned Sig = (0xeb << 0) | // jmp rel8
2533
82
                   (0x06 << 8) | //           .+0x08
2534
82
                   ('v' << 16) |
2535
82
                   ('2' << 24);
2536
82
    return llvm::ConstantInt::get(CGM.Int32Ty, Sig);
2537
82
  }
2538
2539
  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2540
397k
                           CodeGen::CodeGenModule &CGM) const override {
2541
397k
    if (GV->isDeclaration())
2542
223k
      return;
2543
173k
    if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
2544
161k
      if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
2545
1
        llvm::Function *Fn = cast<llvm::Function>(GV);
2546
1
        Fn->addFnAttr("stackrealign");
2547
1
      }
2548
2549
161k
      addX86InterruptAttrs(FD, GV, CGM);
2550
161k
    }
2551
173k
  }
2552
2553
  void checkFunctionCallABI(CodeGenModule &CGM, SourceLocation CallLoc,
2554
                            const FunctionDecl *Caller,
2555
                            const FunctionDecl *Callee,
2556
                            const CallArgList &Args) const override;
2557
};
2558
2559
static void initFeatureMaps(const ASTContext &Ctx,
2560
                            llvm::StringMap<bool> &CallerMap,
2561
                            const FunctionDecl *Caller,
2562
                            llvm::StringMap<bool> &CalleeMap,
2563
13.4k
                            const FunctionDecl *Callee) {
2564
13.4k
  if (CalleeMap.empty() && 
CallerMap.empty()6.25k
) {
2565
    // The caller is potentially nullptr in the case where the call isn't in a
2566
    // function.  In this case, the getFunctionFeatureMap ensures we just get
2567
    // the TU level setting (since it cannot be modified by 'target'..
2568
6.25k
    Ctx.getFunctionFeatureMap(CallerMap, Caller);
2569
6.25k
    Ctx.getFunctionFeatureMap(CalleeMap, Callee);
2570
6.25k
  }
2571
13.4k
}
2572
2573
static bool checkAVXParamFeature(DiagnosticsEngine &Diag,
2574
                                 SourceLocation CallLoc,
2575
                                 const llvm::StringMap<bool> &CallerMap,
2576
                                 const llvm::StringMap<bool> &CalleeMap,
2577
                                 QualType Ty, StringRef Feature,
2578
13.4k
                                 bool IsArgument) {
2579
13.4k
  bool CallerHasFeat = CallerMap.lookup(Feature);
2580
13.4k
  bool CalleeHasFeat = CalleeMap.lookup(Feature);
2581
13.4k
  if (!CallerHasFeat && 
!CalleeHasFeat62
)
2582
56
    return Diag.Report(CallLoc, diag::warn_avx_calling_convention)
2583
56
           << IsArgument << Ty << Feature;
2584
2585
  // Mixing calling conventions here is very clearly an error.
2586
13.3k
  if (!CallerHasFeat || 
!CalleeHasFeat13.3k
)
2587
6
    return Diag.Report(CallLoc, diag::err_avx_calling_convention)
2588
6
           << IsArgument << Ty << Feature;
2589
2590
  // Else, both caller and callee have the required feature, so there is no need
2591
  // to diagnose.
2592
13.3k
  return false;
2593
13.3k
}
2594
2595
static bool checkAVXParam(DiagnosticsEngine &Diag, ASTContext &Ctx,
2596
                          SourceLocation CallLoc,
2597
                          const llvm::StringMap<bool> &CallerMap,
2598
                          const llvm::StringMap<bool> &CalleeMap, QualType Ty,
2599
13.4k
                          bool IsArgument) {
2600
13.4k
  uint64_t Size = Ctx.getTypeSize(Ty);
2601
13.4k
  if (Size > 256)
2602
6.35k
    return checkAVXParamFeature(Diag, CallLoc, CallerMap, CalleeMap, Ty,
2603
6.35k
                                "avx512f", IsArgument);
2604
2605
7.06k
  if (Size > 128)
2606
7.06k
    return checkAVXParamFeature(Diag, CallLoc, CallerMap, CalleeMap, Ty, "avx",
2607
7.06k
                                IsArgument);
2608
2609
0
  return false;
2610
7.06k
}
2611
2612
void X86_64TargetCodeGenInfo::checkFunctionCallABI(
2613
    CodeGenModule &CGM, SourceLocation CallLoc, const FunctionDecl *Caller,
2614
291k
    const FunctionDecl *Callee, const CallArgList &Args) const {
2615
291k
  llvm::StringMap<bool> CallerMap;
2616
291k
  llvm::StringMap<bool> CalleeMap;
2617
291k
  unsigned ArgIndex = 0;
2618
2619
  // We need to loop through the actual call arguments rather than the the
2620
  // function's parameters, in case this variadic.
2621
488k
  for (const CallArg &Arg : Args) {
2622
    // The "avx" feature changes how vectors >128 in size are passed. "avx512f"
2623
    // additionally changes how vectors >256 in size are passed. Like GCC, we
2624
    // warn when a function is called with an argument where this will change.
2625
    // Unlike GCC, we also error when it is an obvious ABI mismatch, that is,
2626
    // the caller and callee features are mismatched.
2627
    // Unfortunately, we cannot do this diagnostic in SEMA, since the callee can
2628
    // change its ABI with attribute-target after this call.
2629
488k
    if (Arg.getType()->isVectorType() &&
2630
488k
        
CGM.getContext().getTypeSize(Arg.getType()) > 12814.6k
) {
2631
7.75k
      initFeatureMaps(CGM.getContext(), CallerMap, Caller, CalleeMap, Callee);
2632
7.75k
      QualType Ty = Arg.getType();
2633
      // The CallArg seems to have desugared the type already, so for clearer
2634
      // diagnostics, replace it with the type in the FunctionDecl if possible.
2635
7.75k
      if (ArgIndex < Callee->getNumParams())
2636
7.72k
        Ty = Callee->getParamDecl(ArgIndex)->getType();
2637
2638
7.75k
      if (checkAVXParam(CGM.getDiags(), CGM.getContext(), CallLoc, CallerMap,
2639
7.75k
                        CalleeMap, Ty, /*IsArgument*/ true))
2640
54
        return;
2641
7.75k
    }
2642
488k
    ++ArgIndex;
2643
488k
  }
2644
2645
  // Check return always, as we don't have a good way of knowing in codegen
2646
  // whether this value is used, tail-called, etc.
2647
291k
  if (Callee->getReturnType()->isVectorType() &&
2648
291k
      
CGM.getContext().getTypeSize(Callee->getReturnType()) > 12810.0k
) {
2649
5.66k
    initFeatureMaps(CGM.getContext(), CallerMap, Caller, CalleeMap, Callee);
2650
5.66k
    checkAVXParam(CGM.getDiags(), CGM.getContext(), CallLoc, CallerMap,
2651
5.66k
                  CalleeMap, Callee->getReturnType(),
2652
5.66k
                  /*IsArgument*/ false);
2653
5.66k
  }
2654
291k
}
2655
2656
107
static std::string qualifyWindowsLibrary(llvm::StringRef Lib) {
2657
  // If the argument does not end in .lib, automatically add the suffix.
2658
  // If the argument contains a space, enclose it in quotes.
2659
  // This matches the behavior of MSVC.
2660
107
  bool Quote = Lib.contains(' ');
2661
107
  std::string ArgStr = Quote ? 
"\""4
:
""103
;
2662
107
  ArgStr += Lib;
2663
107
  if (!Lib.endswith_insensitive(".lib") && 
!Lib.endswith_insensitive(".a")95
)
2664
95
    ArgStr += ".lib";
2665
107
  ArgStr += Quote ? 
"\""4
:
""103
;
2666
107
  return ArgStr;
2667
107
}
2668
2669
class WinX86_32TargetCodeGenInfo : public X86_32TargetCodeGenInfo {
2670
public:
2671
  WinX86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
2672
        bool DarwinVectorABI, bool RetSmallStructInRegABI, bool Win32StructABI,
2673
        unsigned NumRegisterParameters)
2674
    : X86_32TargetCodeGenInfo(CGT, DarwinVectorABI, RetSmallStructInRegABI,
2675
450
        Win32StructABI, NumRegisterParameters, false) {}
2676
2677
  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2678
                           CodeGen::CodeGenModule &CGM) const override;
2679
2680
  void getDependentLibraryOption(llvm::StringRef Lib,
2681
35
                                 llvm::SmallString<24> &Opt) const override {
2682
35
    Opt = "/DEFAULTLIB:";
2683
35
    Opt += qualifyWindowsLibrary(Lib);
2684
35
  }
2685
2686
  void getDetectMismatchOption(llvm::StringRef Name,
2687
                               llvm::StringRef Value,
2688
2
                               llvm::SmallString<32> &Opt) const override {
2689
2
    Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
2690
2
  }
2691
};
2692
2693
static void addStackProbeTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2694
17.5k
                                          CodeGen::CodeGenModule &CGM) {
2695
17.5k
  if (llvm::Function *Fn = dyn_cast_or_null<llvm::Function>(GV)) {
2696
2697
15.1k
    if (CGM.getCodeGenOpts().StackProbeSize != 4096)
2698
1
      Fn->addFnAttr("stack-probe-size",
2699
1
                    llvm::utostr(CGM.getCodeGenOpts().StackProbeSize));
2700
15.1k
    if (CGM.getCodeGenOpts().NoStackArgProbe)
2701
4
      Fn->addFnAttr("no-stack-arg-probe");
2702
15.1k
  }
2703
17.5k
}
2704
2705
void WinX86_32TargetCodeGenInfo::setTargetAttributes(
2706
17.7k
    const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
2707
17.7k
  X86_32TargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
2708
17.7k
  if (GV->isDeclaration())
2709
10.1k
    return;
2710
7.65k
  addStackProbeTargetAttributes(D, GV, CGM);
2711
7.65k
}
2712
2713
class WinX86_64TargetCodeGenInfo : public TargetCodeGenInfo {
2714
public:
2715
  WinX86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
2716
                             X86AVXABILevel AVXLevel)
2717
408
      : TargetCodeGenInfo(std::make_unique<WinX86_64ABIInfo>(CGT, AVXLevel)) {}
2718
2719
  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2720
                           CodeGen::CodeGenModule &CGM) const override;
2721
2722
0
  int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
2723
0
    return 7;
2724
0
  }
2725
2726
  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
2727
0
                               llvm::Value *Address) const override {
2728
0
    llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);
2729
2730
    // 0-15 are the 16 integer registers.
2731
    // 16 is %rip.
2732
0
    AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16);
2733
0
    return false;
2734
0
  }
2735
2736
  void getDependentLibraryOption(llvm::StringRef Lib,
2737
49
                                 llvm::SmallString<24> &Opt) const override {
2738
49
    Opt = "/DEFAULTLIB:";
2739
49
    Opt += qualifyWindowsLibrary(Lib);
2740
49
  }
2741
2742
  void getDetectMismatchOption(llvm::StringRef Name,
2743
                               llvm::StringRef Value,
2744
4
                               llvm::SmallString<32> &Opt) const override {
2745
4
    Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
2746
4
  }
2747
};
2748
2749
void WinX86_64TargetCodeGenInfo::setTargetAttributes(
2750
19.8k
    const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
2751
19.8k
  TargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
2752
19.8k
  if (GV->isDeclaration())
2753
10.8k
    return;
2754
9.07k
  if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
2755
7.96k
    if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
2756
0
      llvm::Function *Fn = cast<llvm::Function>(GV);
2757
0
      Fn->addFnAttr("stackrealign");
2758
0
    }
2759
2760
7.96k
    addX86InterruptAttrs(FD, GV, CGM);
2761
7.96k
  }
2762
2763
9.07k
  addStackProbeTargetAttributes(D, GV, CGM);
2764
9.07k
}
2765
}
2766
2767
void X86_64ABIInfo::postMerge(unsigned AggregateSize, Class &Lo,
2768
13.3k
                              Class &Hi) const {
2769
  // AMD64-ABI 3.2.3p2: Rule 5. Then a post merger cleanup is done:
2770
  //
2771
  // (a) If one of the classes is Memory, the whole argument is passed in
2772
  //     memory.
2773
  //
2774
  // (b) If X87UP is not preceded by X87, the whole argument is passed in
2775
  //     memory.
2776
  //
2777
  // (c) If the size of the aggregate exceeds two eightbytes and the first
2778
  //     eightbyte isn't SSE or any other eightbyte isn't SSEUP, the whole
2779
  //     argument is passed in memory. NOTE: This is necessary to keep the
2780
  //     ABI working for processors that don't support the __m256 type.
2781
  //
2782
  // (d) If SSEUP is not preceded by SSE or SSEUP, it is converted to SSE.
2783
  //
2784
  // Some of these are enforced by the merging logic.  Others can arise
2785
  // only with unions; for example:
2786
  //   union { _Complex double; unsigned; }
2787
  //
2788
  // Note that clauses (b) and (c) were added in 0.98.
2789
  //
2790
13.3k
  if (Hi == Memory)
2791
0
    Lo = Memory;
2792
13.3k
  if (Hi == X87Up && 
Lo != X87372
&&
honorsRevision0_98()17
)
2793
15
    Lo = Memory;
2794
13.3k
  if (AggregateSize > 128 && 
(321
Lo != SSE321
||
Hi != SSEUp24
))
2795
297
    Lo = Memory;
2796
13.3k
  if (Hi == SSEUp && 
Lo != SSE33
)
2797
1
    Hi = SSE;
2798
13.3k
}
2799
2800
20.8k
X86_64ABIInfo::Class X86_64ABIInfo::merge(Class Accum, Class Field) {
2801
  // AMD64-ABI 3.2.3p2: Rule 4. Each field of an object is
2802
  // classified recursively so that always two fields are
2803
  // considered. The resulting class is calculated according to
2804
  // the classes of the fields in the eightbyte:
2805
  //
2806
  // (a) If both classes are equal, this is the resulting class.
2807
  //
2808
  // (b) If one of the classes is NO_CLASS, the resulting class is
2809
  // the other class.
2810
  //
2811
  // (c) If one of the classes is MEMORY, the result is the MEMORY
2812
  // class.
2813
  //
2814
  // (d) If one of the classes is INTEGER, the result is the
2815
  // INTEGER.
2816
  //
2817
  // (e) If one of the classes is X87, X87UP, COMPLEX_X87 class,
2818
  // MEMORY is used as class.
2819
  //
2820
  // (f) Otherwise class SSE is used.
2821
2822
  // Accum should never be memory (we should have returned) or
2823
  // ComplexX87 (because this cannot be passed in a structure).
2824
20.8k
  assert((Accum != Memory && Accum != ComplexX87) &&
2825
20.8k
         "Invalid accumulated classification during merge.");
2826
20.8k
  if (Accum == Field || 
Field == NoClass11.2k
)
2827
11.5k
    return Accum;
2828
9.34k
  if (Field == Memory)
2829
17
    return Memory;
2830
9.32k
  if (Accum == NoClass)
2831
9.22k
    return Field;
2832
101
  if (Accum == Integer || 
Field == Integer73
)
2833
98
    return Integer;
2834
3
  if (Field == X87 || Field == X87Up || Field == ComplexX87 ||
2835
3
      Accum == X87 || 
Accum == X87Up0
)
2836
3
    return Memory;
2837
0
  return SSE;
2838
3
}
2839
2840
void X86_64ABIInfo::classify(QualType Ty, uint64_t OffsetBase, Class &Lo,
2841
469k
                             Class &Hi, bool isNamedArg, bool IsRegCall) const {
2842
  // FIXME: This code can be simplified by introducing a simple value class for
2843
  // Class pairs with appropriate constructor methods for the various
2844
  // situations.
2845
2846
  // FIXME: Some of the split computations are wrong; unaligned vectors
2847
  // shouldn't be passed in registers for example, so there is no chance they
2848
  // can straddle an eightbyte. Verify & simplify.
2849
2850
469k
  Lo = Hi = NoClass;
2851
2852
469k
  Class &Current = OffsetBase < 64 ? 
Lo467k
:
Hi2.03k
;
2853
469k
  Current = Memory;
2854
2855
469k
  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
2856
181k
    BuiltinType::Kind k = BT->getKind();
2857
2858
181k
    if (k == BuiltinType::Void) {
2859
65.0k
      Current = NoClass;
2860
116k
    } else if (k == BuiltinType::Int128 || 
k == BuiltinType::UInt128116k
) {
2861
32
      Lo = Integer;
2862
32
      Hi = Integer;
2863
116k
    } else if (k >= BuiltinType::Bool && 
k <= BuiltinType::LongLong116k
) {
2864
111k
      Current = Integer;
2865
111k
    } else 
if (5.45k
k == BuiltinType::Float5.45k
||
k == BuiltinType::Double3.11k
||
2866
5.45k
               
k == BuiltinType::Float161.40k
) {
2867
4.22k
      Current = SSE;
2868
4.22k
    } else 
if (1.23k
k == BuiltinType::LongDouble1.23k
) {
2869
998
      const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
2870
998
      if (LDF == &llvm::APFloat::IEEEquad()) {
2871
40
        Lo = SSE;
2872
40
        Hi = SSEUp;
2873
958
      } else if (LDF == &llvm::APFloat::x87DoubleExtended()) {
2874
936
        Lo = X87;
2875
936
        Hi = X87Up;
2876
936
      } else 
if (22
LDF == &llvm::APFloat::IEEEdouble()22
) {
2877
22
        Current = SSE;
2878
22
      } else
2879
0
        llvm_unreachable("unexpected long double representation!");
2880
998
    }
2881
    // FIXME: _Decimal32 and _Decimal64 are SSE.
2882
    // FIXME: _float128 and _Decimal128 are (SSE, SSEUp).
2883
181k
    return;
2884
181k
  }
2885
2886
287k
  if (const EnumType *ET = Ty->getAs<EnumType>()) {
2887
    // Classify the underlying integer type.
2888
961
    classify(ET->getDecl()->getIntegerType(), OffsetBase, Lo, Hi, isNamedArg);
2889
961
    return;
2890
961
  }
2891
2892
286k
  if (Ty->hasPointerRepresentation()) {
2893
264k
    Current = Integer;
2894
264k
    return;
2895
264k
  }
2896
2897
21.4k
  if (Ty->isMemberPointerType()) {
2898
126
    if (Ty->isMemberFunctionPointerType()) {
2899
77
      if (Has64BitPointers) {
2900
        // If Has64BitPointers, this is an {i64, i64}, so classify both
2901
        // Lo and Hi now.
2902
69
        Lo = Hi = Integer;
2903
69
      } else {
2904
        // Otherwise, with 32-bit pointers, this is an {i32, i32}. If that
2905
        // straddles an eightbyte boundary, Hi should be classified as well.
2906
8
        uint64_t EB_FuncPtr = (OffsetBase) / 64;
2907
8
        uint64_t EB_ThisAdj = (OffsetBase + 64 - 1) / 64;
2908
8
        if (EB_FuncPtr != EB_ThisAdj) {
2909
2
          Lo = Hi = Integer;
2910
6
        } else {
2911
6
          Current = Integer;
2912
6
        }
2913
8
      }
2914
77
    } else {
2915
49
      Current = Integer;
2916
49
    }
2917
126
    return;
2918
126
  }
2919
2920
21.3k
  if (const VectorType *VT = Ty->getAs<VectorType>()) {
2921
6.52k
    uint64_t Size = getContext().getTypeSize(VT);
2922
6.52k
    if (Size == 1 || Size == 8 || 
Size == 166.52k
||
Size == 326.52k
) {
2923
      // gcc passes the following as integer:
2924
      // 4 bytes - <4 x char>, <2 x short>, <1 x int>, <1 x float>
2925
      // 2 bytes - <2 x char>, <1 x short>
2926
      // 1 byte  - <1 x char>
2927
5
      Current = Integer;
2928
2929
      // If this type crosses an eightbyte boundary, it should be
2930
      // split.
2931
5
      uint64_t EB_Lo = (OffsetBase) / 64;
2932
5
      uint64_t EB_Hi = (OffsetBase + Size - 1) / 64;
2933
5
      if (EB_Lo != EB_Hi)
2934
0
        Hi = Lo;
2935
6.52k
    } else if (Size == 64) {
2936
187
      QualType ElementType = VT->getElementType();
2937
2938
      // gcc passes <1 x double> in memory. :(
2939
187
      if (ElementType->isSpecificBuiltinType(BuiltinType::Double))
2940
0
        return;
2941
2942
      // gcc passes <1 x long long> as SSE but clang used to unconditionally
2943
      // pass them as integer.  For platforms where clang is the de facto
2944
      // platform compiler, we must continue to use integer.
2945
187
      if (!classifyIntegerMMXAsSSE() &&
2946
187
          
(125
ElementType->isSpecificBuiltinType(BuiltinType::LongLong)125
||
2947
125
           
ElementType->isSpecificBuiltinType(BuiltinType::ULongLong)45
||
2948
125
           
ElementType->isSpecificBuiltinType(BuiltinType::Long)45
||
2949
125
           
ElementType->isSpecificBuiltinType(BuiltinType::ULong)45
))
2950
80
        Current = Integer;
2951
107
      else
2952
107
        Current = SSE;
2953
2954
      // If this type crosses an eightbyte boundary, it should be
2955
      // split.
2956
187
      if (OffsetBase && 
OffsetBase != 640
)
2957
0
        Hi = Lo;
2958
6.33k
    } else if (Size == 128 ||
2959
6.33k
               
(3.78k
isNamedArg3.78k
&&
Size <= getNativeVectorSizeForAVXABI(AVXLevel)3.75k
)) {
2960
6.14k
      QualType ElementType = VT->getElementType();
2961
2962
      // gcc passes 256 and 512 bit <X x __int128> vectors in memory. :(
2963
6.14k
      if (passInt128VectorsInMem() && 
Size != 128519
&&
2964
6.14k
          
(256
ElementType->isSpecificBuiltinType(BuiltinType::Int128)256
||
2965
256
           ElementType->isSpecificBuiltinType(BuiltinType::UInt128)))
2966
6
        return;
2967
2968
      // Arguments of 256-bits are split into four eightbyte chunks. The
2969
      // least significant one belongs to class SSE and all the others to class
2970
      // SSEUP. The original Lo and Hi design considers that types can't be
2971
      // greater than 128-bits, so a 64-bit split in Hi and Lo makes sense.
2972
      // This design isn't correct for 256-bits, but since there're no cases
2973
      // where the upper parts would need to be inspected, avoid adding
2974
      // complexity and just consider Hi to match the 64-256 part.
2975
      //
2976
      // Note that per 3.5.7 of AMD64-ABI, 256-bit args are only passed in
2977
      // registers if they are "named", i.e. not part of the "..." of a
2978
      // variadic function.
2979
      //
2980
      // Similarly, per 3.2.3. of the AVX512 draft, 512-bits ("named") args are
2981
      // split into eight eightbyte chunks, one SSE and seven SSEUP.
2982
6.14k
      Lo = SSE;
2983
6.14k
      Hi = SSEUp;
2984
6.14k
    }
2985
6.52k
    return;
2986
6.52k
  }
2987
2988
14.7k
  if (const ComplexType *CT = Ty->getAs<ComplexType>()) {
2989
409
    QualType ET = getContext().getCanonicalType(CT->getElementType());
2990
2991
409
    uint64_t Size = getContext().getTypeSize(Ty);
2992
409
    if (ET->isIntegralOrEnumerationType()) {
2993
34
      if (Size <= 64)
2994
30
        Current = Integer;
2995
4
      else if (Size <= 128)
2996
4
        Lo = Hi = Integer;
2997
375
    } else if (ET->isFloat16Type() || 
ET == getContext().FloatTy363
) {
2998
153
      Current = SSE;
2999
222
    } else if (ET == getContext().DoubleTy) {
3000
113
      Lo = Hi = SSE;
3001
113
    } else 
if (109
ET == getContext().LongDoubleTy109
) {
3002
108
      const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
3003
108
      if (LDF == &llvm::APFloat::IEEEquad())
3004
8
        Current = Memory;
3005
100
      else if (LDF == &llvm::APFloat::x87DoubleExtended())
3006
92
        Current = ComplexX87;
3007
8
      else if (LDF == &llvm::APFloat::IEEEdouble())
3008
8
        Lo = Hi = SSE;
3009
0
      else
3010
0
        llvm_unreachable("unexpected long double representation!");
3011
108
    }
3012
3013
    // If this complex type crosses an eightbyte boundary then it
3014
    // should be split.
3015
409
    uint64_t EB_Real = (OffsetBase) / 64;
3016
409
    uint64_t EB_Imag = (OffsetBase + getContext().getTypeSize(ET)) / 64;
3017
409
    if (Hi == NoClass && 
EB_Real != EB_Imag284
)
3018
104
      Hi = Lo;
3019
3020
409
    return;
3021
409
  }
3022
3023
14.3k
  if (const auto *EITy = Ty->getAs<BitIntType>()) {
3024
94
    if (EITy->getNumBits() <= 64)
3025
72
      Current = Integer;
3026
22
    else if (EITy->getNumBits() <= 128)
3027
22
      Lo = Hi = Integer;
3028
    // Larger values need to get passed in memory.
3029
94
    return;
3030
94
  }
3031
3032
14.2k
  if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) {
3033
    // Arrays are treated like structures.
3034
3035
58
    uint64_t Size = getContext().getTypeSize(Ty);
3036
3037
    // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
3038
    // than eight eightbytes, ..., it has class MEMORY.
3039
    // regcall ABI doesn't have limitation to an object. The only limitation
3040
    // is the free registers, which will be checked in computeInfo.
3041
58
    if (!IsRegCall && 
Size > 51248
)
3042
0
      return;
3043
3044
    // AMD64-ABI 3.2.3p2: Rule 1. If ..., or it contains unaligned
3045
    // fields, it has class MEMORY.
3046
    //
3047
    // Only need to check alignment of array base.
3048
58
    if (OffsetBase % getContext().getTypeAlign(AT->getElementType()))
3049
0
      return;
3050
3051
    // Otherwise implement simplified merge. We could be smarter about
3052
    // this, but it isn't worth it and would be harder to verify.
3053
58
    Current = NoClass;
3054
58
    uint64_t EltSize = getContext().getTypeSize(AT->getElementType());
3055
58
    uint64_t ArraySize = AT->getSize().getZExtValue();
3056
3057
    // The only case a 256-bit wide vector could be used is when the array
3058
    // contains a single 256-bit element. Since Lo and Hi logic isn't extended
3059
    // to work for sizes wider than 128, early check and fallback to memory.
3060
    //
3061
58
    if (Size > 128 &&
3062
58
        
(19
Size != EltSize19
||
Size > getNativeVectorSizeForAVXABI(AVXLevel)4
))
3063
15
      return;
3064
3065
197
    
for (uint64_t i=0, Offset=OffsetBase; 43
i<ArraySize;
++i, Offset += EltSize154
) {
3066
154
      Class FieldLo, FieldHi;
3067
154
      classify(AT->getElementType(), Offset, FieldLo, FieldHi, isNamedArg);
3068
154
      Lo = merge(Lo, FieldLo);
3069
154
      Hi = merge(Hi, FieldHi);
3070
154
      if (Lo == Memory || Hi == Memory)
3071
0
        break;
3072
154
    }
3073
3074
43
    postMerge(Size, Lo, Hi);
3075
43
    assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp array classification.");
3076
0
    return;
3077
58
  }
3078
3079
14.2k
  if (const RecordType *RT = Ty->getAs<RecordType>()) {
3080
13.9k
    uint64_t Size = getContext().getTypeSize(Ty);
3081
3082
    // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
3083
    // than eight eightbytes, ..., it has class MEMORY.
3084
13.9k
    if (Size > 512)
3085
141
      return;
3086
3087
    // AMD64-ABI 3.2.3p2: Rule 2. If a C++ object has either a non-trivial
3088
    // copy constructor or a non-trivial destructor, it is passed by invisible
3089
    // reference.
3090
13.7k
    if (getRecordArgABI(RT, getCXXABI()))
3091
500
      return;
3092
3093
13.2k
    const RecordDecl *RD = RT->getDecl();
3094
3095
    // Assume variable sized types are passed in memory.
3096
13.2k
    if (RD->hasFlexibleArrayMember())
3097
0
      return;
3098
3099
13.2k
    const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
3100
3101
    // Reset Lo class, this will be recomputed.
3102
13.2k
    Current = NoClass;
3103
3104
    // If this is a C++ record, classify the bases first.
3105
13.2k
    if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
3106
12.7k
      for (const auto &I : CXXRD->bases()) {
3107
1.10k
        assert(!I.isVirtual() && !I.getType()->isDependentType() &&
3108
1.10k
               "Unexpected base class!");
3109
0
        const auto *Base =
3110
1.10k
            cast<CXXRecordDecl>(I.getType()->castAs<RecordType>()->getDecl());
3111
3112
        // Classify this field.
3113
        //
3114
        // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate exceeds a
3115
        // single eightbyte, each is classified separately. Each eightbyte gets
3116
        // initialized to class NO_CLASS.
3117
1.10k
        Class FieldLo, FieldHi;
3118
1.10k
        uint64_t Offset =
3119
1.10k
          OffsetBase + getContext().toBits(Layout.getBaseClassOffset(Base));
3120
1.10k
        classify(I.getType(), Offset, FieldLo, FieldHi, isNamedArg);
3121
1.10k
        Lo = merge(Lo, FieldLo);
3122
1.10k
        Hi = merge(Hi, FieldHi);
3123
1.10k
        if (Lo == Memory || 
Hi == Memory1.10k
) {
3124
6
          postMerge(Size, Lo, Hi);
3125
6
          return;
3126
6
        }
3127
1.10k
      }
3128
12.7k
    }
3129
3130
    // Classify the fields one at a time, merging the results.
3131
13.2k
    unsigned idx = 0;
3132
13.2k
    bool UseClang11Compat = getContext().getLangOpts().getClangABICompat() <=
3133
13.2k
                                LangOptions::ClangABI::Ver11 ||
3134
13.2k
                            
getContext().getTargetInfo().getTriple().isPS4()13.1k
;
3135
13.2k
    bool IsUnion = RT->isUnionType() && 
!UseClang11Compat77
;
3136
3137
13.2k
    for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
3138
22.4k
           i != e; 
++i, ++idx9.16k
) {
3139
9.48k
      uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx);
3140
9.48k
      bool BitField = i->isBitField();
3141
3142
      // Ignore padding bit-fields.
3143
9.48k
      if (BitField && 
i->isUnnamedBitfield()51
)
3144
12
        continue;
3145
3146
      // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger than
3147
      // eight eightbytes, or it contains unaligned fields, it has class MEMORY.
3148
      //
3149
      // The only case a 256-bit or a 512-bit wide vector could be used is when
3150
      // the struct contains a single 256-bit or 512-bit element. Early check
3151
      // and fallback to memory.
3152
      //
3153
      // FIXME: Extended the Lo and Hi logic properly to work for size wider
3154
      // than 128.
3155
9.47k
      if (Size > 128 &&
3156
9.47k
          
(318
(318
!IsUnion318
&&
Size != getContext().getTypeSize(i->getType())307
) ||
3157
318
           
Size > getNativeVectorSizeForAVXABI(AVXLevel)86
)) {
3158
285
        Lo = Memory;
3159
285
        postMerge(Size, Lo, Hi);
3160
285
        return;
3161
285
      }
3162
      // Note, skip this test for bit-fields, see below.
3163
9.18k
      if (!BitField && 
Offset % getContext().getTypeAlign(i->getType())9.14k
) {
3164
20
        Lo = Memory;
3165
20
        postMerge(Size, Lo, Hi);
3166
20
        return;
3167
20
      }
3168
3169
      // Classify this field.
3170
      //
3171
      // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate
3172
      // exceeds a single eightbyte, each is classified
3173
      // separately. Each eightbyte gets initialized to class
3174
      // NO_CLASS.
3175
9.16k
      Class FieldLo, FieldHi;
3176
3177
      // Bit-fields require special handling, they do not force the
3178
      // structure to be passed in memory even if unaligned, and
3179
      // therefore they can straddle an eightbyte.
3180
9.16k
      if (BitField) {
3181
39
        assert(!i->isUnnamedBitfield());
3182
0
        uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx);
3183
39
        uint64_t Size = i->getBitWidthValue(getContext());
3184
3185
39
        uint64_t EB_Lo = Offset / 64;
3186
39
        uint64_t EB_Hi = (Offset + Size - 1) / 64;
3187
3188
39
        if (EB_Lo) {
3189
0
          assert(EB_Hi == EB_Lo && "Invalid classification, type > 16 bytes.");
3190
0
          FieldLo = NoClass;
3191
0
          FieldHi = Integer;
3192
39
        } else {
3193
39
          FieldLo = Integer;
3194
39
          FieldHi = EB_Hi ? 
Integer0
: NoClass;
3195
39
        }
3196
39
      } else
3197
9.12k
        classify(i->getType(), Offset, FieldLo, FieldHi, isNamedArg);
3198
0
      Lo = merge(Lo, FieldLo);
3199
9.16k
      Hi = merge(Hi, FieldHi);
3200
9.16k
      if (Lo == Memory || 
Hi == Memory9.15k
)
3201
14
        break;
3202
9.16k
    }
3203
3204
12.9k
    postMerge(Size, Lo, Hi);
3205
12.9k
  }
3206
14.2k
}
3207
3208
373
ABIArgInfo X86_64ABIInfo::getIndirectReturnResult(QualType Ty) const {
3209
  // If this is a scalar LLVM value then assume LLVM will pass it in the right
3210
  // place naturally.
3211
373
  if (!isAggregateTypeForABI(Ty)) {
3212
    // Treat an enum type as its underlying type.
3213
150
    if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3214
0
      Ty = EnumTy->getDecl()->getIntegerType();
3215
3216
150
    if (Ty->isBitIntType())
3217
0
      return getNaturalAlignIndirect(Ty);
3218
3219
150
    return (isPromotableIntegerTypeForABI(Ty) ? 
ABIArgInfo::getExtend(Ty)0
3220
150
                                              : ABIArgInfo::getDirect());
3221
150
  }
3222
3223
223
  return getNaturalAlignIndirect(Ty);
3224
373
}
3225
3226
3.02k
bool X86_64ABIInfo::IsIllegalVectorType(QualType Ty) const {
3227
3.02k
  if (const VectorType *VecTy = Ty->getAs<VectorType>()) {
3228
143
    uint64_t Size = getContext().getTypeSize(VecTy);
3229
143
    unsigned LargestVector = getNativeVectorSizeForAVXABI(AVXLevel);
3230
143
    if (Size <= 64 || 
Size > LargestVector137
)
3231
120
      return true;
3232
23
    QualType EltTy = VecTy->getElementType();
3233
23
    if (passInt128VectorsInMem() &&
3234
23
        
(9
EltTy->isSpecificBuiltinType(BuiltinType::Int128)9
||
3235
9
         EltTy->isSpecificBuiltinType(BuiltinType::UInt128)))
3236
6
      return true;
3237
23
  }
3238
3239
2.90k
  return false;
3240
3.02k
}
3241
3242
ABIArgInfo X86_64ABIInfo::getIndirectResult(QualType Ty,
3243
3.88k
                                            unsigned freeIntRegs) const {
3244
  // If this is a scalar LLVM value then assume LLVM will pass it in the right
3245
  // place naturally.
3246
  //
3247
  // This assumption is optimistic, as there could be free registers available
3248
  // when we need to pass this argument in memory, and LLVM could try to pass
3249
  // the argument in the free register. This does not seem to happen currently,
3250
  // but this code would be much safer if we could mark the argument with
3251
  // 'onstack'. See PR12193.
3252
3.88k
  if (!isAggregateTypeForABI(Ty) && 
!IsIllegalVectorType(Ty)3.02k
&&
3253
3.88k
      
!Ty->isBitIntType()2.90k
) {
3254
    // Treat an enum type as its underlying type.
3255
2.90k
    if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3256
0
      Ty = EnumTy->getDecl()->getIntegerType();
3257
3258
2.90k
    return (isPromotableIntegerTypeForABI(Ty) ? 
ABIArgInfo::getExtend(Ty)290
3259
2.90k
                                              : 
ABIArgInfo::getDirect()2.61k
);
3260
2.90k
  }
3261
3262
980
  if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
3263
513
    return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
3264
3265
  // Compute the byval alignment. We specify the alignment of the byval in all
3266
  // cases so that the mid-level optimizer knows the alignment of the byval.
3267
467
  unsigned Align = std::max(getContext().getTypeAlign(Ty) / 8, 8U);
3268
3269
  // Attempt to avoid passing indirect results using byval when possible. This
3270
  // is important for good codegen.
3271
  //
3272
  // We do this by coercing the value into a scalar type which the backend can
3273
  // handle naturally (i.e., without using byval).
3274
  //
3275
  // For simplicity, we currently only do this when we have exhausted all of the
3276
  // free integer registers. Doing this when there are free integer registers
3277
  // would require more care, as we would have to ensure that the coerced value
3278
  // did not claim the unused register. That would require either reording the
3279
  // arguments to the function (so that any subsequent inreg values came first),
3280
  // or only doing this optimization when there were no following arguments that
3281
  // might be inreg.
3282
  //
3283
  // We currently expect it to be rare (particularly in well written code) for
3284
  // arguments to be passed on the stack when there are still free integer
3285
  // registers available (this would typically imply large structs being passed
3286
  // by value), so this seems like a fair tradeoff for now.
3287
  //
3288
  // We can revisit this if the backend grows support for 'onstack' parameter
3289
  // attributes. See PR12193.
3290
467
  if (freeIntRegs == 0) {
3291
39
    uint64_t Size = getContext().getTypeSize(Ty);
3292
3293
    // If this type fits in an eightbyte, coerce it into the matching integral
3294
    // type, which will end up on the stack (with alignment 8).
3295
39
    if (Align == 8 && 
Size <= 6429
)
3296
6
      return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
3297
6
                                                          Size));
3298
39
  }
3299
3300
461
  return ABIArgInfo::getIndirect(CharUnits::fromQuantity(Align));
3301
467
}
3302
3303
/// The ABI specifies that a value should be passed in a full vector XMM/YMM
3304
/// register. Pick an LLVM IR type that will be passed as a vector register.
3305
6.17k
llvm::Type *X86_64ABIInfo::GetByteVectorType(QualType Ty) const {
3306
  // Wrapper structs/arrays that only contain vectors are passed just like
3307
  // vectors; strip them off if present.
3308
6.17k
  if (const Type *InnerTy = isSingleElementStruct(Ty, getContext()))
3309
25
    Ty = QualType(InnerTy, 0);
3310
3311
6.17k
  llvm::Type *IRType = CGT.ConvertType(Ty);
3312
6.17k
  if (isa<llvm::VectorType>(IRType)) {
3313
    // Don't pass vXi128 vectors in their native type, the backend can't
3314
    // legalize them.
3315
6.13k
    if (passInt128VectorsInMem() &&
3316
6.13k
        
cast<llvm::VectorType>(IRType)->getElementType()->isIntegerTy(128)510
) {
3317
      // Use a vXi64 vector.
3318
6
      uint64_t Size = getContext().getTypeSize(Ty);
3319
6
      return llvm::FixedVectorType::get(llvm::Type::getInt64Ty(getVMContext()),
3320
6
                                        Size / 64);
3321
6
    }
3322
3323
6.13k
    return IRType;
3324
6.13k
  }
3325
3326
43
  if (IRType->getTypeID() == llvm::Type::FP128TyID)
3327
40
    return IRType;
3328
3329
  // We couldn't find the preferred IR vector type for 'Ty'.
3330
3
  uint64_t Size = getContext().getTypeSize(Ty);
3331
3
  assert((Size == 128 || Size == 256 || Size == 512) && "Invalid type found!");
3332
3333
3334
  // Return a LLVM IR vector type based on the size of 'Ty'.
3335
0
  return llvm::FixedVectorType::get(llvm::Type::getDoubleTy(getVMContext()),
3336
3
                                    Size / 64);
3337
43
}
3338
3339
/// BitsContainNoUserData - Return true if the specified [start,end) bit range
3340
/// is known to either be off the end of the specified type or being in
3341
/// alignment padding.  The user type specified is known to be at most 128 bits
3342
/// in size, and have passed through X86_64ABIInfo::classify with a successful
3343
/// classification that put one of the two halves in the INTEGER class.
3344
///
3345
/// It is conservatively correct to return false.
3346
static bool BitsContainNoUserData(QualType Ty, unsigned StartBit,
3347
85.0k
                                  unsigned EndBit, ASTContext &Context) {
3348
  // If the bytes being queried are off the end of the type, there is no user
3349
  // data hiding here.  This handles analysis of builtins, vectors and other
3350
  // types that don't contain interesting padding.
3351
85.0k
  unsigned TySize = (unsigned)Context.getTypeSize(Ty);
3352
85.0k
  if (TySize <= StartBit)
3353
83.7k
    return true;
3354
3355
1.29k
  if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty)) {
3356
20
    unsigned EltSize = (unsigned)Context.getTypeSize(AT->getElementType());
3357
20
    unsigned NumElts = (unsigned)AT->getSize().getZExtValue();
3358
3359
    // Check each element to see if the element overlaps with the queried range.
3360
72
    for (unsigned i = 0; i != NumElts; 
++i52
) {
3361
      // If the element is after the span we care about, then we're done..
3362
69
      unsigned EltOffset = i*EltSize;
3363
69
      if (EltOffset >= EndBit) 
break0
;
3364
3365
69
      unsigned EltStart = EltOffset < StartBit ? 
StartBit-EltOffset52
:
017
;
3366
69
      if (!BitsContainNoUserData(AT->getElementType(), EltStart,
3367
69
                                 EndBit-EltOffset, Context))
3368
17
        return false;
3369
69
    }
3370
    // If it overlaps no elements, then it is safe to process as padding.
3371
3
    return true;
3372
20
  }
3373
3374
1.27k
  if (const RecordType *RT = Ty->getAs<RecordType>()) {
3375
816
    const RecordDecl *RD = RT->getDecl();
3376
816
    const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD);
3377
3378
    // If this is a C++ record, check the bases first.
3379
816
    if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
3380
666
      for (const auto &I : CXXRD->bases()) {
3381
21
        assert(!I.isVirtual() && !I.getType()->isDependentType() &&
3382
21
               "Unexpected base class!");
3383
0
        const auto *Base =
3384
21
            cast<CXXRecordDecl>(I.getType()->castAs<RecordType>()->getDecl());
3385
3386
        // If the base is after the span we care about, ignore it.
3387
21
        unsigned BaseOffset = Context.toBits(Layout.getBaseClassOffset(Base));
3388
21
        if (BaseOffset >= EndBit) 
continue0
;
3389
3390
21
        unsigned BaseStart = BaseOffset < StartBit ? StartBit-BaseOffset :
00
;
3391
21
        if (!BitsContainNoUserData(I.getType(), BaseStart,
3392
21
                                   EndBit-BaseOffset, Context))
3393
20
          return false;
3394
21
      }
3395
666
    }
3396
3397
    // Verify that no field has data that overlaps the region of interest.  Yes
3398
    // this could be sped up a lot by being smarter about queried fields,
3399
    // however we're only looking at structs up to 16 bytes, so we don't care
3400
    // much.
3401
796
    unsigned idx = 0;
3402
796
    for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
3403
1.80k
         i != e; 
++i, ++idx1.01k
) {
3404
1.60k
      unsigned FieldOffset = (unsigned)Layout.getFieldOffset(idx);
3405
3406
      // If we found a field after the region we care about, then we're done.
3407
1.60k
      if (FieldOffset >= EndBit) 
break115
;
3408
3409
1.48k
      unsigned FieldStart = FieldOffset < StartBit ? 
StartBit-FieldOffset1.05k
:
0434
;
3410
1.48k
      if (!BitsContainNoUserData(i->getType(), FieldStart, EndBit-FieldOffset,
3411
1.48k
                                 Context))
3412
476
        return false;
3413
1.48k
    }
3414
3415
    // If nothing in this record overlapped the area of interest, then we're
3416
    // clean.
3417
320
    return true;
3418
796
  }
3419
3420
459
  return false;
3421
1.27k
}
3422
3423
/// getFPTypeAtOffset - Return a floating point type at the specified offset.
3424
static llvm::Type *getFPTypeAtOffset(llvm::Type *IRType, unsigned IROffset,
3425
12.3k
                                     const llvm::DataLayout &TD) {
3426
12.3k
  if (IROffset == 0 && 
IRType->isFloatingPointTy()11.6k
)
3427
4.73k
    return IRType;
3428
3429
  // If this is a struct, recurse into the field at the specified offset.
3430
7.63k
  if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) {
3431
1.33k
    if (!STy->getNumContainedTypes())
3432
4
      return nullptr;
3433
3434
1.32k
    const llvm::StructLayout *SL = TD.getStructLayout(STy);
3435
1.32k
    unsigned Elt = SL->getElementContainingOffset(IROffset);
3436
1.32k
    IROffset -= SL->getElementOffset(Elt);
3437
1.32k
    return getFPTypeAtOffset(STy->getElementType(Elt), IROffset, TD);
3438
1.33k
  }
3439
3440
  // If this is an array, recurse into the field at the specified offset.
3441
6.29k
  if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) {
3442
20
    llvm::Type *EltTy = ATy->getElementType();
3443
20
    unsigned EltSize = TD.getTypeAllocSize(EltTy);
3444
20
    IROffset -= IROffset / EltSize * EltSize;
3445
20
    return getFPTypeAtOffset(EltTy, IROffset, TD);
3446
20
  }
3447
3448
6.27k
  return nullptr;
3449
6.29k
}
3450
3451
/// GetSSETypeAtOffset - Return a type that will be passed by the backend in the
3452
/// low 8 bytes of an XMM register, corresponding to the SSE class.
3453
llvm::Type *X86_64ABIInfo::
3454
GetSSETypeAtOffset(llvm::Type *IRType, unsigned IROffset,
3455
10.6k
                   QualType SourceTy, unsigned SourceOffset) const {
3456
10.6k
  const llvm::DataLayout &TD = getDataLayout();
3457
10.6k
  unsigned SourceSize =
3458
10.6k
      (unsigned)getContext().getTypeSize(SourceTy) / 8 - SourceOffset;
3459
10.6k
  llvm::Type *T0 = getFPTypeAtOffset(IRType, IROffset, TD);
3460
10.6k
  if (!T0 || 
T0->isDoubleTy()4.38k
)
3461
8.21k
    return llvm::Type::getDoubleTy(getVMContext());
3462
3463
  // Get the adjacent FP type.
3464
2.42k
  llvm::Type *T1 = nullptr;
3465
2.42k
  unsigned T0Size = TD.getTypeAllocSize(T0);
3466
2.42k
  if (SourceSize > T0Size)
3467
368
      T1 = getFPTypeAtOffset(IRType, IROffset + T0Size, TD);
3468
2.42k
  if (T1 == nullptr) {
3469
    // Check if IRType is a half + float. float type will be in IROffset+4 due
3470
    // to its alignment.
3471
2.08k
    if (T0->isHalfTy() && 
SourceSize > 4132
)
3472
6
      T1 = getFPTypeAtOffset(IRType, IROffset + 4, TD);
3473
    // If we can't get a second FP type, return a simple half or float.
3474
    // avx512fp16-abi.c:pr51813_2 shows it works to return float for
3475
    // {float, i8} too.
3476
2.08k
    if (T1 == nullptr)
3477
2.08k
      return T0;
3478
2.08k
  }
3479
3480
340
  if (T0->isFloatTy() && 
T1->isFloatTy()313
)
3481
307
    return llvm::FixedVectorType::get(T0, 2);
3482
3483
33
  if (T0->isHalfTy() && 
T1->isHalfTy()27
) {
3484
23
    llvm::Type *T2 = nullptr;
3485
23
    if (SourceSize > 4)
3486
8
      T2 = getFPTypeAtOffset(IRType, IROffset + 4, TD);
3487
23
    if (T2 == nullptr)
3488
15
      return llvm::FixedVectorType::get(T0, 2);
3489
8
    return llvm::FixedVectorType::get(T0, 4);
3490
23
  }
3491
3492
10
  if (T0->isHalfTy() || 
T1->isHalfTy()6
)
3493
10
    return llvm::FixedVectorType::get(llvm::Type::getHalfTy(getVMContext()), 4);
3494
3495
0
  return llvm::Type::getDoubleTy(getVMContext());
3496
10
}
3497
3498
3499
/// GetINTEGERTypeAtOffset - The ABI specifies that a value should be passed in
3500
/// an 8-byte GPR.  This means that we either have a scalar or we are talking
3501
/// about the high or low part of an up-to-16-byte struct.  This routine picks
3502
/// the best LLVM IR type to represent this, which may be i64 or may be anything
3503
/// else that the backend will pass in a GPR that works better (e.g. i8, %foo*,
3504
/// etc).
3505
///
3506
/// PrefType is an LLVM IR type that corresponds to (part of) the IR type for
3507
/// the source type.  IROffset is an offset in bytes into the LLVM IR type that
3508
/// the 8-byte value references.  PrefType may be null.
3509
///
3510
/// SourceTy is the source-level type for the entire argument.  SourceOffset is
3511
/// an offset into this that we're processing (which is always either 0 or 8).
3512
///
3513
llvm::Type *X86_64ABIInfo::
3514
GetINTEGERTypeAtOffset(llvm::Type *IRType, unsigned IROffset,
3515
384k
                       QualType SourceTy, unsigned SourceOffset) const {
3516
  // If we're dealing with an un-offset LLVM IR type, then it means that we're
3517
  // returning an 8-byte unit starting with it.  See if we can safely use it.
3518
384k
  if (IROffset == 0) {
3519
    // Pointers and int64's always fill the 8-byte unit.
3520
382k
    if ((isa<llvm::PointerType>(IRType) && 
Has64BitPointers264k
) ||
3521
382k
        
IRType->isIntegerTy(64)117k
)
3522
288k
      return IRType;
3523
3524
    // If we have a 1/2/4-byte integer, we can use it only if the rest of the
3525
    // goodness in the source type is just tail padding.  This is allowed to
3526
    // kick in for struct {double,int} on the int, but not on
3527
    // struct{double,int,int} because we wouldn't return the second int.  We
3528
    // have to do this analysis on the source type because we can't depend on
3529
    // unions being lowered a specific way etc.
3530
93.5k
    if (IRType->isIntegerTy(8) || 
IRType->isIntegerTy(16)89.8k
||
3531
93.5k
        
IRType->isIntegerTy(32)89.0k
||
3532
93.5k
        
(10.1k
isa<llvm::PointerType>(IRType)10.1k
&&
!Has64BitPointers92
)) {
3533
83.4k
      unsigned BitWidth = isa<llvm::PointerType>(IRType) ? 
3292
:
3534
83.4k
          
cast<llvm::IntegerType>(IRType)->getBitWidth()83.3k
;
3535
3536
83.4k
      if (BitsContainNoUserData(SourceTy, SourceOffset*8+BitWidth,
3537
83.4k
                                SourceOffset*8+64, getContext()))
3538
83.0k
        return IRType;
3539
83.4k
    }
3540
93.5k
  }
3541
3542
12.3k
  if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) {
3543
    // If this is a struct, recurse into the field at the specified offset.
3544
7.91k
    const llvm::StructLayout *SL = getDataLayout().getStructLayout(STy);
3545
7.91k
    if (IROffset < SL->getSizeInBytes()) {
3546
7.91k
      unsigned FieldIdx = SL->getElementContainingOffset(IROffset);
3547
7.91k
      IROffset -= SL->getElementOffset(FieldIdx);
3548
3549
7.91k
      return GetINTEGERTypeAtOffset(STy->getElementType(FieldIdx), IROffset,
3550
7.91k
                                    SourceTy, SourceOffset);
3551
7.91k
    }
3552
7.91k
  }
3553
3554
4.40k
  if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) {
3555
50
    llvm::Type *EltTy = ATy->getElementType();
3556
50
    unsigned EltSize = getDataLayout().getTypeAllocSize(EltTy);
3557
50
    unsigned EltOffset = IROffset/EltSize*EltSize;
3558
50
    return GetINTEGERTypeAtOffset(EltTy, IROffset-EltOffset, SourceTy,
3559
50
                                  SourceOffset);
3560
50
  }
3561
3562
  // Okay, we don't have any better idea of what to pass, so we pass this in an
3563
  // integer register that isn't too big to fit the rest of the struct.
3564
4.35k
  unsigned TySizeInBytes =
3565
4.35k
    (unsigned)getContext().getTypeSizeInChars(SourceTy).getQuantity();
3566
3567
4.35k
  assert(TySizeInBytes != SourceOffset && "Empty field?");
3568
3569
  // It is always safe to classify this as an integer type up to i64 that
3570
  // isn't larger than the structure.
3571
0
  return llvm::IntegerType::get(getVMContext(),
3572
4.35k
                                std::min(TySizeInBytes-SourceOffset, 8U)*8);
3573
4.40k
}
3574
3575
3576
/// GetX86_64ByValArgumentPair - Given a high and low type that can ideally
3577
/// be used as elements of a two register pair to pass or return, return a
3578
/// first class aggregate to represent them.  For example, if the low part of
3579
/// a by-value argument should be passed as i32* and the high part as float,
3580
/// return {i32*, float}.
3581
static llvm::Type *
3582
GetX86_64ByValArgumentPair(llvm::Type *Lo, llvm::Type *Hi,
3583
2.02k
                           const llvm::DataLayout &TD) {
3584
  // In order to correctly satisfy the ABI, we need to the high part to start
3585
  // at offset 8.  If the high and low parts we inferred are both 4-byte types
3586
  // (e.g. i32 and i32) then the resultant struct type ({i32,i32}) won't have
3587
  // the second element at offset 8.  Check for this:
3588
2.02k
  unsigned LoSize = (unsigned)TD.getTypeAllocSize(Lo);
3589
2.02k
  unsigned HiAlign = TD.getABITypeAlignment(Hi);
3590
2.02k
  unsigned HiStart = llvm::alignTo(LoSize, HiAlign);
3591
2.02k
  assert(HiStart != 0 && HiStart <= 8 && "Invalid x86-64 argument pair!");
3592
3593
  // To handle this, we have to increase the size of the low part so that the
3594
  // second element will start at an 8 byte offset.  We can't increase the size
3595
  // of the second element because it might make us access off the end of the
3596
  // struct.
3597
2.02k
  if (HiStart != 8) {
3598
    // There are usually two sorts of types the ABI generation code can produce
3599
    // for the low part of a pair that aren't 8 bytes in size: half, float or
3600
    // i8/i16/i32.  This can also include pointers when they are 32-bit (X32 and
3601
    // NaCl).
3602
    // Promote these to a larger type.
3603
6
    if (Lo->isHalfTy() || Lo->isFloatTy())
3604
1
      Lo = llvm::Type::getDoubleTy(Lo->getContext());
3605
5
    else {
3606
5
      assert((Lo->isIntegerTy() || Lo->isPointerTy())
3607
5
             && "Invalid/unknown lo type");
3608
0
      Lo = llvm::Type::getInt64Ty(Lo->getContext());
3609
5
    }
3610
6
  }
3611
3612
0
  llvm::StructType *Result = llvm::StructType::get(Lo, Hi);
3613
3614
  // Verify that the second element is at an 8-byte offset.
3615
2.02k
  assert(TD.getStructLayout(Result)->getElementOffset(1) == 8 &&
3616
2.02k
         "Invalid x86-64 argument pair!");
3617
0
  return Result;
3618
2.02k
}
3619
3620
ABIArgInfo X86_64ABIInfo::
3621
163k
classifyReturnType(QualType RetTy) const {
3622
  // AMD64-ABI 3.2.3p4: Rule 1. Classify the return type with the
3623
  // classification algorithm.
3624
163k
  X86_64ABIInfo::Class Lo, Hi;
3625
163k
  classify(RetTy, 0, Lo, Hi, /*isNamedArg*/ true);
3626
3627
  // Check some invariants.
3628
163k
  assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.");
3629
0
  assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
3630
3631
0
  llvm::Type *ResType = nullptr;
3632
163k
  switch (Lo) {
3633
65.4k
  case NoClass:
3634
65.4k
    if (Hi == NoClass)
3635
65.4k
      return ABIArgInfo::getIgnore();
3636
    // If the low part is just padding, it takes no register, leave ResType
3637
    // null.
3638
1
    assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
3639
1
           "Unknown missing lo part");
3640
0
    break;
3641
3642
0
  case SSEUp:
3643
0
  case X87Up:
3644
0
    llvm_unreachable("Invalid classification for lo word.");
3645
3646
    // AMD64-ABI 3.2.3p4: Rule 2. Types of class memory are returned via
3647
    // hidden argument.
3648
372
  case Memory:
3649
372
    return getIndirectReturnResult(RetTy);
3650
3651
    // AMD64-ABI 3.2.3p4: Rule 3. If the class is INTEGER, the next
3652
    // available register of the sequence %rax, %rdx is used.
3653
93.6k
  case Integer:
3654
93.6k
    ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0);
3655
3656
    // If we have a sign or zero extended integer, make sure to return Extend
3657
    // so that the parameter gets the right LLVM IR attributes.
3658
93.6k
    if (Hi == NoClass && 
isa<llvm::IntegerType>(ResType)92.6k
) {
3659
      // Treat an enum type as its underlying type.
3660
52.5k
      if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
3661
101
        RetTy = EnumTy->getDecl()->getIntegerType();
3662
3663
52.5k
      if (RetTy->isIntegralOrEnumerationType() &&
3664
52.5k
          
isPromotableIntegerTypeForABI(RetTy)51.6k
)
3665
4.49k
        return ABIArgInfo::getExtend(RetTy);
3666
52.5k
    }
3667
89.1k
    break;
3668
3669
    // AMD64-ABI 3.2.3p4: Rule 4. If the class is SSE, the next
3670
    // available SSE register of the sequence %xmm0, %xmm1 is used.
3671
89.1k
  case SSE:
3672
3.49k
    ResType = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0);
3673
3.49k
    break;
3674
3675
    // AMD64-ABI 3.2.3p4: Rule 6. If the class is X87, the value is
3676
    // returned on the X87 stack in %st0 as 80-bit x87 number.
3677
675
  case X87:
3678
675
    ResType = llvm::Type::getX86_FP80Ty(getVMContext());
3679
675
    break;
3680
3681
    // AMD64-ABI 3.2.3p4: Rule 8. If the class is COMPLEX_X87, the real
3682
    // part of the value is returned in %st0 and the imaginary part in
3683
    // %st1.
3684
38
  case ComplexX87:
3685
38
    assert(Hi == ComplexX87 && "Unexpected ComplexX87 classification.");
3686
0
    ResType = llvm::StructType::get(llvm::Type::getX86_FP80Ty(getVMContext()),
3687
38
                                    llvm::Type::getX86_FP80Ty(getVMContext()));
3688
38
    break;
3689
163k
  }
3690
3691
93.3k
  llvm::Type *HighPart = nullptr;
3692
93.3k
  switch (Hi) {
3693
    // Memory was handled previously and X87 should
3694
    // never occur as a hi class.
3695
0
  case Memory:
3696
0
  case X87:
3697
0
    llvm_unreachable("Invalid classification for hi word.");
3698
3699
38
  case ComplexX87: // Previously handled.
3700
89.2k
  case NoClass:
3701
89.2k
    break;
3702
3703
980
  case Integer:
3704
980
    HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3705
980
    if (Lo == NoClass)  // Return HighPart at offset 8 in memory.
3706
0
      return ABIArgInfo::getDirect(HighPart, 8);
3707
980
    break;
3708
980
  case SSE:
3709
147
    HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3710
147
    if (Lo == NoClass)  // Return HighPart at offset 8 in memory.
3711
1
      return ABIArgInfo::getDirect(HighPart, 8);
3712
146
    break;
3713
3714
    // AMD64-ABI 3.2.3p4: Rule 5. If the class is SSEUP, the eightbyte
3715
    // is passed in the next available eightbyte chunk if the last used
3716
    // vector register.
3717
    //
3718
    // SSEUP should always be preceded by SSE, just widen.
3719
2.30k
  case SSEUp:
3720
2.30k
    assert(Lo == SSE && "Unexpected SSEUp classification.");
3721
0
    ResType = GetByteVectorType(RetTy);
3722
2.30k
    break;
3723
3724
    // AMD64-ABI 3.2.3p4: Rule 7. If the class is X87UP, the value is
3725
    // returned together with the previous X87 value in %st0.
3726
675
  case X87Up:
3727
    // If X87Up is preceded by X87, we don't need to do
3728
    // anything. However, in some cases with unions it may not be
3729
    // preceded by X87. In such situations we follow gcc and pass the
3730
    // extra bits in an SSE reg.
3731
675
    if (Lo != X87) {
3732
0
      HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3733
0
      if (Lo == NoClass)  // Return HighPart at offset 8 in memory.
3734
0
        return ABIArgInfo::getDirect(HighPart, 8);
3735
0
    }
3736
675
    break;
3737
93.3k
  }
3738
3739
  // If a high part was specified, merge it together with the low part.  It is
3740
  // known to pass in the high eightbyte of the result.  We do this by forming a
3741
  // first class struct aggregate with the high and low part: {low, high}
3742
93.3k
  if (HighPart)
3743
1.12k
    ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout());
3744
3745
93.3k
  return ABIArgInfo::getDirect(ResType);
3746
93.3k
}
3747
3748
ABIArgInfo
3749
X86_64ABIInfo::classifyArgumentType(QualType Ty, unsigned freeIntRegs,
3750
                                    unsigned &neededInt, unsigned &neededSSE,
3751
294k
                                    bool isNamedArg, bool IsRegCall) const {
3752
294k
  Ty = useFirstFieldIfTransparentUnion(Ty);
3753
3754
294k
  X86_64ABIInfo::Class Lo, Hi;
3755
294k
  classify(Ty, 0, Lo, Hi, isNamedArg, IsRegCall);
3756
3757
  // Check some invariants.
3758
  // FIXME: Enforce these by construction.
3759
294k
  assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.");
3760
0
  assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
3761
3762
0
  neededInt = 0;
3763
294k
  neededSSE = 0;
3764
294k
  llvm::Type *ResType = nullptr;
3765
294k
  switch (Lo) {
3766
5.01k
  case NoClass:
3767
5.01k
    if (Hi == NoClass)
3768
5.01k
      return ABIArgInfo::getIgnore();
3769
    // If the low part is just padding, it takes no register, leave ResType
3770
    // null.
3771
2
    assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
3772
2
           "Unknown missing lo part");
3773
0
    break;
3774
3775
    // AMD64-ABI 3.2.3p3: Rule 1. If the class is MEMORY, pass the argument
3776
    // on the stack.
3777
1.33k
  case Memory:
3778
3779
    // AMD64-ABI 3.2.3p3: Rule 5. If the class is X87, X87UP or
3780
    // COMPLEX_X87, it is passed in memory.
3781
1.57k
  case X87:
3782
1.63k
  case ComplexX87:
3783
1.63k
    if (getRecordArgABI(Ty, getCXXABI()) == CGCXXABI::RAA_Indirect)
3784
513
      ++neededInt;
3785
1.63k
    return getIndirectResult(Ty, freeIntRegs);
3786
3787
0
  case SSEUp:
3788
0
  case X87Up:
3789
0
    llvm_unreachable("Invalid classification for lo word.");
3790
3791
    // AMD64-ABI 3.2.3p3: Rule 2. If the class is INTEGER, the next
3792
    // available register of the sequence %rdi, %rsi, %rdx, %rcx, %r8
3793
    // and %r9 is used.
3794
280k
  case Integer:
3795
280k
    ++neededInt;
3796
3797
    // Pick an 8-byte type based on the preferred type.
3798
280k
    ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 0, Ty, 0);
3799
3800
    // If we have a sign or zero extended integer, make sure to return Extend
3801
    // so that the parameter gets the right LLVM IR attributes.
3802
280k
    if (Hi == NoClass && 
isa<llvm::IntegerType>(ResType)279k
) {
3803
      // Treat an enum type as its underlying type.
3804
56.8k
      if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3805
858
        Ty = EnumTy->getDecl()->getIntegerType();
3806
3807
56.8k
      if (Ty->isIntegralOrEnumerationType() &&
3808
56.8k
          
isPromotableIntegerTypeForABI(Ty)56.4k
)
3809
3.26k
        return ABIArgInfo::getExtend(Ty);
3810
56.8k
    }
3811
3812
277k
    break;
3813
3814
    // AMD64-ABI 3.2.3p3: Rule 3. If the class is SSE, the next
3815
    // available SSE register is used, the registers are taken in the
3816
    // order from %xmm0 to %xmm7.
3817
277k
  case SSE: {
3818
6.83k
    llvm::Type *IRType = CGT.ConvertType(Ty);
3819
6.83k
    ResType = GetSSETypeAtOffset(IRType, 0, Ty, 0);
3820
6.83k
    ++neededSSE;
3821
6.83k
    break;
3822
280k
  }
3823
294k
  }
3824
3825
284k
  llvm::Type *HighPart = nullptr;
3826
284k
  switch (Hi) {
3827
    // Memory was handled previously, ComplexX87 and X87 should
3828
    // never occur as hi classes, and X87Up must be preceded by X87,
3829
    // which is passed in memory.
3830
0
  case Memory:
3831
0
  case X87:
3832
0
  case ComplexX87:
3833
0
    llvm_unreachable("Invalid classification for hi word.");
3834
3835
279k
  case NoClass: break;
3836
3837
738
  case Integer:
3838
738
    ++neededInt;
3839
    // Pick an 8-byte type based on the preferred type.
3840
738
    HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8);
3841
3842
738
    if (Lo == NoClass)  // Pass HighPart at offset 8 in memory.
3843
2
      return ABIArgInfo::getDirect(HighPart, 8);
3844
736
    break;
3845
3846
    // X87Up generally doesn't occur here (long double is passed in
3847
    // memory), except in situations involving unions.
3848
736
  case X87Up:
3849
158
  case SSE:
3850
158
    HighPart = GetSSETypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8);
3851
3852
158
    if (Lo == NoClass)  // Pass HighPart at offset 8 in memory.
3853
0
      return ABIArgInfo::getDirect(HighPart, 8);
3854
3855
158
    ++neededSSE;
3856
158
    break;
3857
3858
    // AMD64-ABI 3.2.3p3: Rule 4. If the class is SSEUP, the
3859
    // eightbyte is passed in the upper half of the last used SSE
3860
    // register.  This only happens when 128-bit vectors are passed.
3861
3.87k
  case SSEUp:
3862
3.87k
    assert(Lo == SSE && "Unexpected SSEUp classification");
3863
0
    ResType = GetByteVectorType(Ty);
3864
3.87k
    break;
3865
284k
  }
3866
3867
  // If a high part was specified, merge it together with the low part.  It is
3868
  // known to pass in the high eightbyte of the result.  We do this by forming a
3869
  // first class struct aggregate with the high and low part: {low, high}
3870
284k
  if (HighPart)
3871
894
    ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout());
3872
3873
284k
  return ABIArgInfo::getDirect(ResType);
3874
284k
}
3875
3876
ABIArgInfo
3877
X86_64ABIInfo::classifyRegCallStructTypeImpl(QualType Ty, unsigned &NeededInt,
3878
                                             unsigned &NeededSSE,
3879
20
                                             unsigned &MaxVectorWidth) const {
3880
20
  auto RT = Ty->getAs<RecordType>();
3881
20
  assert(RT && "classifyRegCallStructType only valid with struct types");
3882
3883
20
  if (RT->getDecl()->hasFlexibleArrayMember())
3884
0
    return getIndirectReturnResult(Ty);
3885
3886
  // Sum up bases
3887
20
  if (auto CXXRD = dyn_cast<CXXRecordDecl>(RT->getDecl())) {
3888
0
    if (CXXRD->isDynamicClass()) {
3889
0
      NeededInt = NeededSSE = 0;
3890
0
      return getIndirectReturnResult(Ty);
3891
0
    }
3892
3893
0
    for (const auto &I : CXXRD->bases())
3894
0
      if (classifyRegCallStructTypeImpl(I.getType(), NeededInt, NeededSSE,
3895
0
                                        MaxVectorWidth)
3896
0
              .isIndirect()) {
3897
0
        NeededInt = NeededSSE = 0;
3898
0
        return getIndirectReturnResult(Ty);
3899
0
      }
3900
0
  }
3901
3902
  // Sum up members
3903
48
  
for (const auto *FD : RT->getDecl()->fields())20
{
3904
48
    QualType MTy = FD->getType();
3905
48
    if (MTy->isRecordType() && 
!MTy->isUnionType()0
) {
3906
0
      if (classifyRegCallStructTypeImpl(MTy, NeededInt, NeededSSE,
3907
0
                                        MaxVectorWidth)
3908
0
              .isIndirect()) {
3909
0
        NeededInt = NeededSSE = 0;
3910
0
        return getIndirectReturnResult(Ty);
3911
0
      }
3912
48
    } else {
3913
48
      unsigned LocalNeededInt, LocalNeededSSE;
3914
48
      if (classifyArgumentType(MTy, UINT_MAX, LocalNeededInt, LocalNeededSSE,
3915
48
                               true, true)
3916
48
              .isIndirect()) {
3917
0
        NeededInt = NeededSSE = 0;
3918
0
        return getIndirectReturnResult(Ty);
3919
0
      }
3920
48
      if (const auto *AT = getContext().getAsConstantArrayType(MTy))
3921
10
        MTy = AT->getElementType();
3922
48
      if (const auto *VT = MTy->getAs<VectorType>())
3923
25
        if (getContext().getTypeSize(VT) > MaxVectorWidth)
3924
12
          MaxVectorWidth = getContext().getTypeSize(VT);
3925
48
      NeededInt += LocalNeededInt;
3926
48
      NeededSSE += LocalNeededSSE;
3927
48
    }
3928
48
  }
3929
3930
20
  return ABIArgInfo::getDirect();
3931
20
}
3932
3933
ABIArgInfo
3934
X86_64ABIInfo::classifyRegCallStructType(QualType Ty, unsigned &NeededInt,
3935
                                         unsigned &NeededSSE,
3936
20
                                         unsigned &MaxVectorWidth) const {
3937
3938
20
  NeededInt = 0;
3939
20
  NeededSSE = 0;
3940
20
  MaxVectorWidth = 0;
3941
3942
20
  return classifyRegCallStructTypeImpl(Ty, NeededInt, NeededSSE,
3943
20
                                       MaxVectorWidth);
3944
20
}
3945
3946
164k
void X86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
3947
3948
164k
  const unsigned CallingConv = FI.getCallingConvention();
3949
  // It is possible to force Win64 calling convention on any x86_64 target by
3950
  // using __attribute__((ms_abi)). In such case to correctly emit Win64
3951
  // compatible code delegate this call to WinX86_64ABIInfo::computeInfo.
3952
164k
  if (CallingConv == llvm::CallingConv::Win64) {
3953
13
    WinX86_64ABIInfo Win64ABIInfo(CGT, AVXLevel);
3954
13
    Win64ABIInfo.computeInfo(FI);
3955
13
    return;
3956
13
  }
3957
3958
164k
  bool IsRegCall = CallingConv == llvm::CallingConv::X86_RegCall;
3959
3960
  // Keep track of the number of assigned registers.
3961
164k
  unsigned FreeIntRegs = IsRegCall ? 
1128
:
6164k
;
3962
164k
  unsigned FreeSSERegs = IsRegCall ? 
1628
:
8164k
;
3963
164k
  unsigned NeededInt = 0, NeededSSE = 0, MaxVectorWidth = 0;
3964
3965
164k
  if (!::classifyReturnType(getCXXABI(), FI, *this)) {
3966
163k
    if (IsRegCall && 
FI.getReturnType()->getTypePtr()->isRecordType()27
&&
3967
163k
        
!FI.getReturnType()->getTypePtr()->isUnionType()3
) {
3968
3
      FI.getReturnInfo() = classifyRegCallStructType(
3969
3
          FI.getReturnType(), NeededInt, NeededSSE, MaxVectorWidth);
3970
3
      if (FreeIntRegs >= NeededInt && FreeSSERegs >= NeededSSE) {
3971
3
        FreeIntRegs -= NeededInt;
3972
3
        FreeSSERegs -= NeededSSE;
3973
3
      } else {
3974
0
        FI.getReturnInfo() = getIndirectReturnResult(FI.getReturnType());
3975
0
      }
3976
163k
    } else if (IsRegCall && 
FI.getReturnType()->getAs<ComplexType>()24
&&
3977
163k
               getContext().getCanonicalType(FI.getReturnType()
3978
2
                                                 ->getAs<ComplexType>()
3979
2
                                                 ->getElementType()) ==
3980
2
                   getContext().LongDoubleTy)
3981
      // Complex Long Double Type is passed in Memory when Regcall
3982
      // calling convention is used.
3983
1
      FI.getReturnInfo() = getIndirectReturnResult(FI.getReturnType());
3984
163k
    else
3985
163k
      FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
3986
163k
  }
3987
3988
  // If the return value is indirect, then the hidden argument is consuming one
3989
  // integer register.
3990
164k
  if (FI.getReturnInfo().isIndirect())
3991
1.07k
    --FreeIntRegs;
3992
163k
  else if (NeededSSE && 
MaxVectorWidth > 01
)
3993
0
    FI.setMaxVectorWidth(MaxVectorWidth);
3994
3995
  // The chain argument effectively gives us another free register.
3996
164k
  if (FI.isChainCall())
3997
4
    ++FreeIntRegs;
3998
3999
164k
  unsigned NumRequiredArgs = FI.getNumRequiredArgs();
4000
  // AMD64-ABI 3.2.3p3: Once arguments are classified, the registers
4001
  // get assigned (in left-to-right order) for passing as follows...
4002
164k
  unsigned ArgNo = 0;
4003
164k
  for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end();
4004
458k
       it != ie; 
++it, ++ArgNo293k
) {
4005
293k
    bool IsNamedArg = ArgNo < NumRequiredArgs;
4006
4007
293k
    if (IsRegCall && 
it->type->isStructureOrClassType()64
)
4008
17
      it->info = classifyRegCallStructType(it->type, NeededInt, NeededSSE,
4009
17
                                           MaxVectorWidth);
4010
293k
    else
4011
293k
      it->info = classifyArgumentType(it->type, FreeIntRegs, NeededInt,
4012
293k
                                      NeededSSE, IsNamedArg);
4013
4014
    // AMD64-ABI 3.2.3p3: If there are no registers available for any
4015
    // eightbyte of an argument, the whole argument is passed on the
4016
    // stack. If registers have already been assigned for some
4017
    // eightbytes of such an argument, the assignments get reverted.
4018
293k
    if (FreeIntRegs >= NeededInt && 
FreeSSERegs >= NeededSSE291k
) {
4019
291k
      FreeIntRegs -= NeededInt;
4020
291k
      FreeSSERegs -= NeededSSE;
4021
291k
      if (MaxVectorWidth > FI.getMaxVectorWidth())
4022
7
        FI.setMaxVectorWidth(MaxVectorWidth);
4023
291k
    } else {
4024
2.24k
      it->info = getIndirectResult(it->type, FreeIntRegs);
4025
2.24k
    }
4026
293k
  }
4027
164k
}
4028
4029
static Address EmitX86_64VAArgFromMemory(CodeGenFunction &CGF,
4030
94
                                         Address VAListAddr, QualType Ty) {
4031
94
  Address overflow_arg_area_p =
4032
94
      CGF.Builder.CreateStructGEP(VAListAddr, 2, "overflow_arg_area_p");
4033
94
  llvm::Value *overflow_arg_area =
4034
94
    CGF.Builder.CreateLoad(overflow_arg_area_p, "overflow_arg_area");
4035
4036
  // AMD64-ABI 3.5.7p5: Step 7. Align l->overflow_arg_area upwards to a 16
4037
  // byte boundary if alignment needed by type exceeds 8 byte boundary.
4038
  // It isn't stated explicitly in the standard, but in practice we use
4039
  // alignment greater than 16 where necessary.
4040
94
  CharUnits Align = CGF.getContext().getTypeAlignInChars(Ty);
4041
94
  if (Align > CharUnits::fromQuantity(8)) {
4042
18
    overflow_arg_area = emitRoundPointerUpToAlignment(CGF, overflow_arg_area,
4043
18
                                                      Align);
4044
18
  }
4045
4046
  // AMD64-ABI 3.5.7p5: Step 8. Fetch type from l->overflow_arg_area.
4047
94
  llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
4048
94
  llvm::Value *Res =
4049
94
    CGF.Builder.CreateBitCast(overflow_arg_area,
4050
94
                              llvm::PointerType::getUnqual(LTy));
4051
4052
  // AMD64-ABI 3.5.7p5: Step 9. Set l->overflow_arg_area to:
4053
  // l->overflow_arg_area + sizeof(type).
4054
  // AMD64-ABI 3.5.7p5: Step 10. Align l->overflow_arg_area upwards to
4055
  // an 8 byte boundary.
4056
4057
94
  uint64_t SizeInBytes = (CGF.getContext().getTypeSize(Ty) + 7) / 8;
4058
94
  llvm::Value *Offset =
4059
94
      llvm::ConstantInt::get(CGF.Int32Ty, (SizeInBytes + 7)  & ~7);
4060
94
  overflow_arg_area = CGF.Builder.CreateGEP(CGF.Int8Ty, overflow_arg_area,
4061
94
                                            Offset, "overflow_arg_area.next");
4062
94
  CGF.Builder.CreateStore(overflow_arg_area, overflow_arg_area_p);
4063
4064
  // AMD64-ABI 3.5.7p5: Step 11. Return the fetched type.
4065
94
  return Address(Res, LTy, Align);
4066
94
}
4067
4068
Address X86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4069
94
                                 QualType Ty) const {
4070
  // Assume that va_list type is correct; should be pointer to LLVM type:
4071
  // struct {
4072
  //   i32 gp_offset;
4073
  //   i32 fp_offset;
4074
  //   i8* overflow_arg_area;
4075
  //   i8* reg_save_area;
4076
  // };
4077
94
  unsigned neededInt, neededSSE;
4078
4079
94
  Ty = getContext().getCanonicalType(Ty);
4080
94
  ABIArgInfo AI = classifyArgumentType(Ty, 0, neededInt, neededSSE,
4081
94
                                       /*isNamedArg*/false);
4082
4083
  // AMD64-ABI 3.5.7p5: Step 1. Determine whether type may be passed
4084
  // in the registers. If not go to step 7.
4085
94
  if (!neededInt && 
!neededSSE31
)
4086
14
    return EmitX86_64VAArgFromMemory(CGF, VAListAddr, Ty);
4087
4088
  // AMD64-ABI 3.5.7p5: Step 2. Compute num_gp to hold the number of
4089
  // general purpose registers needed to pass type and num_fp to hold
4090
  // the number of floating point registers needed.
4091
4092
  // AMD64-ABI 3.5.7p5: Step 3. Verify whether arguments fit into
4093
  // registers. In the case: l->gp_offset > 48 - num_gp * 8 or
4094
  // l->fp_offset > 304 - num_fp * 16 go to step 7.
4095
  //
4096
  // NOTE: 304 is a typo, there are (6 * 8 + 8 * 16) = 176 bytes of
4097
  // register save space).
4098
4099
80
  llvm::Value *InRegs = nullptr;
4100
80
  Address gp_offset_p = Address::invalid(), fp_offset_p = Address::invalid();
4101
80
  llvm::Value *gp_offset = nullptr, *fp_offset = nullptr;
4102
80
  if (neededInt) {
4103
63
    gp_offset_p = CGF.Builder.CreateStructGEP(VAListAddr, 0, "gp_offset_p");
4104
63
    gp_offset = CGF.Builder.CreateLoad(gp_offset_p, "gp_offset");
4105
63
    InRegs = llvm::ConstantInt::get(CGF.Int32Ty, 48 - neededInt * 8);
4106
63
    InRegs = CGF.Builder.CreateICmpULE(gp_offset, InRegs, "fits_in_gp");
4107
63
  }
4108
4109
80
  if (neededSSE) {
4110
21
    fp_offset_p = CGF.Builder.CreateStructGEP(VAListAddr, 1, "fp_offset_p");
4111
21
    fp_offset = CGF.Builder.CreateLoad(fp_offset_p, "fp_offset");
4112
21
    llvm::Value *FitsInFP =
4113
21
      llvm::ConstantInt::get(CGF.Int32Ty, 176 - neededSSE * 16);
4114
21
    FitsInFP = CGF.Builder.CreateICmpULE(fp_offset, FitsInFP, "fits_in_fp");
4115
21
    InRegs = InRegs ? 
CGF.Builder.CreateAnd(InRegs, FitsInFP)4
:
FitsInFP17
;
4116
21
  }
4117
4118
80
  llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
4119
80
  llvm::BasicBlock *InMemBlock = CGF.createBasicBlock("vaarg.in_mem");
4120
80
  llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
4121
80
  CGF.Builder.CreateCondBr(InRegs, InRegBlock, InMemBlock);
4122
4123
  // Emit code to load the value if it was passed in registers.
4124
4125
80
  CGF.EmitBlock(InRegBlock);
4126
4127
  // AMD64-ABI 3.5.7p5: Step 4. Fetch type from l->reg_save_area with
4128
  // an offset of l->gp_offset and/or l->fp_offset. This may require
4129
  // copying to a temporary location in case the parameter is passed
4130
  // in different register classes or requires an alignment greater
4131
  // than 8 for general purpose registers and 16 for XMM registers.
4132
  //
4133
  // FIXME: This really results in shameful code when we end up needing to
4134
  // collect arguments from different places; often what should result in a
4135
  // simple assembling of a structure from scattered addresses has many more
4136
  // loads than necessary. Can we clean this up?
4137
80
  llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
4138
80
  llvm::Value *RegSaveArea = CGF.Builder.CreateLoad(
4139
80
      CGF.Builder.CreateStructGEP(VAListAddr, 3), "reg_save_area");
4140
4141
80
  Address RegAddr = Address::invalid();
4142
80
  if (neededInt && 
neededSSE63
) {
4143
    // FIXME: Cleanup.
4144
4
    assert(AI.isDirect() && "Unexpected ABI info for mixed regs");
4145
0
    llvm::StructType *ST = cast<llvm::StructType>(AI.getCoerceToType());
4146
4
    Address Tmp = CGF.CreateMemTemp(Ty);
4147
4
    Tmp = CGF.Builder.CreateElementBitCast(Tmp, ST);
4148
4
    assert(ST->getNumElements() == 2 && "Unexpected ABI info for mixed regs");
4149
0
    llvm::Type *TyLo = ST->getElementType(0);
4150
4
    llvm::Type *TyHi = ST->getElementType(1);
4151
4
    assert((TyLo->isFPOrFPVectorTy() ^ TyHi->isFPOrFPVectorTy()) &&
4152
4
           "Unexpected ABI info for mixed regs");
4153
0
    llvm::Type *PTyLo = llvm::PointerType::getUnqual(TyLo);
4154
4
    llvm::Type *PTyHi = llvm::PointerType::getUnqual(TyHi);
4155
4
    llvm::Value *GPAddr =
4156
4
        CGF.Builder.CreateGEP(CGF.Int8Ty, RegSaveArea, gp_offset);
4157
4
    llvm::Value *FPAddr =
4158
4
        CGF.Builder.CreateGEP(CGF.Int8Ty, RegSaveArea, fp_offset);
4159
4
    llvm::Value *RegLoAddr = TyLo->isFPOrFPVectorTy() ? 
FPAddr1
:
GPAddr3
;
4160
4
    llvm::Value *RegHiAddr = TyLo->isFPOrFPVectorTy() ? 
GPAddr1
:
FPAddr3
;
4161
4162
    // Copy the first element.
4163
    // FIXME: Our choice of alignment here and below is probably pessimistic.
4164
4
    llvm::Value *V = CGF.Builder.CreateAlignedLoad(
4165
4
        TyLo, CGF.Builder.CreateBitCast(RegLoAddr, PTyLo),
4166
4
        CharUnits::fromQuantity(getDataLayout().getABITypeAlignment(TyLo)));
4167
4
    CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 0));
4168
4169
    // Copy the second element.
4170
4
    V = CGF.Builder.CreateAlignedLoad(
4171
4
        TyHi, CGF.Builder.CreateBitCast(RegHiAddr, PTyHi),
4172
4
        CharUnits::fromQuantity(getDataLayout().getABITypeAlignment(TyHi)));
4173
4
    CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 1));
4174
4175
4
    RegAddr = CGF.Builder.CreateElementBitCast(Tmp, LTy);
4176
76
  } else if (neededInt) {
4177
59
    RegAddr = Address(CGF.Builder.CreateGEP(CGF.Int8Ty, RegSaveArea, gp_offset),
4178
59
                      CGF.Int8Ty, CharUnits::fromQuantity(8));
4179
59
    RegAddr = CGF.Builder.CreateElementBitCast(RegAddr, LTy);
4180
4181
    // Copy to a temporary if necessary to ensure the appropriate alignment.
4182
59
    auto TInfo = getContext().getTypeInfoInChars(Ty);
4183
59
    uint64_t TySize = TInfo.Width.getQuantity();
4184
59
    CharUnits TyAlign = TInfo.Align;
4185
4186
    // Copy into a temporary if the type is more aligned than the
4187
    // register save area.
4188
59
    if (TyAlign.getQuantity() > 8) {
4189
3
      Address Tmp = CGF.CreateMemTemp(Ty);
4190
3
      CGF.Builder.CreateMemCpy(Tmp, RegAddr, TySize, false);
4191
3
      RegAddr = Tmp;
4192
3
    }
4193
4194
59
  } else 
if (17
neededSSE == 117
) {
4195
7
    RegAddr = Address(CGF.Builder.CreateGEP(CGF.Int8Ty, RegSaveArea, fp_offset),
4196
7
                      CGF.Int8Ty, CharUnits::fromQuantity(16));
4197
7
    RegAddr = CGF.Builder.CreateElementBitCast(RegAddr, LTy);
4198
10
  } else {
4199
10
    assert(neededSSE == 2 && "Invalid number of needed registers!");
4200
    // SSE registers are spaced 16 bytes apart in the register save
4201
    // area, we need to collect the two eightbytes together.
4202
    // The ABI isn't explicit about this, but it seems reasonable
4203
    // to assume that the slots are 16-byte aligned, since the stack is
4204
    // naturally 16-byte aligned and the prologue is expected to store
4205
    // all the SSE registers to the RSA.
4206
0
    Address RegAddrLo = Address(CGF.Builder.CreateGEP(CGF.Int8Ty, RegSaveArea,
4207
10
                                                      fp_offset),
4208
10
                                CGF.Int8Ty, CharUnits::fromQuantity(16));
4209
10
    Address RegAddrHi =
4210
10
      CGF.Builder.CreateConstInBoundsByteGEP(RegAddrLo,
4211
10
                                             CharUnits::fromQuantity(16));
4212
10
    llvm::Type *ST = AI.canHaveCoerceToType()
4213
10
                         ? AI.getCoerceToType()
4214
10
                         : 
llvm::StructType::get(CGF.DoubleTy, CGF.DoubleTy)0
;
4215
10
    llvm::Value *V;
4216
10
    Address Tmp = CGF.CreateMemTemp(Ty);
4217
10
    Tmp = CGF.Builder.CreateElementBitCast(Tmp, ST);
4218
10
    V = CGF.Builder.CreateLoad(CGF.Builder.CreateElementBitCast(
4219
10
        RegAddrLo, ST->getStructElementType(0)));
4220
10
    CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 0));
4221
10
    V = CGF.Builder.CreateLoad(CGF.Builder.CreateElementBitCast(
4222
10
        RegAddrHi, ST->getStructElementType(1)));
4223
10
    CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 1));
4224
4225
10
    RegAddr = CGF.Builder.CreateElementBitCast(Tmp, LTy);
4226
10
  }
4227
4228
  // AMD64-ABI 3.5.7p5: Step 5. Set:
4229
  // l->gp_offset = l->gp_offset + num_gp * 8
4230
  // l->fp_offset = l->fp_offset + num_fp * 16.
4231
80
  if (neededInt) {
4232
63
    llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededInt * 8);
4233
63
    CGF.Builder.CreateStore(CGF.Builder.CreateAdd(gp_offset, Offset),
4234
63
                            gp_offset_p);
4235
63
  }
4236
80
  if (neededSSE) {
4237
21
    llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededSSE * 16);
4238
21
    CGF.Builder.CreateStore(CGF.Builder.CreateAdd(fp_offset, Offset),
4239
21
                            fp_offset_p);
4240
21
  }
4241
80
  CGF.EmitBranch(ContBlock);
4242
4243
  // Emit code to load the value if it was passed in memory.
4244
4245
80
  CGF.EmitBlock(InMemBlock);
4246
80
  Address MemAddr = EmitX86_64VAArgFromMemory(CGF, VAListAddr, Ty);
4247
4248
  // Return the appropriate result.
4249
4250
80
  CGF.EmitBlock(ContBlock);
4251
80
  Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock, MemAddr, InMemBlock,
4252
80
                                 "vaarg.addr");
4253
80
  return ResAddr;
4254
94
}
4255
4256
Address X86_64ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
4257
8
                                   QualType Ty) const {
4258
  // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
4259
  // not 1, 2, 4, or 8 bytes, must be passed by reference."
4260
8
  uint64_t Width = getContext().getTypeSize(Ty);
4261
8
  bool IsIndirect = Width > 64 || 
!llvm::isPowerOf2_64(Width)4
;
4262
4263
8
  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect,
4264
8
                          CGF.getContext().getTypeInfoInChars(Ty),
4265
8
                          CharUnits::fromQuantity(8),
4266
8
                          /*allowHigherAlign*/ false);
4267
8
}
4268
4269
ABIArgInfo WinX86_64ABIInfo::reclassifyHvaArgForVectorCall(
4270
97
    QualType Ty, unsigned &FreeSSERegs, const ABIArgInfo &current) const {
4271
97
  const Type *Base = nullptr;
4272
97
  uint64_t NumElts = 0;
4273
4274
97
  if (!Ty->isBuiltinType() && 
!Ty->isVectorType()49
&&
4275
97
      
isHomogeneousAggregate(Ty, Base, NumElts)36
&&
FreeSSERegs >= NumElts27
) {
4276
18
    FreeSSERegs -= NumElts;
4277
18
    return getDirectX86Hva();
4278
18
  }
4279
79
  return current;
4280
97
}
4281
4282
ABIArgInfo WinX86_64ABIInfo::classify(QualType Ty, unsigned &FreeSSERegs,
4283
                                      bool IsReturnType, bool IsVectorCall,
4284
10.1k
                                      bool IsRegCall) const {
4285
4286
10.1k
  if (Ty->isVoidType())
4287
1.69k
    return ABIArgInfo::getIgnore();
4288
4289
8.43k
  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
4290
20
    Ty = EnumTy->getDecl()->getIntegerType();
4291
4292
8.43k
  TypeInfo Info = getContext().getTypeInfo(Ty);
4293
8.43k
  uint64_t Width = Info.Width;
4294
8.43k
  CharUnits Align = getContext().toCharUnitsFromBits(Info.Align);
4295
4296
8.43k
  const RecordType *RT = Ty->getAs<RecordType>();
4297
8.43k
  if (RT) {
4298
306
    if (!IsReturnType) {
4299
267
      if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI()))
4300
71
        return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
4301
267
    }
4302
4303
235
    if (RT->getDecl()->hasFlexibleArrayMember())
4304
0
      return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
4305
4306
235
  }
4307
4308
8.36k
  const Type *Base = nullptr;
4309
8.36k
  uint64_t NumElts = 0;
4310
  // vectorcall adds the concept of a homogenous vector aggregate, similar to
4311
  // other targets.
4312
8.36k
  if ((IsVectorCall || 
IsRegCall8.25k
) &&
4313
8.36k
      
isHomogeneousAggregate(Ty, Base, NumElts)175
) {
4314
95
    if (IsRegCall) {
4315
32
      if (FreeSSERegs >= NumElts) {
4316
32
        FreeSSERegs -= NumElts;
4317
32
        if (IsReturnType || 
Ty->isBuiltinType()27
||
Ty->isVectorType()21
)
4318
17
          return ABIArgInfo::getDirect();
4319
15
        return ABIArgInfo::getExpand();
4320
32
      }
4321
0
      return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
4322
63
    } else if (IsVectorCall) {
4323
63
      if (FreeSSERegs >= NumElts &&
4324
63
          
(57
IsReturnType57
||
Ty->isBuiltinType()45
||
Ty->isVectorType()36
)) {
4325
34
        FreeSSERegs -= NumElts;
4326
34
        return ABIArgInfo::getDirect();
4327
34
      } else 
if (29
IsReturnType29
) {
4328
0
        return ABIArgInfo::getExpand();
4329
29
      } else if (!Ty->isBuiltinType() && 
!Ty->isVectorType()27
) {
4330
        // HVAs are delayed and reclassified in the 2nd step.
4331
27
        return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
4332
27
      }
4333
63
    }
4334
95
  }
4335
4336
8.26k
  if (Ty->isMemberPointerType()) {
4337
    // If the member pointer is represented by an LLVM int or ptr, pass it
4338
    // directly.
4339
160
    llvm::Type *LLTy = CGT.ConvertType(Ty);
4340
160
    if (LLTy->isPointerTy() || 
LLTy->isIntegerTy()77
)
4341
91
      return ABIArgInfo::getDirect();
4342
160
  }
4343
4344
8.17k
  if (RT || 
Ty->isAnyComplexType()7.99k
||
Ty->isMemberPointerType()7.97k
) {
4345
    // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
4346
    // not 1, 2, 4, or 8 bytes, must be passed by reference."
4347
273
    if (Width > 64 || 
!llvm::isPowerOf2_64(Width)150
)
4348
123
      return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
4349
4350
    // Otherwise, coerce it to a small integer.
4351
150
    return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Width));
4352
273
  }
4353
4354
7.90k
  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
4355
2.22k
    switch (BT->getKind()) {
4356
32
    case BuiltinType::Bool:
4357
      // Bool type is always extended to the ABI, other builtin types are not
4358
      // extended.
4359
32
      return ABIArgInfo::getExtend(Ty);
4360
4361
64
    case BuiltinType::LongDouble:
4362
      // Mingw64 GCC uses the old 80 bit extended precision floating point
4363
      // unit. It passes them indirectly through memory.
4364
64
      if (IsMingw64) {
4365
6
        const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
4366
6
        if (LDF == &llvm::APFloat::x87DoubleExtended())
4367
6
          return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
4368
6
      }
4369
58
      break;
4370
4371
58
    case BuiltinType::Int128:
4372
10
    case BuiltinType::UInt128:
4373
      // If it's a parameter type, the normal ABI rule is that arguments larger
4374
      // than 8 bytes are passed indirectly. GCC follows it. We follow it too,
4375
      // even though it isn't particularly efficient.
4376
10
      if (!IsReturnType)
4377
4
        return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
4378
4379
      // Mingw64 GCC returns i128 in XMM0. Coerce to v2i64 to handle that.
4380
      // Clang matches them for compatibility.
4381
6
      return ABIArgInfo::getDirect(llvm::FixedVectorType::get(
4382
6
          llvm::Type::getInt64Ty(getVMContext()), 2));
4383
4384
2.11k
    default:
4385
2.11k
      break;
4386
2.22k
    }
4387
2.22k
  }
4388
4389
7.85k
  if (Ty->isBitIntType()) {
4390
    // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
4391
    // not 1, 2, 4, or 8 bytes, must be passed by reference."
4392
    // However, non-power-of-two bit-precise integers will be passed as 1, 2, 4,
4393
    // or 8 bytes anyway as long is it fits in them, so we don't have to check
4394
    // the power of 2.
4395
51
    if (Width <= 64)
4396
37
      return ABIArgInfo::getDirect();
4397
14
    return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
4398
51
  }
4399
4400
7.80k
  return ABIArgInfo::getDirect();
4401
7.85k
}
4402
4403
4.18k
void WinX86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
4404
4.18k
  const unsigned CC = FI.getCallingConvention();
4405
4.18k
  bool IsVectorCall = CC == llvm::CallingConv::X86_VectorCall;
4406
4.18k
  bool IsRegCall = CC == llvm::CallingConv::X86_RegCall;
4407
4408
  // If __attribute__((sysv_abi)) is in use, use the SysV argument
4409
  // classification rules.
4410
4.18k
  if (CC == llvm::CallingConv::X86_64_SysV) {
4411
14
    X86_64ABIInfo SysVABIInfo(CGT, AVXLevel);
4412
14
    SysVABIInfo.computeInfo(FI);
4413
14
    return;
4414
14
  }
4415
4416
4.17k
  unsigned FreeSSERegs = 0;
4417
4.17k
  if (IsVectorCall) {
4418
    // We can use up to 4 SSE return registers with vectorcall.
4419
49
    FreeSSERegs = 4;
4420
4.12k
  } else if (IsRegCall) {
4421
    // RegCall gives us 16 SSE registers.
4422
26
    FreeSSERegs = 16;
4423
26
  }
4424
4425
4.17k
  if (!getCXXABI().classifyReturnType(FI))
4426
4.12k
    FI.getReturnInfo() = classify(FI.getReturnType(), FreeSSERegs, true,
4427
4.12k
                                  IsVectorCall, IsRegCall);
4428
4429
4.17k
  if (IsVectorCall) {
4430
    // We can use up to 6 SSE register parameters with vectorcall.
4431
49
    FreeSSERegs = 6;
4432
4.12k
  } else if (IsRegCall) {
4433
    // RegCall gives us 16 SSE registers, we can reuse the return registers.
4434
26
    FreeSSERegs = 16;
4435
26
  }
4436
4437
4.17k
  unsigned ArgNum = 0;
4438
4.17k
  unsigned ZeroSSERegs = 0;
4439
6.00k
  for (auto &I : FI.arguments()) {
4440
    // Vectorcall in x64 only permits the first 6 arguments to be passed as
4441
    // XMM/YMM registers. After the sixth argument, pretend no vector
4442
    // registers are left.
4443
6.00k
    unsigned *MaybeFreeSSERegs =
4444
6.00k
        (IsVectorCall && 
ArgNum >= 697
) ?
&ZeroSSERegs5
:
&FreeSSERegs5.99k
;
4445
6.00k
    I.info =
4446
6.00k
        classify(I.type, *MaybeFreeSSERegs, false, IsVectorCall, IsRegCall);
4447
6.00k
    ++ArgNum;
4448
6.00k
  }
4449
4450
4.17k
  if (IsVectorCall) {
4451
    // For vectorcall, assign aggregate HVAs to any free vector registers in a
4452
    // second pass.
4453
49
    for (auto &I : FI.arguments())
4454
97
      I.info = reclassifyHvaArgForVectorCall(I.type, FreeSSERegs, I.info);
4455
49
  }
4456
4.17k
}
4457
4458
Address WinX86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4459
19
                                    QualType Ty) const {
4460
  // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
4461
  // not 1, 2, 4, or 8 bytes, must be passed by reference."
4462
19
  uint64_t Width = getContext().getTypeSize(Ty);
4463
19
  bool IsIndirect = Width > 64 || 
!llvm::isPowerOf2_64(Width)8
;
4464
4465
19
  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect,
4466
19
                          CGF.getContext().getTypeInfoInChars(Ty),
4467
19
                          CharUnits::fromQuantity(8),
4468
19
                          /*allowHigherAlign*/ false);
4469
19
}
4470
4471
static bool PPC_initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4472
                                        llvm::Value *Address, bool Is64Bit,
4473
4
                                        bool IsAIX) {
4474
  // This is calculated from the LLVM and GCC tables and verified
4475
  // against gcc output.  AFAIK all PPC ABIs use the same encoding.
4476
4477
4
  CodeGen::CGBuilderTy &Builder = CGF.Builder;
4478
4479
4
  llvm::IntegerType *i8 = CGF.Int8Ty;
4480
4
  llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
4481
4
  llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
4482
4
  llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16);
4483
4484
  // 0-31: r0-31, the 4-byte or 8-byte general-purpose registers
4485
4
  AssignToArrayRange(Builder, Address, Is64Bit ? 
Eight82
:
Four82
, 0, 31);
4486
4487
  // 32-63: fp0-31, the 8-byte floating-point registers
4488
4
  AssignToArrayRange(Builder, Address, Eight8, 32, 63);
4489
4490
  // 64-67 are various 4-byte or 8-byte special-purpose registers:
4491
  // 64: mq
4492
  // 65: lr
4493
  // 66: ctr
4494
  // 67: ap
4495
4
  AssignToArrayRange(Builder, Address, Is64Bit ? 
Eight82
:
Four82
, 64, 67);
4496
4497
  // 68-76 are various 4-byte special-purpose registers:
4498
  // 68-75 cr0-7
4499
  // 76: xer
4500
4
  AssignToArrayRange(Builder, Address, Four8, 68, 76);
4501
4502
  // 77-108: v0-31, the 16-byte vector registers
4503
4
  AssignToArrayRange(Builder, Address, Sixteen8, 77, 108);
4504
4505
  // 109: vrsave
4506
  // 110: vscr
4507
4
  AssignToArrayRange(Builder, Address, Is64Bit ? 
Eight82
:
Four82
, 109, 110);
4508
4509
  // AIX does not utilize the rest of the registers.
4510
4
  if (IsAIX)
4511
2
    return false;
4512
4513
  // 111: spe_acc
4514
  // 112: spefscr
4515
  // 113: sfp
4516
2
  AssignToArrayRange(Builder, Address, Is64Bit ? 
Eight81
:
Four81
, 111, 113);
4517
4518
2
  if (!Is64Bit)
4519
1
    return false;
4520
4521
  // TODO: Need to verify if these registers are used on 64 bit AIX with Power8
4522
  // or above CPU.
4523
  // 64-bit only registers:
4524
  // 114: tfhar
4525
  // 115: tfiar
4526
  // 116: texasr
4527
1
  AssignToArrayRange(Builder, Address, Eight8, 114, 116);
4528
4529
1
  return false;
4530
2
}
4531
4532
// AIX
4533
namespace {
4534
/// AIXABIInfo - The AIX XCOFF ABI information.
4535
class AIXABIInfo : public ABIInfo {
4536
  const bool Is64Bit;
4537
  const unsigned PtrByteSize;
4538
  CharUnits getParamTypeAlignment(QualType Ty) const;
4539
4540
public:
4541
  AIXABIInfo(CodeGen::CodeGenTypes &CGT, bool Is64Bit)
4542
99
      : ABIInfo(CGT), Is64Bit(Is64Bit), PtrByteSize(Is64Bit ? 8 : 4) {}
4543
4544
  bool isPromotableTypeForABI(QualType Ty) const;
4545
4546
  ABIArgInfo classifyReturnType(QualType RetTy) const;
4547
  ABIArgInfo classifyArgumentType(QualType Ty) const;
4548
4549
227
  void computeInfo(CGFunctionInfo &FI) const override {
4550
227
    if (!getCXXABI().classifyReturnType(FI))
4551
227
      FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
4552
4553
227
    for (auto &I : FI.arguments())
4554
174
      I.info = classifyArgumentType(I.type);
4555
227
  }
4556
4557
  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4558
                    QualType Ty) const override;
4559
};
4560
4561
class AIXTargetCodeGenInfo : public TargetCodeGenInfo {
4562
  const bool Is64Bit;
4563
4564
public:
4565
  AIXTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, bool Is64Bit)
4566
      : TargetCodeGenInfo(std::make_unique<AIXABIInfo>(CGT, Is64Bit)),
4567
99
        Is64Bit(Is64Bit) {}
4568
2
  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4569
2
    return 1; // r1 is the dedicated stack pointer
4570
2
  }
4571
4572
  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4573
                               llvm::Value *Address) const override;
4574
};
4575
} // namespace
4576
4577
// Return true if the ABI requires Ty to be passed sign- or zero-
4578
// extended to 32/64 bits.
4579
281
bool AIXABIInfo::isPromotableTypeForABI(QualType Ty) const {
4580
  // Treat an enum type as its underlying type.
4581
281
  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
4582
2
    Ty = EnumTy->getDecl()->getIntegerType();
4583
4584
  // Promotable integer types are required to be promoted by the ABI.
4585
281
  if (Ty->isPromotableIntegerType())
4586
3
    return true;
4587
4588
278
  if (!Is64Bit)
4589
155
    return false;
4590
4591
  // For 64 bit mode, in addition to the usual promotable integer types, we also
4592
  // need to extend all 32-bit types, since the ABI requires promotion to 64
4593
  // bits.
4594
123
  if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
4595
78
    switch (BT->getKind()) {
4596
50
    case BuiltinType::Int:
4597
54
    case BuiltinType::UInt:
4598
54
      return true;
4599
24
    default:
4600
24
      break;
4601
78
    }
4602
4603
69
  return false;
4604
123
}
4605
4606
227
ABIArgInfo AIXABIInfo::classifyReturnType(QualType RetTy) const {
4607
227
  if (RetTy->isAnyComplexType())
4608
6
    return ABIArgInfo::getDirect();
4609
4610
221
  if (RetTy->isVectorType())
4611
0
    return ABIArgInfo::getDirect();
4612
4613
221
  if (RetTy->isVoidType())
4614
103
    return ABIArgInfo::getIgnore();
4615
4616
118
  if (isAggregateTypeForABI(RetTy))
4617
2
    return getNaturalAlignIndirect(RetTy);
4618
4619
116
  return (isPromotableTypeForABI(RetTy) ? 
ABIArgInfo::getExtend(RetTy)30
4620
116
                                        : 
ABIArgInfo::getDirect()86
);
4621
118
}
4622
4623
174
ABIArgInfo AIXABIInfo::classifyArgumentType(QualType Ty) const {
4624
174
  Ty = useFirstFieldIfTransparentUnion(Ty);
4625
4626
174
  if (Ty->isAnyComplexType())
4627
6
    return ABIArgInfo::getDirect();
4628
4629
168
  if (Ty->isVectorType())
4630
0
    return ABIArgInfo::getDirect();
4631
4632
168
  if (isAggregateTypeForABI(Ty)) {
4633
    // Records with non-trivial destructors/copy-constructors should not be
4634
    // passed by value.
4635
3
    if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
4636
0
      return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
4637
4638
3
    CharUnits CCAlign = getParamTypeAlignment(Ty);
4639
3
    CharUnits TyAlign = getContext().getTypeAlignInChars(Ty);
4640
4641
3
    return ABIArgInfo::getIndirect(CCAlign, /*ByVal*/ true,
4642
3
                                   /*Realign*/ TyAlign > CCAlign);
4643
3
  }
4644
4645
165
  return (isPromotableTypeForABI(Ty) ? 
ABIArgInfo::getExtend(Ty)27
4646
165
                                     : 
ABIArgInfo::getDirect()138
);
4647
168
}
4648
4649
3
CharUnits AIXABIInfo::getParamTypeAlignment(QualType Ty) const {
4650
  // Complex types are passed just like their elements.
4651
3
  if (const ComplexType *CTy = Ty->getAs<ComplexType>())
4652
0
    Ty = CTy->getElementType();
4653
4654
3
  if (Ty->isVectorType())
4655
0
    return CharUnits::fromQuantity(16);
4656
4657
  // If the structure contains a vector type, the alignment is 16.
4658
3
  if (isRecordWithSIMDVectorType(getContext(), Ty))
4659
0
    return CharUnits::fromQuantity(16);
4660
4661
3
  return CharUnits::fromQuantity(PtrByteSize);
4662
3
}
4663
4664
Address AIXABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4665
0
                              QualType Ty) const {
4666
4667
0
  auto TypeInfo = getContext().getTypeInfoInChars(Ty);
4668
0
  TypeInfo.Align = getParamTypeAlignment(Ty);
4669
4670
0
  CharUnits SlotSize = CharUnits::fromQuantity(PtrByteSize);
4671
4672
  // If we have a complex type and the base type is smaller than the register
4673
  // size, the ABI calls for the real and imaginary parts to be right-adjusted
4674
  // in separate words in 32bit mode or doublewords in 64bit mode. However,
4675
  // Clang expects us to produce a pointer to a structure with the two parts
4676
  // packed tightly. So generate loads of the real and imaginary parts relative
4677
  // to the va_list pointer, and store them to a temporary structure. We do the
4678
  // same as the PPC64ABI here.
4679
0
  if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
4680
0
    CharUnits EltSize = TypeInfo.Width / 2;
4681
0
    if (EltSize < SlotSize)
4682
0
      return complexTempStructure(CGF, VAListAddr, Ty, SlotSize, EltSize, CTy);
4683
0
  }
4684
4685
0
  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false, TypeInfo,
4686
0
                          SlotSize, /*AllowHigher*/ true);
4687
0
}
4688
4689
bool AIXTargetCodeGenInfo::initDwarfEHRegSizeTable(
4690
2
    CodeGen::CodeGenFunction &CGF, llvm::Value *Address) const {
4691
2
  return PPC_initDwarfEHRegSizeTable(CGF, Address, Is64Bit, /*IsAIX*/ true);
4692
2
}
4693
4694
// PowerPC-32
4695
namespace {
4696
/// PPC32_SVR4_ABIInfo - The 32-bit PowerPC ELF (SVR4) ABI information.
4697
class PPC32_SVR4_ABIInfo : public DefaultABIInfo {
4698
  bool IsSoftFloatABI;
4699
  bool IsRetSmallStructInRegABI;
4700
4701
  CharUnits getParamTypeAlignment(QualType Ty) const;
4702
4703
public:
4704
  PPC32_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, bool SoftFloatABI,
4705
                     bool RetSmallStructInRegABI)
4706
      : DefaultABIInfo(CGT), IsSoftFloatABI(SoftFloatABI),
4707
65
        IsRetSmallStructInRegABI(RetSmallStructInRegABI) {}
4708
4709
  ABIArgInfo classifyReturnType(QualType RetTy) const;
4710
4711
166
  void computeInfo(CGFunctionInfo &FI) const override {
4712
166
    if (!getCXXABI().classifyReturnType(FI))
4713
166
      FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
4714
166
    for (auto &I : FI.arguments())
4715
277
      I.info = classifyArgumentType(I.type);
4716
166
  }
4717
4718
  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4719
                    QualType Ty) const override;
4720
};
4721
4722
class PPC32TargetCodeGenInfo : public TargetCodeGenInfo {
4723
public:
4724
  PPC32TargetCodeGenInfo(CodeGenTypes &CGT, bool SoftFloatABI,
4725
                         bool RetSmallStructInRegABI)
4726
      : TargetCodeGenInfo(std::make_unique<PPC32_SVR4_ABIInfo>(
4727
65
            CGT, SoftFloatABI, RetSmallStructInRegABI)) {}
4728
4729
  static bool isStructReturnInRegABI(const llvm::Triple &Triple,
4730
                                     const CodeGenOptions &Opts);
4731
4732
1
  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4733
    // This is recovered from gcc output.
4734
1
    return 1; // r1 is the dedicated stack pointer
4735
1
  }
4736
4737
  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4738
                               llvm::Value *Address) const override;
4739
};
4740
}
4741
4742
0
CharUnits PPC32_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
4743
  // Complex types are passed just like their elements.
4744
0
  if (const ComplexType *CTy = Ty->getAs<ComplexType>())
4745
0
    Ty = CTy->getElementType();
4746
4747
0
  if (Ty->isVectorType())
4748
0
    return CharUnits::fromQuantity(getContext().getTypeSize(Ty) == 128 ? 16
4749
0
                                                                       : 4);
4750
4751
  // For single-element float/vector structs, we consider the whole type
4752
  // to have the same alignment requirements as its single element.
4753
0
  const Type *AlignTy = nullptr;
4754
0
  if (const Type *EltType = isSingleElementStruct(Ty, getContext())) {
4755
0
    const BuiltinType *BT = EltType->getAs<BuiltinType>();
4756
0
    if ((EltType->isVectorType() && getContext().getTypeSize(EltType) == 128) ||
4757
0
        (BT && BT->isFloatingPoint()))
4758
0
      AlignTy = EltType;
4759
0
  }
4760
4761
0
  if (AlignTy)
4762
0
    return CharUnits::fromQuantity(AlignTy->isVectorType() ? 16 : 4);
4763
0
  return CharUnits::fromQuantity(4);
4764
0
}
4765
4766
166
ABIArgInfo PPC32_SVR4_ABIInfo::classifyReturnType(QualType RetTy) const {
4767
166
  uint64_t Size;
4768
4769
  // -msvr4-struct-return puts small aggregates in GPR3 and GPR4.
4770
166
  if (isAggregateTypeForABI(RetTy) && 
IsRetSmallStructInRegABI21
&&
4771
166
      
(Size = getContext().getTypeSize(RetTy)) <= 6418
) {
4772
    // System V ABI (1995), page 3-22, specified:
4773
    // > A structure or union whose size is less than or equal to 8 bytes
4774
    // > shall be returned in r3 and r4, as if it were first stored in the
4775
    // > 8-byte aligned memory area and then the low addressed word were
4776
    // > loaded into r3 and the high-addressed word into r4.  Bits beyond
4777
    // > the last member of the structure or union are not defined.
4778
    //
4779
    // GCC for big-endian PPC32 inserts the pad before the first member,
4780
    // not "beyond the last member" of the struct.  To stay compatible
4781
    // with GCC, we coerce the struct to an integer of the same size.
4782
    // LLVM will extend it and return i32 in r3, or i64 in r3:r4.
4783
7
    if (Size == 0)
4784
1
      return ABIArgInfo::getIgnore();
4785
6
    else {
4786
6
      llvm::Type *CoerceTy = llvm::Type::getIntNTy(getVMContext(), Size);
4787
6
      return ABIArgInfo::getDirect(CoerceTy);
4788
6
    }
4789
7
  }
4790
4791
159
  return DefaultABIInfo::classifyReturnType(RetTy);
4792
166
}
4793
4794
// TODO: this implementation is now likely redundant with
4795
// DefaultABIInfo::EmitVAArg.
4796
Address PPC32_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAList,
4797
1
                                      QualType Ty) const {
4798
1
  if (getTarget().getTriple().isOSDarwin()) {
4799
0
    auto TI = getContext().getTypeInfoInChars(Ty);
4800
0
    TI.Align = getParamTypeAlignment(Ty);
4801
4802
0
    CharUnits SlotSize = CharUnits::fromQuantity(4);
4803
0
    return emitVoidPtrVAArg(CGF, VAList, Ty,
4804
0
                            classifyArgumentType(Ty).isIndirect(), TI, SlotSize,
4805
0
                            /*AllowHigherAlign=*/true);
4806
0
  }
4807
4808
1
  const unsigned OverflowLimit = 8;
4809
1
  if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
4810
    // TODO: Implement this. For now ignore.
4811
0
    (void)CTy;
4812
0
    return Address::invalid(); // FIXME?
4813
0
  }
4814
4815
  // struct __va_list_tag {
4816
  //   unsigned char gpr;
4817
  //   unsigned char fpr;
4818
  //   unsigned short reserved;
4819
  //   void *overflow_arg_area;
4820
  //   void *reg_save_area;
4821
  // };
4822
4823
1
  bool isI64 = Ty->isIntegerType() && 
getContext().getTypeSize(Ty) == 640
;
4824
1
  bool isInt = !Ty->isFloatingType();
4825
1
  bool isF64 = Ty->isFloatingType() && getContext().getTypeSize(Ty) == 64;
4826
4827
  // All aggregates are passed indirectly?  That doesn't seem consistent
4828
  // with the argument-lowering code.
4829
1
  bool isIndirect = isAggregateTypeForABI(Ty);
4830
4831
1
  CGBuilderTy &Builder = CGF.Builder;
4832
4833
  // The calling convention either uses 1-2 GPRs or 1 FPR.
4834
1
  Address NumRegsAddr = Address::invalid();
4835
1
  if (isInt || IsSoftFloatABI) {
4836
1
    NumRegsAddr = Builder.CreateStructGEP(VAList, 0, "gpr");
4837
1
  } else {
4838
0
    NumRegsAddr = Builder.CreateStructGEP(VAList, 1, "fpr");
4839
0
  }
4840
4841
1
  llvm::Value *NumRegs = Builder.CreateLoad(NumRegsAddr, "numUsedRegs");
4842
4843
  // "Align" the register count when TY is i64.
4844
1
  if (isI64 || (isF64 && IsSoftFloatABI)) {
4845
1
    NumRegs = Builder.CreateAdd(NumRegs, Builder.getInt8(1));
4846
1
    NumRegs = Builder.CreateAnd(NumRegs, Builder.getInt8((uint8_t) ~1U));
4847
1
  }
4848
4849
1
  llvm::Value *CC =
4850
1
      Builder.CreateICmpULT(NumRegs, Builder.getInt8(OverflowLimit), "cond");
4851
4852
1
  llvm::BasicBlock *UsingRegs = CGF.createBasicBlock("using_regs");
4853
1
  llvm::BasicBlock *UsingOverflow = CGF.createBasicBlock("using_overflow");
4854
1
  llvm::BasicBlock *Cont = CGF.createBasicBlock("cont");
4855
4856
1
  Builder.CreateCondBr(CC, UsingRegs, UsingOverflow);
4857
4858
1
  llvm::Type *DirectTy = CGF.ConvertType(Ty), *ElementTy = DirectTy;
4859
1
  if (isIndirect) 
DirectTy = DirectTy->getPointerTo(0)0
;
4860
4861
  // Case 1: consume registers.
4862
1
  Address RegAddr = Address::invalid();
4863
1
  {
4864
1
    CGF.EmitBlock(UsingRegs);
4865
4866
1
    Address RegSaveAreaPtr = Builder.CreateStructGEP(VAList, 4);
4867
1
    RegAddr = Address(Builder.CreateLoad(RegSaveAreaPtr), CGF.Int8Ty,
4868
1
                      CharUnits::fromQuantity(8));
4869
1
    assert(RegAddr.getElementType() == CGF.Int8Ty);
4870
4871
    // Floating-point registers start after the general-purpose registers.
4872
1
    if (!(isInt || IsSoftFloatABI)) {
4873
0
      RegAddr = Builder.CreateConstInBoundsByteGEP(RegAddr,
4874
0
                                                   CharUnits::fromQuantity(32));
4875
0
    }
4876
4877
    // Get the address of the saved value by scaling the number of
4878
    // registers we've used by the number of
4879
1
    CharUnits RegSize = CharUnits::fromQuantity((isInt || IsSoftFloatABI) ? 4 : 
80
);
4880
1
    llvm::Value *RegOffset =
4881
1
        Builder.CreateMul(NumRegs, Builder.getInt8(RegSize.getQuantity()));
4882
1
    RegAddr = Address(
4883
1
        Builder.CreateInBoundsGEP(CGF.Int8Ty, RegAddr.getPointer(), RegOffset),
4884
1
        CGF.Int8Ty, RegAddr.getAlignment().alignmentOfArrayElement(RegSize));
4885
1
    RegAddr = Builder.CreateElementBitCast(RegAddr, DirectTy);
4886
4887
    // Increase the used-register count.
4888
1
    NumRegs =
4889
1
      Builder.CreateAdd(NumRegs,
4890
1
                        Builder.getInt8((isI64 || (isF64 && IsSoftFloatABI)) ? 2 : 
10
));
4891
1
    Builder.CreateStore(NumRegs, NumRegsAddr);
4892
4893
1
    CGF.EmitBranch(Cont);
4894
1
  }
4895
4896
  // Case 2: consume space in the overflow area.
4897
0
  Address MemAddr = Address::invalid();
4898
1
  {
4899
1
    CGF.EmitBlock(UsingOverflow);
4900
4901
1
    Builder.CreateStore(Builder.getInt8(OverflowLimit), NumRegsAddr);
4902
4903
    // Everything in the overflow area is rounded up to a size of at least 4.
4904
1
    CharUnits OverflowAreaAlign = CharUnits::fromQuantity(4);
4905
4906
1
    CharUnits Size;
4907
1
    if (!isIndirect) {
4908
1
      auto TypeInfo = CGF.getContext().getTypeInfoInChars(Ty);
4909
1
      Size = TypeInfo.Width.alignTo(OverflowAreaAlign);
4910
1
    } else {
4911
0
      Size = CGF.getPointerSize();
4912
0
    }
4913
4914
1
    Address OverflowAreaAddr = Builder.CreateStructGEP(VAList, 3);
4915
1
    Address OverflowArea =
4916
1
        Address(Builder.CreateLoad(OverflowAreaAddr, "argp.cur"), CGF.Int8Ty,
4917
1
                OverflowAreaAlign);
4918
    // Round up address of argument to alignment
4919
1
    CharUnits Align = CGF.getContext().getTypeAlignInChars(Ty);
4920
1
    if (Align > OverflowAreaAlign) {
4921
1
      llvm::Value *Ptr = OverflowArea.getPointer();
4922
1
      OverflowArea = Address(emitRoundPointerUpToAlignment(CGF, Ptr, Align),
4923
1
                             OverflowArea.getElementType(), Align);
4924
1
    }
4925
4926
1
    MemAddr = Builder.CreateElementBitCast(OverflowArea, DirectTy);
4927
4928
    // Increase the overflow area.
4929
1
    OverflowArea = Builder.CreateConstInBoundsByteGEP(OverflowArea, Size);
4930
1
    Builder.CreateStore(OverflowArea.getPointer(), OverflowAreaAddr);
4931
1
    CGF.EmitBranch(Cont);
4932
1
  }
4933
4934
1
  CGF.EmitBlock(Cont);
4935
4936
  // Merge the cases with a phi.
4937
1
  Address Result = emitMergePHI(CGF, RegAddr, UsingRegs, MemAddr, UsingOverflow,
4938
1
                                "vaarg.addr");
4939
4940
  // Load the pointer if the argument was passed indirectly.
4941
1
  if (isIndirect) {
4942
0
    Result = Address(Builder.CreateLoad(Result, "aggr"), ElementTy,
4943
0
                     getContext().getTypeAlignInChars(Ty));
4944
0
  }
4945
4946
1
  return Result;
4947
1
}
4948
4949
bool PPC32TargetCodeGenInfo::isStructReturnInRegABI(
4950
65
    const llvm::Triple &Triple, const CodeGenOptions &Opts) {
4951
65
  assert(Triple.isPPC32());
4952
4953
0
  switch (Opts.getStructReturnConvention()) {
4954
65
  case CodeGenOptions::SRCK_Default:
4955
65
    break;
4956
0
  case CodeGenOptions::SRCK_OnStack: // -maix-struct-return
4957
0
    return false;
4958
0
  case CodeGenOptions::SRCK_InRegs: // -msvr4-struct-return
4959
0
    return true;
4960
65
  }
4961
4962
65
  if (Triple.isOSBinFormatELF() && !Triple.isOSLinux())
4963
56
    return true;
4964
4965
9
  return false;
4966
65
}
4967
4968
bool
4969
PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4970
1
                                                llvm::Value *Address) const {
4971
1
  return PPC_initDwarfEHRegSizeTable(CGF, Address, /*Is64Bit*/ false,
4972
1
                                     /*IsAIX*/ false);
4973
1
}
4974
4975
// PowerPC-64
4976
4977
namespace {
4978
/// PPC64_SVR4_ABIInfo - The 64-bit PowerPC ELF (SVR4) ABI information.
4979
class PPC64_SVR4_ABIInfo : public SwiftABIInfo {
4980
public:
4981
  enum ABIKind {
4982
    ELFv1 = 0,
4983
    ELFv2
4984
  };
4985
4986
private:
4987
  static const unsigned GPRBits = 64;
4988
  ABIKind Kind;
4989
  bool IsSoftFloatABI;
4990
4991
public:
4992
  PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, ABIKind Kind,
4993
                     bool SoftFloatABI)
4994
2.54k
      : SwiftABIInfo(CGT), Kind(Kind), IsSoftFloatABI(SoftFloatABI) {}
4995
4996
  bool isPromotableTypeForABI(QualType Ty) const;
4997
  CharUnits getParamTypeAlignment(QualType Ty) const;
4998
4999
  ABIArgInfo classifyReturnType(QualType RetTy) const;
5000
  ABIArgInfo classifyArgumentType(QualType Ty) const;
5001
5002
  bool isHomogeneousAggregateBaseType(QualType Ty) const override;
5003
  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
5004
                                         uint64_t Members) const override;
5005
5006
  // TODO: We can add more logic to computeInfo to improve performance.
5007
  // Example: For aggregate arguments that fit in a register, we could
5008
  // use getDirectInReg (as is done below for structs containing a single
5009
  // floating-point value) to avoid pushing them to memory on function
5010
  // entry.  This would require changing the logic in PPCISelLowering
5011
  // when lowering the parameters in the caller and args in the callee.
5012
13.5k
  void computeInfo(CGFunctionInfo &FI) const override {
5013
13.5k
    if (!getCXXABI().classifyReturnType(FI))
5014
13.5k
      FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
5015
26.8k
    for (auto &I : FI.arguments()) {
5016
      // We rely on the default argument classification for the most part.
5017
      // One exception:  An aggregate containing a single floating-point
5018
      // or vector item must be passed in a register if one is available.
5019
26.8k
      const Type *T = isSingleElementStruct(I.type, getContext());
5020
26.8k
      if (T) {
5021
23
        const BuiltinType *BT = T->getAs<BuiltinType>();
5022
23
        if ((T->isVectorType() && 
getContext().getTypeSize(T) == 1283
) ||
5023
23
            
(21
BT21
&&
BT->isFloatingPoint()18
)) {
5024
19
          QualType QT(T, 0);
5025
19
          I.info = ABIArgInfo::getDirectInReg(CGT.ConvertType(QT));
5026
19
          continue;
5027
19
        }
5028
23
      }
5029
26.8k
      I.info = classifyArgumentType(I.type);
5030
26.8k
    }
5031
13.5k
  }
5032
5033
  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
5034
                    QualType Ty) const override;
5035
5036
  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
5037
0
                                    bool asReturnValue) const override {
5038
0
    return occupiesMoreThan(CGT, scalars, /*total*/ 4);
5039
0
  }
5040
5041
0
  bool isSwiftErrorInRegister() const override {
5042
0
    return false;
5043
0
  }
5044
};
5045
5046
class PPC64_SVR4_TargetCodeGenInfo : public TargetCodeGenInfo {
5047
5048
public:
5049
  PPC64_SVR4_TargetCodeGenInfo(CodeGenTypes &CGT,
5050
                               PPC64_SVR4_ABIInfo::ABIKind Kind,
5051
                               bool SoftFloatABI)
5052
      : TargetCodeGenInfo(
5053
2.54k
            std::make_unique<PPC64_SVR4_ABIInfo>(CGT, Kind, SoftFloatABI)) {}
5054
5055
1
  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
5056
    // This is recovered from gcc output.
5057
1
    return 1; // r1 is the dedicated stack pointer
5058
1
  }
5059
5060
  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
5061
                               llvm::Value *Address) const override;
5062
};
5063
5064
class PPC64TargetCodeGenInfo : public DefaultTargetCodeGenInfo {
5065
public:
5066
0
  PPC64TargetCodeGenInfo(CodeGenTypes &CGT) : DefaultTargetCodeGenInfo(CGT) {}
5067
5068
0
  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
5069
    // This is recovered from gcc output.
5070
0
    return 1; // r1 is the dedicated stack pointer
5071
0
  }
5072
5073
  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
5074
                               llvm::Value *Address) const override;
5075
};
5076
5077
}
5078
5079
// Return true if the ABI requires Ty to be passed sign- or zero-
5080
// extended to 64 bits.
5081
bool
5082
29.5k
PPC64_SVR4_ABIInfo::isPromotableTypeForABI(QualType Ty) const {
5083
  // Treat an enum type as its underlying type.
5084
29.5k
  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
5085
0
    Ty = EnumTy->getDecl()->getIntegerType();
5086
5087
  // Promotable integer types are required to be promoted by the ABI.
5088
29.5k
  if (isPromotableIntegerTypeForABI(Ty))
5089
63
    return true;
5090
5091
  // In addition to the usual promotable integer types, we also need to
5092
  // extend all 32-bit types, since the ABI requires promotion to 64 bits.
5093
29.5k
  if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
5094
12.5k
    switch (BT->getKind()) {
5095
5.26k
    case BuiltinType::Int:
5096
5.28k
    case BuiltinType::UInt:
5097
5.28k
      return true;
5098
7.28k
    default:
5099
7.28k
      break;
5100
12.5k
    }
5101
5102
24.2k
  if (const auto *EIT = Ty->getAs<BitIntType>())
5103
9
    if (EIT->getNumBits() < 64)
5104
2
      return true;
5105
5106
24.2k
  return false;
5107
24.2k
}
5108
5109
/// isAlignedParamType - Determine whether a type requires 16-byte or
5110
/// higher alignment in the parameter area.  Always returns at least 8.
5111
130
CharUnits PPC64_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
5112
  // Complex types are passed just like their elements.
5113
130
  if (const ComplexType *CTy = Ty->getAs<ComplexType>())
5114
0
    Ty = CTy->getElementType();
5115
5116
159
  auto FloatUsesVector = [this](QualType Ty){
5117
159
    return Ty->isRealFloatingType() && &getContext().getFloatTypeSemantics(
5118
44
                                           Ty) == &llvm::APFloat::IEEEquad();
5119
159
  };
5120
5121
  // Only vector types of size 16 bytes need alignment (larger types are
5122
  // passed via reference, smaller types are not aligned).
5123
130
  if (Ty->isVectorType()) {
5124
0
    return CharUnits::fromQuantity(getContext().getTypeSize(Ty) == 128 ? 16 : 8);
5125
130
  } else if (FloatUsesVector(Ty)) {
5126
    // According to ABI document section 'Optional Save Areas': If extended
5127
    // precision floating-point values in IEEE BINARY 128 QUADRUPLE PRECISION
5128
    // format are supported, map them to a single quadword, quadword aligned.
5129
9
    return CharUnits::fromQuantity(16);
5130
9
  }
5131
5132
  // For single-element float/vector structs, we consider the whole type
5133
  // to have the same alignment requirements as its single element.
5134
121
  const Type *AlignAsType = nullptr;
5135
121
  const Type *EltType = isSingleElementStruct(Ty, getContext());
5136
121
  if (EltType) {
5137
6
    const BuiltinType *BT = EltType->getAs<BuiltinType>();
5138
6
    if ((EltType->isVectorType() && 
getContext().getTypeSize(EltType) == 1282
) ||
5139
6
        
(5
BT5
&&
BT->isFloatingPoint()4
))
5140
5
      AlignAsType = EltType;
5141
6
  }
5142
5143
  // Likewise for ELFv2 homogeneous aggregates.
5144
121
  const Type *Base = nullptr;
5145
121
  uint64_t Members = 0;
5146
121
  if (!AlignAsType && 
Kind == ELFv2116
&&
5147
121
      
isAggregateTypeForABI(Ty)88
&&
isHomogeneousAggregate(Ty, Base, Members)83
)
5148
43
    AlignAsType = Base;
5149
5150
  // With special case aggregates, only vector base types need alignment.
5151
121
  if (AlignAsType) {
5152
48
    bool UsesVector = AlignAsType->isVectorType() ||
5153
48
                      
FloatUsesVector(QualType(AlignAsType, 0))29
;
5154
48
    return CharUnits::fromQuantity(UsesVector ? 
1631
:
817
);
5155
48
  }
5156
5157
  // Otherwise, we only need alignment for any aggregate type that
5158
  // has an alignment requirement of >= 16 bytes.
5159
73