Coverage Report

Created: 2023-09-30 09:22

/Users/buildslave/jenkins/workspace/coverage/llvm-project/lldb/source/Plugins/Instruction/RISCV/RISCVCInstructions.h
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//===-- RISCVCInstructions.h ----------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLDB_SOURCE_PLUGINS_INSTRUCTION_RISCV_RISCVCINSTRUCTION_H
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#define LLDB_SOURCE_PLUGINS_INSTRUCTION_RISCV_RISCVCINSTRUCTION_H
11
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#include <cstdint>
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#include <variant>
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#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
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#include "RISCVInstructions.h"
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namespace lldb_private {
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/// Unified RISC-V C register encoding.
21
struct RxC {
22
  uint32_t rd;
23
  bool shift = true;
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19
  operator int() { return rd; }
25
27
  operator Rd() { return Rd{rd + (shift ? 
815
:
012
)}; }
26
45
  operator Rs() { return Rs{rd + (shift ? 
832
:
013
)}; }
27
};
28
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// decode register for RVC
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2
constexpr RxC DecodeCR_RD(uint32_t inst) { return RxC{DecodeRD(inst), false}; }
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14
constexpr RxC DecodeCI_RD(uint32_t inst) { return RxC{DecodeRD(inst), false}; }
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3
constexpr RxC DecodeCR_RS1(uint32_t inst) { return RxC{DecodeRD(inst), false}; }
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0
constexpr RxC DecodeCI_RS1(uint32_t inst) { return RxC{DecodeRD(inst), false}; }
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7
constexpr RxC DecodeCR_RS2(uint32_t inst) {
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7
  return RxC{(inst & 0x7C) >> 2, false};
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7
}
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19
constexpr RxC DecodeCIW_RD(uint32_t inst) { return RxC{(inst & 0x1C) >> 2}; }
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5
constexpr RxC DecodeCL_RD(uint32_t inst) { return RxC{DecodeCIW_RD(inst)}; }
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21
constexpr RxC DecodeCA_RD(uint32_t inst) { return RxC{(inst & 0x380) >> 7}; }
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3
constexpr RxC DecodeCB_RD(uint32_t inst) { return RxC{DecodeCA_RD(inst)}; }
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5
constexpr RxC DecodeCL_RS1(uint32_t inst) { return RxC{DecodeCA_RD(inst)}; }
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5
constexpr RxC DecodeCS_RS1(uint32_t inst) { return RxC{DecodeCA_RD(inst)}; }
45
0
constexpr RxC DecodeCA_RS1(uint32_t inst) { return RxC{DecodeCA_RD(inst)}; }
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2
constexpr RxC DecodeCB_RS1(uint32_t inst) { return RxC{DecodeCA_RD(inst)}; }
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5
constexpr RxC DecodeCSS_RS2(uint32_t inst) { return DecodeCR_RS2(inst); }
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5
constexpr RxC DecodeCS_RS2(uint32_t inst) { return RxC{DecodeCIW_RD(inst)}; }
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6
constexpr RxC DecodeCA_RS2(uint32_t inst) { return RxC{DecodeCIW_RD(inst)}; }
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1
RISCVInst DecodeC_LWSP(uint32_t inst) {
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1
  auto rd = DecodeCI_RD(inst);
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1
  uint16_t offset = ((inst << 4) & 0xc0)    // offset[7:6]
55
1
                    | ((inst >> 7) & 0x20)  // offset[5]
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1
                    | ((inst >> 2) & 0x1c); // offset[4:2]
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1
  if (rd == 0)
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0
    return RESERVED{inst};
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1
  return LW{rd, Rs{gpr_sp_riscv}, uint32_t(offset)};
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1
}
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1
RISCVInst DecodeC_LDSP(uint32_t inst) {
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1
  auto rd = DecodeCI_RD(inst);
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1
  uint16_t offset = ((inst << 4) & 0x1c0)   // offset[8:6]
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1
                    | ((inst >> 7) & 0x20)  // offset[5]
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1
                    | ((inst >> 2) & 0x18); // offset[4:3]
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1
  if (rd == 0)
68
0
    return RESERVED{inst};
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1
  return LD{rd, Rs{gpr_sp_riscv}, uint32_t(offset)};
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1
}
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1
RISCVInst DecodeC_SWSP(uint32_t inst) {
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1
  uint16_t offset = ((inst >> 1) & 0xc0)    // offset[7:6]
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1
                    | ((inst >> 7) & 0x3c); // offset[5:2]
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1
  return SW{Rs{gpr_sp_riscv}, DecodeCSS_RS2(inst), uint32_t(offset)};
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1
}
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1
RISCVInst DecodeC_SDSP(uint32_t inst) {
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1
  uint16_t offset = ((inst >> 1) & 0x1c0)   // offset[8:6]
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1
                    | ((inst >> 7) & 0x38); // offset[5:3]
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1
  return SD{Rs{gpr_sp_riscv}, DecodeCSS_RS2(inst), uint32_t(offset)};
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1
}
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1
RISCVInst DecodeC_LW(uint32_t inst) {
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1
  uint16_t offset = ((inst << 1) & 0x40)   // imm[6]
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1
                    | ((inst >> 7) & 0x38) // imm[5:3]
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1
                    | ((inst >> 4) & 0x4); // imm[2]
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1
  return LW{DecodeCL_RD(inst), DecodeCL_RS1(inst), uint32_t(offset)};
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1
}
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1
RISCVInst DecodeC_LD(uint32_t inst) {
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1
  uint16_t offset = ((inst << 1) & 0xc0)    // imm[7:6]
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1
                    | ((inst >> 7) & 0x38); // imm[5:3]
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1
  return LD{DecodeCL_RD(inst), DecodeCL_RS1(inst), uint32_t(offset)};
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1
}
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1
RISCVInst DecodeC_SW(uint32_t inst) {
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1
  uint16_t offset = ((inst << 1) & 0x40)   // imm[6]
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1
                    | ((inst >> 7) & 0x38) // imm[5:3]
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1
                    | ((inst >> 4) & 0x4); // imm[2]
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1
  return SW{DecodeCS_RS1(inst), DecodeCS_RS2(inst), uint32_t(offset)};
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1
}
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1
RISCVInst DecodeC_SD(uint32_t inst) {
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1
  uint16_t offset = ((inst << 1) & 0xc0)    // imm[7:6]
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1
                    | ((inst >> 7) & 0x38); // imm[5:3]
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1
  return SD{DecodeCS_RS1(inst), DecodeCS_RS2(inst), uint32_t(offset)};
108
1
}
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1
RISCVInst DecodeC_J(uint32_t inst) {
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1
  uint16_t offset = ((inst >> 1) & 0x800)   // offset[11]
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1
                    | ((inst << 2) & 0x400) // offset[10]
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1
                    | ((inst >> 1) & 0x300) // offset[9:8]
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1
                    | ((inst << 1) & 0x80)  // offset[7]
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1
                    | ((inst >> 1) & 0x40)  // offset[6]
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1
                    | ((inst << 3) & 0x20)  // offset[5]
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1
                    | ((inst >> 7) & 0x10)  // offset[4]
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1
                    | ((inst >> 2) & 0xe);  // offset[3:1]
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1
  if ((offset & 0x800) == 0)
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1
    return JAL{Rd{0}, uint32_t(offset)};
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0
  return JAL{Rd{0}, uint32_t(int32_t(int16_t(offset | 0xf000)))};
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1
}
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1
RISCVInst DecodeC_JR(uint32_t inst) {
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1
  auto rs1 = DecodeCR_RS1(inst);
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1
  if (rs1 == 0)
127
0
    return RESERVED{inst};
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1
  return JALR{Rd{0}, rs1, 0};
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1
}
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2
RISCVInst DecodeC_JALR(uint32_t inst) {
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2
  auto rs1 = DecodeCR_RS1(inst);
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2
  if (rs1 == 0)
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1
    return EBREAK{inst};
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1
  return JALR{Rd{1}, rs1, 0};
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2
}
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2
constexpr uint16_t BOffset(uint32_t inst) {
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2
  return ((inst >> 4) & 0x100)  // offset[8]
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2
         | ((inst << 1) & 0xc0) // offset[7:6]
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2
         | ((inst << 3) & 0x20) // offset[5]
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2
         | ((inst >> 7) & 0x18) // offset[4:3]
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2
         | ((inst >> 2) & 0x6); // offset[2:1]
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2
}
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1
RISCVInst DecodeC_BNEZ(uint32_t inst) {
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1
  auto rs1 = DecodeCB_RS1(inst);
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1
  uint16_t offset = BOffset(inst);
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1
  if ((offset & 0x100) == 0)
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1
    return B{rs1, Rs{0}, uint32_t(offset), 0b001};
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0
  return B{rs1, Rs{0}, uint32_t(int32_t(int16_t(offset | 0xfe00))), 0b001};
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1
}
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1
RISCVInst DecodeC_BEQZ(uint32_t inst) {
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1
  auto rs1 = DecodeCB_RS1(inst);
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1
  uint16_t offset = BOffset(inst);
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1
  if ((offset & 0x100) == 0)
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1
    return B{rs1, Rs{0}, uint32_t(offset), 0b000};
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0
  return B{rs1, Rs{0}, uint32_t(int32_t(int16_t(offset | 0xfe00))), 0b000};
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1
}
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1
RISCVInst DecodeC_LI(uint32_t inst) {
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1
  auto rd = DecodeCI_RD(inst);
164
1
  uint16_t imm = ((inst >> 7) & 0x20) | ((inst >> 2) & 0x1f);
165
1
  if ((imm & 0x20) == 0)
166
1
    return ADDI{rd, Rs{0}, uint32_t(imm)};
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0
  return ADDI{rd, Rs{0}, uint32_t(int32_t(int8_t(imm | 0xc0)))};
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1
}
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2
RISCVInst DecodeC_LUI_ADDI16SP(uint32_t inst) {
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2
  auto rd = DecodeCI_RD(inst);
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2
  if (rd == 0)
173
0
    return HINT{inst};
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2
  if (rd == 2) {
175
1
    uint16_t nzimm = ((inst >> 3) & 0x200)   // nzimm[9]
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1
                     | ((inst >> 2) & 0x10)  // nzimm[4]
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1
                     | ((inst << 1) & 0x40)  // nzimm[6]
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1
                     | ((inst << 4) & 0x180) // nzimm[8:7]
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1
                     | ((inst << 3) & 0x20); // nzimm[5]
180
1
    if (nzimm == 0)
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0
      return RESERVED{inst};
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1
    if ((nzimm & 0x200) == 0)
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0
      return ADDI{Rd{gpr_sp_riscv}, Rs{gpr_sp_riscv}, uint32_t(nzimm)};
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1
    return ADDI{Rd{gpr_sp_riscv}, Rs{gpr_sp_riscv},
185
1
                uint32_t(int32_t(int16_t(nzimm | 0xfc00)))};
186
1
  }
187
1
  uint32_t imm =
188
1
      ((uint32_t(inst) << 5) & 0x20000) | ((uint32_t(inst) << 10) & 0x1f000);
189
1
  if ((imm & 0x20000) == 0)
190
0
    return LUI{rd, imm};
191
1
  return LUI{rd, uint32_t(int32_t(imm | 0xfffc0000))};
192
1
}
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2
RISCVInst DecodeC_ADDI(uint32_t inst) {
195
2
  auto rd = DecodeCI_RD(inst);
196
2
  if (rd == 0)
197
1
    return NOP{inst};
198
1
  uint16_t imm = ((inst >> 7) & 0x20) | ((inst >> 2) & 0x1f);
199
1
  if ((imm & 0x20) == 0)
200
0
    return ADDI{rd, rd, uint32_t(imm)};
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1
  return ADDI{rd, rd, uint32_t(int32_t(int8_t(imm | 0xc0)))};
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1
}
203
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1
RISCVInst DecodeC_ADDIW(uint32_t inst) {
205
1
  auto rd = DecodeCI_RD(inst);
206
1
  if (rd == 0)
207
0
    return RESERVED{inst};
208
1
  uint16_t imm = ((inst >> 7) & 0x20) | ((inst >> 2) & 0x1f);
209
1
  if ((imm & 0x20) == 0)
210
1
    return ADDIW{rd, rd, uint32_t(imm)};
211
0
  return ADDIW{rd, rd, uint32_t(int32_t(int8_t(imm | 0xc0)))};
212
1
}
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214
3
RISCVInst DecodeC_ADDI4SPN(uint32_t inst) {
215
3
  auto rd = DecodeCIW_RD(inst);
216
3
  uint16_t nzuimm = ((inst >> 1) & 0x3c0)  // nzuimm[9:6]
217
3
                    | ((inst >> 7) & 0x30) // nzuimm[5:4]
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3
                    | ((inst >> 2) & 0x8)  // nzuimm[3]
219
3
                    | ((inst >> 4) & 0x4); // nzuimm[2]
220
221
3
  if (rd == 0 && 
nzuimm == 01
)
222
1
    return INVALID{inst};
223
2
  if (nzuimm == 0)
224
1
    return RESERVED{inst};
225
1
  return ADDI{rd, Rs{gpr_sp_riscv}, uint32_t(nzuimm)};
226
2
}
227
228
3
RISCVInst DecodeC_SLLI(uint32_t inst) {
229
3
  auto rd = DecodeCI_RD(inst);
230
3
  uint16_t shamt = ((inst >> 7) & 0x20) | ((inst >> 2) & 0x1f);
231
3
  if (rd == 0 || 
shamt == 02
)
232
2
    return HINT{inst};
233
1
  return SLLI{rd, rd, uint8_t(shamt)};
234
3
}
235
236
1
RISCVInst DecodeC_SRLI(uint32_t inst) {
237
1
  auto rd = DecodeCB_RD(inst);
238
1
  uint16_t shamt = ((inst >> 7) & 0x20) | ((inst >> 2) & 0x1f);
239
1
  if (shamt == 0)
240
0
    return HINT{inst};
241
1
  return SRLI{rd, rd, uint8_t(shamt)};
242
1
}
243
244
1
RISCVInst DecodeC_SRAI(uint32_t inst) {
245
1
  auto rd = DecodeCB_RD(inst);
246
1
  uint16_t shamt = ((inst >> 7) & 0x20) | ((inst >> 2) & 0x1f);
247
1
  if (shamt == 0)
248
0
    return HINT{inst};
249
1
  return SRAI{rd, rd, uint8_t(shamt)};
250
1
}
251
252
1
RISCVInst DecodeC_ANDI(uint32_t inst) {
253
1
  auto rd = DecodeCB_RD(inst);
254
1
  uint16_t imm = ((inst >> 7) & 0x20) | ((inst >> 2) & 0x1f);
255
1
  if ((imm & 0x20) == 0)
256
1
    return ANDI{rd, rd, uint32_t(imm)};
257
0
  return ANDI{rd, rd, uint32_t(int32_t(int8_t(imm | 0xc0)))};
258
1
}
259
260
1
RISCVInst DecodeC_MV(uint32_t inst) {
261
1
  auto rd = DecodeCR_RD(inst);
262
1
  auto rs2 = DecodeCR_RS2(inst);
263
1
  if (rd == 0)
264
0
    return HINT{inst};
265
1
  return ADD{rd, Rs{0}, rs2};
266
1
}
267
268
1
RISCVInst DecodeC_ADD(uint32_t inst) {
269
1
  auto rd = DecodeCR_RD(inst);
270
1
  return ADD{rd, rd, DecodeCR_RS2(inst)};
271
1
}
272
273
1
RISCVInst DecodeC_AND(uint32_t inst) {
274
1
  auto rd = DecodeCA_RD(inst);
275
1
  return AND{rd, rd, DecodeCA_RS2(inst)};
276
1
}
277
278
1
RISCVInst DecodeC_OR(uint32_t inst) {
279
1
  auto rd = DecodeCA_RD(inst);
280
1
  return OR{rd, rd, DecodeCA_RS2(inst)};
281
1
}
282
283
1
RISCVInst DecodeC_XOR(uint32_t inst) {
284
1
  auto rd = DecodeCA_RD(inst);
285
1
  return XOR{rd, rd, DecodeCA_RS2(inst)};
286
1
}
287
288
1
RISCVInst DecodeC_SUB(uint32_t inst) {
289
1
  auto rd = DecodeCA_RD(inst);
290
1
  return SUB{rd, rd, DecodeCA_RS2(inst)};
291
1
}
292
293
1
RISCVInst DecodeC_SUBW(uint32_t inst) {
294
1
  auto rd = DecodeCA_RD(inst);
295
1
  return SUBW{rd, rd, DecodeCA_RS2(inst)};
296
1
}
297
298
1
RISCVInst DecodeC_ADDW(uint32_t inst) {
299
1
  auto rd = DecodeCA_RD(inst);
300
1
  return ADDW{rd, rd, DecodeCA_RS2(inst)};
301
1
}
302
1
RISCVInst DecodeC_FLW(uint32_t inst) {
303
1
  uint16_t offset = ((inst << 1) & 0x40)   // imm[6]
304
1
                    | ((inst >> 7) & 0x38) // imm[5:3]
305
1
                    | ((inst >> 4) & 0x4); // imm[2]
306
1
  return FLW{DecodeCL_RD(inst), DecodeCL_RS1(inst), uint32_t(offset)};
307
1
}
308
309
1
RISCVInst DecodeC_FSW(uint32_t inst) {
310
1
  uint16_t offset = ((inst << 1) & 0x40)   // imm[6]
311
1
                    | ((inst >> 7) & 0x38) // imm[5:3]
312
1
                    | ((inst >> 4) & 0x4); // imm[2]
313
1
  return FSW{DecodeCS_RS1(inst), DecodeCS_RS2(inst), uint32_t(offset)};
314
1
}
315
316
1
RISCVInst DecodeC_FLWSP(uint32_t inst) {
317
1
  auto rd = DecodeCI_RD(inst);
318
1
  uint16_t offset = ((inst << 4) & 0xc0)    // offset[7:6]
319
1
                    | ((inst >> 7) & 0x20)  // offset[5]
320
1
                    | ((inst >> 2) & 0x1c); // offset[4:2]
321
1
  return FLW{rd, Rs{gpr_sp_riscv}, uint32_t(offset)};
322
1
}
323
324
1
RISCVInst DecodeC_FSWSP(uint32_t inst) {
325
1
  uint16_t offset = ((inst >> 1) & 0xc0)    // offset[7:6]
326
1
                    | ((inst >> 7) & 0x3c); // offset[5:2]
327
1
  return FSW{Rs{gpr_sp_riscv}, DecodeCSS_RS2(inst), uint32_t(offset)};
328
1
}
329
330
2
RISCVInst DecodeC_FLDSP(uint32_t inst) {
331
2
  auto rd = DecodeCI_RD(inst);
332
2
  uint16_t offset = ((inst << 4) & 0x1c0)   // offset[8:6]
333
2
                    | ((inst >> 7) & 0x20)  // offset[5]
334
2
                    | ((inst >> 2) & 0x18); // offset[4:3]
335
2
  return FLD{rd, Rs{gpr_sp_riscv}, uint32_t(offset)};
336
2
}
337
338
2
RISCVInst DecodeC_FSDSP(uint32_t inst) {
339
2
  uint16_t offset = ((inst >> 1) & 0x1c0)   // offset[8:6]
340
2
                    | ((inst >> 7) & 0x38); // offset[5:3]
341
2
  return FSD{Rs{gpr_sp_riscv}, DecodeCSS_RS2(inst), uint32_t(offset)};
342
2
}
343
344
2
RISCVInst DecodeC_FLD(uint32_t inst) {
345
2
  uint16_t offset = ((inst << 1) & 0xc0)    // imm[7:6]
346
2
                    | ((inst >> 7) & 0x38); // imm[5:3]
347
2
  return FLD{DecodeCL_RD(inst), DecodeCL_RS1(inst), uint32_t(offset)};
348
2
}
349
350
2
RISCVInst DecodeC_FSD(uint32_t inst) {
351
2
  uint16_t offset = ((inst << 1) & 0xc0)    // imm[7:6]
352
2
                    | ((inst >> 7) & 0x38); // imm[5:3]
353
2
  return FSD{DecodeCS_RS1(inst), DecodeCS_RS2(inst), uint32_t(offset)};
354
2
}
355
356
} // namespace lldb_private
357
#endif // LLDB_SOURCE_PLUGINS_INSTRUCTION_RISCV_RISCVCINSTRUCTION_H